JPS6354227B2 - - Google Patents
Info
- Publication number
- JPS6354227B2 JPS6354227B2 JP56183396A JP18339681A JPS6354227B2 JP S6354227 B2 JPS6354227 B2 JP S6354227B2 JP 56183396 A JP56183396 A JP 56183396A JP 18339681 A JP18339681 A JP 18339681A JP S6354227 B2 JPS6354227 B2 JP S6354227B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- etching
- mask
- wiring pattern
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 37
- 239000011229 interlayer Substances 0.000 description 15
- 238000005468 ion implantation Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 11
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 239000004020 conductor Substances 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- -1 titanium/tungsten Chemical compound 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- UDKYUQZDRMRDOR-UHFFFAOYSA-N tungsten Chemical compound [W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W] UDKYUQZDRMRDOR-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は、ゲート電極をマスクとしてイオン注
入を行う電界効果トランジスタ素子を含む半導体
装置について、該ゲート電極にもイオンが注入さ
れることに起因する問題点を排除する製造方法の
改善に関する。Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a semiconductor device including a field effect transistor element in which ions are implanted using a gate electrode as a mask. This invention relates to improvements in manufacturing methods that eliminate the problems associated with manufacturing.
(2) 技術の背景
半導体装置特に集積回路において、トランジス
タ、ダイオード等の電極もしくは引出電極間を接
続する配線パターンは、しばしば一部の電極と同
一導体膜から形成される。またこれらの一の配線
が他の配線と交叉することがしばしば必要とされ
るが、この場合にはその電極・配線パターンは通
常二層以上の導体膜を用いて形成される。(2) Background of the Technology In semiconductor devices, especially integrated circuits, wiring patterns that connect electrodes or extraction electrodes of transistors, diodes, etc. are often formed from the same conductive film as some of the electrodes. Further, it is often necessary for one of these wirings to cross another wiring, and in this case, the electrode/wiring pattern is usually formed using two or more layers of conductor films.
すなわちまず第一層の導体膜に所要のパターニ
ングを施して電極・配線パターンの第一層を形成
し、その上に例えば二酸化シリコン（SiO2）、窒
化シリコン（Si3N4）等よりなる層間絶縁膜を形
成してこれに所要の開口を設ける。次いで第二層
の導体膜を設け、所要のパターニングを施して電
極・配線パターンの第二層を形成することによ
り、層間絶縁膜により交叉する配線相互間が絶縁
され、所要の接続が層間絶縁膜の開口においてな
される電極・配線パターンが形成される。 That is, first, the first layer of conductive film is patterned to form a first layer of electrode/wiring patterns, and then an interlayer of silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), etc. is formed on top of that. An insulating film is formed and required openings are provided therein. Next, a second layer of conductive film is provided and required patterning is performed to form a second layer of electrode/wiring patterns, thereby insulating the intersecting wires with the interlayer insulating film and making the necessary connections through the interlayer insulating film. An electrode/wiring pattern is formed in the opening.
(3) 従来技術と問題点
前記の如く電極・配線パターンを交叉させる場
合において、第一層の電極・配線によりその上に
形成された層間絶縁膜に段差を生じ、第二層の配
線パターンは一般にこの段差を横断する形状とな
るから、段差のエツジ部分で第二層の配線パター
ンの断線を生じ易い。(3) Prior art and problems When the electrodes and wiring patterns intersect as described above, the electrodes and wiring in the first layer create a step in the interlayer insulating film formed thereon, and the wiring pattern in the second layer Since the shape generally crosses this step, the second layer wiring pattern is likely to be disconnected at the edge of the step.
この断線に対する対策として、層間絶縁膜の凹
凸部分を絶縁膜で埋め込んで段差をなくする樹脂
膜コート法と呼ばれる方法、或いは層間絶縁膜を
酸化ゲルマニウム（GeO2）を含んだ燐珪酸ガラ
スによつて形成し、これに高温熱処理を施してそ
の形状を滑らかにする方法等が従来実施されてい
る。 As a countermeasure against this disconnection, there is a method called the resin film coating method in which uneven parts of the interlayer insulating film are filled with an insulating film to eliminate the level difference, or the interlayer insulating film is made of phosphosilicate glass containing germanium oxide (GeO 2 ). Conventionally, a method has been practiced in which the shape is smoothed by forming the shape and subjecting it to high-temperature heat treatment to make the shape smooth.
これらの既に知られている高温熱処理を含む方
法は、高温熱処理に比較的に耐えるシリコン
（Si）を半導体材料とする場合には容易に活用で
きるが、例えばガリウム砒素（GaAs）等の化合
物半導体材料による半導体装置の製造工程におい
ては、結晶特性の劣化を発生させることなく450
℃程度以上の高温熱処理を長時間施すことは非常
に困難であるために、前記方法に代る新しい製造
方法が必要とされる。 These already known methods involving high-temperature heat treatment can be easily utilized when the semiconductor material is silicon (Si), which is relatively resistant to high-temperature heat treatment, but for example, when using compound semiconductor materials such as gallium arsenide (GaAs). In the manufacturing process of semiconductor devices using
Since it is very difficult to perform high-temperature heat treatment at a temperature of about 0.degree. C. or higher for a long time, a new manufacturing method is needed to replace the above method.
またGaAs等の化合物半導体装置においてはシ
ヨツトキバリア形電界効果トランジスタ素子が多
く用いられ、そのゲート電極をマスクとしてソー
ス及びドレイン領域に不純物イオン注入を行うセ
ルフアライメント（Self alignment）法により特
性が顕著に改善されるが、この製造方法では、シ
ヨツトキバリア形ゲート電極及び第一層配線とす
る導体膜は、注入した不純物を活性化する熱処理
で半導体基板との間に金属学的反応を生ぜずシヨ
ツトキバリアが保存されることが必要で、例えば
タングステン・シリサイド、チタン／タングステ
ン・シリサイド等の高融点金属珪化物が適してお
り、イオン注入する不純物は例えばSiとし、ゲー
ト電極・第一層配線パターン上に設ける層間絶縁
膜は例えば二酸化シリコン（SiO2）とすること
が最も普通である。 In addition, Schottky barrier field effect transistor elements are often used in compound semiconductor devices such as GaAs, and their characteristics have been significantly improved by a self-alignment method in which impurity ions are implanted into the source and drain regions using the gate electrode as a mask. However, in this manufacturing method, the shot barrier type gate electrode and the conductive film used as the first layer wiring are heat-treated to activate the implanted impurities, so that no metallurgical reaction occurs with the semiconductor substrate and the shot barrier is preserved. For example, high melting point metal silicides such as tungsten silicide and titanium/tungsten silicide are suitable, and the impurity to be ion-implanted is, for example, Si, and the interlayer insulating film provided on the gate electrode and first layer wiring pattern is suitable. is most commonly, for example, silicon dioxide (SiO 2 ).
この製造方法では、マスクとしたゲート電極に
もSiなどの不純物が注入され、その表面の例えば
厚さ数10Å程度の部分はSiが過剰となり、損傷が
発生している。この上に層間絶縁膜をCVD法に
よりSiO2などで設けるとき、成長条件によつて
はゲート電極等の面上でこれが異常成長し段差が
拡大されて、第二層の導体膜が十分に成長せず、
或いはパターニングを施し得ないなどの障害の危
険性が増大する。更にこの表面層は第二層配線と
の間のコンタクト抵抗を上昇させる要因ともな
り、半導体装置、特に第二層配線の信頼度を著し
く低下させる。 In this manufacturing method, impurities such as Si are also implanted into the gate electrode used as a mask, and a portion of the surface with a thickness of, for example, several tens of angstroms contains excess Si, causing damage. When an interlayer insulating film is formed using SiO 2 or the like using the CVD method, depending on the growth conditions, this may grow abnormally on the surface of the gate electrode, etc., enlarging the step, and preventing the second layer conductor film from growing sufficiently. Without,
Alternatively, the risk of problems such as not being able to perform patterning increases. Furthermore, this surface layer also causes an increase in the contact resistance with the second layer wiring, which significantly lowers the reliability of the semiconductor device, especially the second layer wiring.
(4) 発明の目的
本発明は、ゲート電極をマスクとしてイオン注
入を行う電界効果トランジスタ素子を含む半導体
装置について、該ゲート電極にもイオンが注入さ
れることに起因する半導体装置、特に第二層配線
の信頼度低下を排除することを目的とする。(4) Purpose of the Invention The present invention relates to a semiconductor device including a field effect transistor element in which ions are implanted using a gate electrode as a mask, and particularly relates to a semiconductor device including a field effect transistor element in which ions are implanted using the gate electrode as a mask. The purpose is to eliminate deterioration in wiring reliability.
(5) 発明の構成
本発明の前記目的は、電界効果トランジスタ素
子のソース及びドレインとする領域に、該素子の
ゲート電極をマスクとして不純物のイオン注入を
行う工程と、該素子形成面に垂直方向の効果が平
面方向より大きい異方性エツチング処理により、
該ゲート電極の該不純物が注入された部分を除去
する工程と、該素子形成面上にCVD法により絶
縁層を形成する工程と、該絶縁層上に配線を形成
する工程とを有する半導体装置の製造方法により
達成される。(5) Structure of the Invention The above object of the present invention is to provide a step of implanting impurity ions into the source and drain regions of a field effect transistor element using the gate electrode of the element as a mask, and a step of implanting impurity ions in a direction perpendicular to the element forming surface. The anisotropic etching process has a greater effect than in the planar direction.
A semiconductor device comprising: removing a portion of the gate electrode into which the impurity is implanted; forming an insulating layer on the element formation surface by CVD; and forming a wiring on the insulating layer. This is achieved by a manufacturing method.
(6) 発明の実施例
以下に本発明を実施例により、図面を参照して
具体的に説明する。(6) Examples of the invention The present invention will be specifically described below using examples with reference to the drawings.
第１図乃至第９図はGaAs集積回路における本
発明の第一の実施例、第１０図乃至第１４図は第
一の実施例を部分的に変更した第二の実施例、第
１５図乃至第１７図は第二の実施例を部分的に変
更した第三の実施例を示す断面図であり、各図を
通じて同一符号は同一対象部分を示す。また第１
８図は本実施例のゲート電極のエツチングを説明
する模式断面図である。 FIGS. 1 to 9 show a first embodiment of the present invention in a GaAs integrated circuit, FIGS. 10 to 14 show a second embodiment partially modified from the first embodiment, and FIGS. FIG. 17 is a sectional view showing a third embodiment which is a partial modification of the second embodiment, and the same reference numerals indicate the same target parts throughout the figures. Also the first
FIG. 8 is a schematic cross-sectional view illustrating the etching of the gate electrode in this example.
第１図に示す如く、半絶縁性GaAs基板１上に
例えばSiO2によりマスク２を設けて、Siもしく
は錫（Sn）等の選択的イオン注入を行い、温度
700℃乃至900℃程度の酸素を含まない雰囲気中で
15分間程度の熱処理を施してｎ型活性層３を形成
する。 As shown in FIG. 1, a mask 2 made of, for example, SiO 2 is provided on a semi-insulating GaAs substrate 1, and selective ions such as Si or tin (Sn) are implanted.
In an oxygen-free atmosphere at approximately 700℃ to 900℃
A heat treatment is performed for about 15 minutes to form an n-type active layer 3.
次に第２図に示す如く、前記選択的イオン注入
に用いたマスク２を除去し、基板１の全表面にゲ
ート電極及び第一層配線の材料となる高融点金属
珪化物、例えばチタン／タングステン・シリサイ
ドよりなる第一の導体膜４を、厚さ600nm程度に
スパツタ法もしくはMO―CVD法等により形成
する。 Next, as shown in FIG. 2, the mask 2 used for the selective ion implantation is removed, and a high melting point metal silicide, such as titanium/tungsten, which will be the material for the gate electrode and the first layer wiring, is applied to the entire surface of the substrate 1. - A first conductor film 4 made of silicide is formed to a thickness of about 600 nm by sputtering or MO-CVD.
次に第３図に示す如く、前記導体膜４にゲート
電極及び第一層配線のパターニングを行うための
マスク５をSiO2等により形成する。このマスク
５の形成は、CVD法等により形成されたSiO2膜
上に一旦レジストよりなるマスク（図には表示を
省略）を設け、ドライもしくはウエツトエツチン
グを施すものである。 Next, as shown in FIG. 3, a mask 5 made of SiO 2 or the like is formed on the conductor film 4 for patterning the gate electrode and the first layer wiring. The mask 5 is formed by first providing a resist mask (not shown in the figure) on the SiO 2 film formed by CVD or the like, and then performing dry or wet etching.
次いで前記導体膜４をエツチングし、ゲート電
極６及び第一層の配線パターン７を形成するが、
その肩の部分を丸みをおびた滑らかな形状とし、
かつゲート電極６の断面形状が裾広がりの台形と
なりイオン注入のマスク効果の不完全な領域を生
ずることを防止するために、本実施例では、化学
反応によるリアクテイブ・エツチング効果と、イ
オン・エツチング技術の物質である異方性エツチ
ング効果とを有するリアクテイブイオン・エツチ
ング処理を適用し、かつ第１８図ａ、ｂに模式的
に示す如く、条件が異なる２回のエツチング処理
を下記の様に実施する。 Next, the conductor film 4 is etched to form a gate electrode 6 and a first layer wiring pattern 7.
The shoulder part has a rounded and smooth shape,
In addition, in order to prevent the cross-sectional shape of the gate electrode 6 from becoming a trapezoid with a widening base, resulting in an area where the mask effect of ion implantation is incomplete, this embodiment uses a reactive etching effect due to a chemical reaction and an ion etching technique. A reactive ion etching process having an anisotropic etching effect using a material of do.
すなわち第一のエツチング処理ではエツチング
速度を考慮してガス圧力はさほど低くせず、バイ
アス電圧を高めて垂直方向の方向性を強めてお
り、第１８図ａの如く、従来技術よりサイドエツ
チングが少ないが、なお裾が広がつた台形となつ
ている。 In other words, in the first etching process, the gas pressure is not so low in consideration of the etching speed, and the bias voltage is increased to strengthen the vertical directionality, resulting in less side etching than in the conventional technique, as shown in Figure 18a. However, it still has a trapezoidal shape with the hem widening.
次いで第二のエツチング処理では高真空リアク
テイブイオン・エツチング技術を用いて更に垂直
方向の異方性を強め、かつマスク５を除去して、
第１８図ｂに示す如く、ゲート電極６の裾の部分
を除去するとともにそのパターンの肩の部分のエ
ツチングを進行させる。なお半導体基体の損傷を
考慮して、通常前記第一のエツチングよりバイア
ス電圧を低くする。 Next, in the second etching process, the vertical anisotropy is further strengthened using high vacuum reactive ion etching technology, and the mask 5 is removed.
As shown in FIG. 18b, the bottom portion of the gate electrode 6 is removed and the shoulder portion of the pattern is etched. Note that in consideration of damage to the semiconductor substrate, the bias voltage is usually lower than that in the first etching.
なおこのリアクテイブイオン・エツチング処理
には平行平板型装置が適しており、また導体膜４
に例えばチタン／タングステン・シリサイドを用
いた本実施例では、炭火水素の弗素を主とするフ
ルオルクロル置換体、例えば四弗化炭素（CF4）
を主成分とするガスがエツチヤントに適する。 A parallel plate type device is suitable for this reactive ion etching process, and the conductor film 4
For example, in this example, titanium/tungsten silicide is used as a fluorine-substituted fluorine-substituted hydrocarbon, such as carbon tetrafluoride (CF 4 ).
A gas containing as the main component is suitable as an etchant.
すなわち本実施例では、第４図に示す如き前記
導体膜４からゲート電極６及び第一層の配線パタ
ーン７を形成する前記第一のエツチングを、例え
ば下記例の如き条件のリアクテイブイオン・エツ
チング法により、サイドエツチングがさほど進行
しない程度に実施する。 That is, in this embodiment, the first etching for forming the gate electrode 6 and the first layer wiring pattern 7 from the conductor film 4 as shown in FIG. According to the method, the side etching should be carried out to the extent that side etching does not progress much.
エツチヤントガス組成：
CF4＋He＝80sccm＋20sccm
エツチヤントガス圧力： 2pa
セルフバイアス電圧： 140V
高周波電力： 100W
エツチング速度： 約200Å／分
次に第５図に示す如く、前記マスク５を除去し
た後に例えば下記例の如き条件で垂直方向に異方
性を強めた前記第二のエツチングを実施し、前記
ゲート電極６及び配線パターン７の裾の部分を除
去するとともにその肩の部分を丸みをおびた滑ら
かな形状とする断面形状の整形を行う。 Etchant gas composition: CF 4 +He=80sccm+20sccm Etchant gas pressure: 2pa Self-bias voltage: 140V High frequency power: 100W Etching rate: Approximately 200 Å/min Next, as shown in FIG. 5, after removing the mask 5, the following conditions are applied. The second etching is performed to increase the anisotropy in the vertical direction, and the bottom portions of the gate electrode 6 and the wiring pattern 7 are removed, and the shoulder portions are made into a rounded and smooth cross section. Perform shape shaping.
エツチヤントガス組成：
CF4＝100sccm
エツチヤントガス圧力： 0.5pa
セルフバイアス電圧： 100V
高周波電力： 50W
エツチング速度： 約100Å／分
次に第６図に示す如く、ソース高濃度領域及び
ドレイン高濃度領域の形成を行う。すなわちレジ
ストを塗布し、イオン注入を行う範囲に開口を設
けるパターニングを施してマスク８を形成した後
に、ゲート電極６及び該マスク８をマスクとし
て、SiもしくはSn等の選択的イオン注入を行い、
前記と同様の熱処理を施して、キヤリア濃度が表
面で３×1017cm-3程度のソース高濃度領域９及び
ドレイン高濃度領域１０が形成される。 Etchant gas composition: CF 4 =100 sccm Etchant gas pressure: 0.5 pa Self-bias voltage: 100 V High frequency power: 50 W Etching rate: Approximately 100 Å/min Next, as shown in Figure 6, a source high concentration region and a drain high concentration region are formed. . That is, after coating a resist and performing patterning to provide an opening in the ion implantation range to form a mask 8, selective ion implantation of Si, Sn, etc. is performed using the gate electrode 6 and the mask 8 as a mask.
By performing the same heat treatment as described above, a high concentration source region 9 and a high concentration drain region 10 having a carrier concentration of about 3×10 17 cm −3 at the surface are formed.
次に第７図に示す如くマスク８を除去して、ゲ
ート電極６に、本実施例では同時に配線パターン
７にも第三のエツチングを施し、第１８図ｃに示
す如くその表面の厚さ例えば10〜100Å程度の部
分を除去する。 Next, as shown in FIG. 7, the mask 8 is removed, and a third etching is applied to the gate electrode 6, and in this embodiment, the wiring pattern 7 at the same time. A portion of about 10 to 100 Å is removed.
このイオン注入後にゲート電極６に施す第三の
エツチングは、例えば前記第二のエツチングと同
様な条件で効果が垂直方向に大きい異方性リアク
テイブイオン・エツチング法を適用して、その表
面の前記イオン注入の結果Siが過剰となり損傷が
発生している部分を除去するもので、後段の工程
で形成するCVD法によるSiO2等の層間絶縁膜の
段差拡大、第二層配線との間のコンタクト抵抗の
上昇という上述の問題点を防止する効果を有す
る。 The third etching performed on the gate electrode 6 after this ion implantation is performed by applying an anisotropic reactive ion etching method, which has a large effect in the vertical direction, under the same conditions as the second etching, and etching the surface of the gate electrode 6. This process removes the damaged areas due to excess Si as a result of ion implantation, and increases the step difference in the interlayer insulating film such as SiO 2 using the CVD method, which will be formed in the later process, and makes contact with the second layer wiring. This has the effect of preventing the above-mentioned problem of increased resistance.
前記第三のエツチング後に、例えば金・ゲルマ
ニウム・金を蒸着してソース電極１１及びドレイ
ン電極１２を形成する。 After the third etching, the source electrode 11 and the drain electrode 12 are formed by depositing gold, germanium, and gold, for example.
次に第８図に示す如く層間絶縁膜１３を設け
る。この層間絶縁膜１３は例えばCVD法による
SiO2とし、厚さ600nm程度とする。本実施例に
おいては以上説明した如く、ゲート電極６及び配
線パターン７の肩の部分が丸みをおびた滑らかな
形状に整形され、更にイオン注入後にもゲート電
極６の表面がエツチングされているために、この
層間絶縁膜１３はゲート電極６或いは配線パター
ン７上の段差部分においても滑らかな形状とな
る。 Next, as shown in FIG. 8, an interlayer insulating film 13 is provided. This interlayer insulating film 13 is formed by, for example, the CVD method.
It is made of SiO 2 and has a thickness of about 600 nm. In this embodiment, as explained above, the shoulder portions of the gate electrode 6 and wiring pattern 7 are shaped into rounded and smooth shapes, and the surface of the gate electrode 6 is etched even after ion implantation. , this interlayer insulating film 13 has a smooth shape even at the step portion on the gate electrode 6 or wiring pattern 7.
次に第９図に示す如く、前記層間絶縁膜１３に
所要の開口、例えば１４及び１５をリソグラフイ
法により設けた後、第二層の導体膜を形成し、所
要のパターニングを実施して第二層の配線パター
ン１６を得る。 Next, as shown in FIG. 9, after forming required openings, e.g. 14 and 15, in the interlayer insulating film 13 by lithography, a second layer of conductive film is formed, and required patterning is performed. A two-layer wiring pattern 16 is obtained.
この第二層の配線パターン１６の形成は第４図
を参照して説明した第一層の配線パターン７の形
成方法に準じて実施することが可能であつて、更
に第三層の配線パターンを設けるなど、第二層の
配線パターン１６の整形を必要とする場合には、
第二層の配線パターン１６形成のためのマスク除
去後に、第５図を参照して説明したエツチングを
重ねて実施する。 The formation of the second layer wiring pattern 16 can be carried out according to the method of forming the first layer wiring pattern 7 described with reference to FIG. When it is necessary to shape the second layer wiring pattern 16, such as when
After removing the mask for forming the second layer wiring pattern 16, the etching described with reference to FIG. 5 is repeated.
以上説明した第一の実施例を部分的に変更した
第二の実施例について、第１０図乃至第１４図を
参照して説明する。 A second embodiment, which is a partial modification of the first embodiment described above, will be described with reference to FIGS. 10 to 14.
第一の実施例について第４図を参照して説明し
たゲート電極６及び第一層の配線パターン７の形
成後、ゲート電極６のマスク５を除去し、第一層
の配線パターン７のマスク５については少なくと
もその一部を残置する。この状態のウエーハにつ
いて第１０図に示す如く、前記第一の実施例と同
様の条件で第二のエツチングを行う。この際にマ
スク５が残置された配線パターン７は上面がエツ
チングされず、側面も殆どエツチングされない。 After forming the gate electrode 6 and the first layer wiring pattern 7 described in the first embodiment with reference to FIG. 4, the mask 5 of the gate electrode 6 is removed, and the mask 5 of the first layer wiring pattern 7 is removed. At least part of it will remain. As shown in FIG. 10, the wafer in this state is subjected to a second etching process under the same conditions as in the first embodiment. At this time, the upper surface of the wiring pattern 7 where the mask 5 remains is not etched, and the side surfaces are also hardly etched.
次に第１１図に示す如く、レジストを塗布しイ
オン注入を行う範囲に開口を設けるパターニング
を施してマスク８を形成した後に、ゲート電極６
及びマスク８をマスクとしてSi等の選択的イオン
注入を行い、前記と同様の熱処理を施して、キヤ
リア濃度が表面で３×1017cm-3程度のソース高濃
度領域９及びドレイン高濃度領域１０が形成され
る。 Next, as shown in FIG. 11, a resist is applied and patterned to form an opening in the ion implantation range to form a mask 8, and then a gate electrode 6 is formed.
Then, selective ion implantation of Si or the like is performed using the mask 8 as a mask, and the same heat treatment as described above is performed to form a source high concentration region 9 and a drain high concentration region 10 with a carrier concentration of about 3×10 17 cm -3 at the surface. is formed.
次に第１２図に示す如く、イオン注入のマスク
８及び配線パターン７のエツチング・マスク５を
除去した後に、ゲート電極６及び配線パターン７
に例えば前記第一の実施例の第三のエツチングと
同一条件で第三のエツチングを実施する。 Next, as shown in FIG. 12, after removing the ion implantation mask 8 and the etching mask 5 of the wiring pattern 7, the gate electrode 6 and the wiring pattern 7 are removed.
For example, a third etching is performed under the same conditions as the third etching in the first embodiment.
ここで行われる第三のエツチングは、ゲート電
極６については第一の実施例の場合と同じくイオ
ン注入の結果Siが過剰となり損傷が発生している
部分を除去するもので、層間絶縁膜の段差拡大
と、第二層配線との間のコンクタト抵抗上昇を防
止する効果を有する。 The third etching performed here is to remove the portion of the gate electrode 6 where damage has occurred due to excessive Si as a result of ion implantation, as in the first embodiment, and removes the step of the interlayer insulating film. This has the effect of preventing an increase in contact resistance between the expansion and the second layer wiring.
他方配線パターン７については、そのエツジ部
分を丸みをおびた滑らかな形状とする効果を与え
る。本実施例においては第１０図を参照して説明
した第二のエツチング処理による配線パターン７
の断面積の減少が殆どなく、今回の第三のエツチ
ング処理後においても第一の実施例に比較して大
きい断面積の、側端面がやや傾斜した配線パター
ン７が得られる。 On the other hand, the wiring pattern 7 has the effect of making its edges rounded and smooth. In this embodiment, the wiring pattern 7 is formed by the second etching process described with reference to FIG.
There is almost no decrease in the cross-sectional area, and even after the third etching process, a wiring pattern 7 having a larger cross-sectional area than the first embodiment and whose side end surfaces are slightly inclined can be obtained.
前記第三のエツチング後に、ソース電極１１及
びドレイン電極１２を形成する。 After the third etching, a source electrode 11 and a drain electrode 12 are formed.
次いで第１３図及び第１４図に示す如く、第一
の実施例と同様に絶縁層１３、第二層の配線パタ
ーン１６の形成を行う。 Next, as shown in FIGS. 13 and 14, an insulating layer 13 and a second layer wiring pattern 16 are formed in the same manner as in the first embodiment.
更に第二の実施例を部分的に変更した第三の実
施例について、第１５図乃至第１７図を参照して
説明する。 Furthermore, a third embodiment, which is a partial modification of the second embodiment, will be described with reference to FIGS. 15 to 17.
第二の実施例について第１１図を参照して説明
したソース高濃度領域９及びドレイン高濃度領域
１０の形成後、第１５図に示す如くイオン注入の
マスク８を除去し、配線パターン７のエツチン
グ・マスク５は残置して、ゲート電極６及び配線
パターン７に第三のエツチングを実施し、その後
ソース電極１１及びドレイン電極１２を形成す
る。 After forming the high concentration source region 9 and the high concentration drain region 10 described with reference to FIG. 11 for the second embodiment, the ion implantation mask 8 is removed as shown in FIG. 15, and the wiring pattern 7 is etched. - Third etching is performed on the gate electrode 6 and wiring pattern 7 with the mask 5 left in place, and then the source electrode 11 and drain electrode 12 are formed.
本実施例のイオン注入後の第三のエツチング
は、エツチング・マスク５を残置した配線パター
ン７が、第一の実施例の如くゲート電極に類似す
る形状ではなく、その側端面が基板１に対して傾
斜しエツジ部分が鈍角となる様に、リアクテイブ
イオン・エツチングの条件は例えば下記の如く前
記各エツチングよりガス圧力を高くして異方性の
程度を少なくする。 In the third etching after ion implantation in this embodiment, the wiring pattern 7 with the etching mask 5 left behind does not have a shape similar to the gate electrode as in the first embodiment, but its side end surface faces the substrate 1. The conditions for the reactive ion etching are, for example, as follows: the gas pressure is higher than that for each of the etchings described above, and the degree of anisotropy is reduced so that the edges are obtuse.
エツチヤントガス組成：
CF4＋He＝50sccm＋50sccm
エツチヤントガス圧力： 5pa
セルフバイアス電圧： 120V
高周波電力： 100W
エツチング速度： 約200Å／分
この様に配線パターン７の第三のエツチングを
マスク５を残して実施することにより、エツチン
グ後の断面積が第二の実施例より更に大きく、配
像抵抗の上昇が抑制される。 Etchant gas composition: CF 4 +He = 50sccm + 50sccm Etchant gas pressure: 5pa Self-bias voltage: 120V High frequency power: 100W Etching speed: Approximately 200 Å/min By performing the third etching of the wiring pattern 7 in this way, leaving the mask 5, The cross-sectional area after etching is larger than that of the second embodiment, and an increase in image alignment resistance is suppressed.
なおゲート電極６については、この第三のエツ
チングの効果は前記両実施例と同様様である。 Regarding the gate electrode 6, the effect of this third etching is the same as in both of the above embodiments.
次いで第１６図及び第１７図に示す如くマスク
５の除去、絶縁膜１３、第二層の配線パターン１
６の形成を行う。 Next, as shown in FIGS. 16 and 17, the mask 5 is removed, the insulating film 13 and the second layer wiring pattern 1 are removed.
6.
(7) 発明の効果
本発明は以上説明した如く、ゲート電極をマス
クとしてイオン注入を行う電界効果トランジスタ
素子を含む半導体装置の製造工程において、該ゲ
ート電極の該イオンが注入された部分を除去した
後に絶縁膜を形成することにより、その異常成長
による第二層配線の障害、コンクタト抵抗上昇な
どを防止して、半導体装置の信頼度を向上する効
果を有し、同様の目的に対する従来技術の如く高
温度の熱処理を必要としない優れた特徴を有す
る。(7) Effects of the Invention As explained above, the present invention provides a method for removing the ion-implanted portion of the gate electrode in the manufacturing process of a semiconductor device including a field effect transistor element in which ions are implanted using the gate electrode as a mask. By forming an insulating film afterwards, it has the effect of improving the reliability of the semiconductor device by preventing damage to the second layer wiring and increase in contact resistance due to abnormal growth, and is similar to conventional technology for the same purpose. It has an excellent feature that does not require high-temperature heat treatment.
第１図乃至第９図は本発明の第一の実施例、第
１０図乃至第１４図は第二の実施例、第１５図乃
至第１７図は第三の実施例を示す断面図、第１８
図は本実施例のゲート電極のエツチングを説明す
る模式断面図である。
図において、１は基板、２はマスク、３はｎ型
活性層、４は導体膜、５はマスク、６はゲート電
極、７はイオン注入窓、８は保護膜、９はソース
高濃度領域、１０はドレイン高濃度領域、１１は
第一層の配線パターン、１２はソース電極、１３
はドレイン電極、１４は層間絶縁膜、１５は開
口、１６は開口、１７は第二層の配線パターンを
示す。
1 to 9 are sectional views showing a first embodiment of the present invention, FIGS. 10 to 14 are sectional views showing a second embodiment, and FIGS. 15 to 17 are sectional views showing a third embodiment. 18
The figure is a schematic cross-sectional view illustrating the etching of the gate electrode in this example. In the figure, 1 is a substrate, 2 is a mask, 3 is an n-type active layer, 4 is a conductor film, 5 is a mask, 6 is a gate electrode, 7 is an ion implantation window, 8 is a protective film, 9 is a source high concentration region, 10 is a drain high concentration region, 11 is a first layer wiring pattern, 12 is a source electrode, 13
14 is a drain electrode, 14 is an interlayer insulating film, 15 is an opening, 16 is an opening, and 17 is a second layer wiring pattern.
Claims (1)
インとする領域に、該素子のゲート電極をマスク
として不純物のイオン注入を行う工程と、 該素子形成面に垂直方向の効果が平面方向より
大きい異方性エツチング処理により、該ゲート電
極の該不純物が注入された部分を除去する工程
と、 該素子形成面上にCVD法により絶縁層を形成
する工程と、 該絶縁層上に配線を形成する工程とを有するこ
とを特徴とする半導体装置の製造方法。[Claims] 1. A step of implanting impurity ions into regions to be the source and drain of a field effect transistor element using the gate electrode of the element as a mask; a step of removing the portion of the gate electrode into which the impurity has been implanted by a large anisotropic etching process; a step of forming an insulating layer on the element forming surface by a CVD method; and forming a wiring on the insulating layer. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18339681A JPS5885569A (en) | 1981-11-16 | 1981-11-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18339681A JPS5885569A (en) | 1981-11-16 | 1981-11-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5885569A JPS5885569A (en) | 1983-05-21 |
| JPS6354227B2 true JPS6354227B2 (en) | 1988-10-27 |
Family
ID=16135040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18339681A Granted JPS5885569A (en) | 1981-11-16 | 1981-11-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5885569A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0498234U (en) * | 1991-01-22 | 1992-08-25 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53125777A (en) * | 1977-04-08 | 1978-11-02 | Nec Corp | Manufacture for field effect transistor |
-
1981
- 1981-11-16 JP JP18339681A patent/JPS5885569A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53125777A (en) * | 1977-04-08 | 1978-11-02 | Nec Corp | Manufacture for field effect transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0498234U (en) * | 1991-01-22 | 1992-08-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5885569A (en) | 1983-05-21 |
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