JPS6257265B2 - - Google Patents
Info
- Publication number
- JPS6257265B2 JPS6257265B2 JP56183394A JP18339481A JPS6257265B2 JP S6257265 B2 JPS6257265 B2 JP S6257265B2 JP 56183394 A JP56183394 A JP 56183394A JP 18339481 A JP18339481 A JP 18339481A JP S6257265 B2 JPS6257265 B2 JP S6257265B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- wiring pattern
- mask
- layer
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 claims description 36
- 239000010410 layer Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 22
- 239000011229 interlayer Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 230000000694 effects Effects 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- -1 titanium/tungsten Chemical compound 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- UDKYUQZDRMRDOR-UHFFFAOYSA-N tungsten Chemical compound [W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W][W] UDKYUQZDRMRDOR-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は半導体装置の製造工程において、その
基板上に形成する電極・配線パターンの断面形状
を整形して、上層配線の断線障害等の排除、特性
の向上等を実現する製造方法の改善に関する。[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention is directed to eliminating problems such as disconnection of upper layer wiring by shaping the cross-sectional shape of electrode/wiring patterns formed on the substrate in the manufacturing process of semiconductor devices. , relates to improvements in manufacturing methods that achieve improved characteristics, etc.
(2) 技術の背景
半導体装置特に集積回路において、トランジス
タ、ダイオード等の電極もしくは引出電極間を接
続する配線パターンは、しばしば一部の電極と同
一導体膜から形成される。またこれらの一の配線
が他の配線と交叉することがしばしば必要とされ
るが、この場合にはその電極・配線パターンは通
常二層以上の導体膜を用いて形成される。(2) Background of the Technology In semiconductor devices, especially integrated circuits, wiring patterns that connect electrodes or extraction electrodes of transistors, diodes, etc. are often formed from the same conductive film as some of the electrodes. Further, it is often necessary for one of these wirings to cross another wiring, and in this case, the electrode/wiring pattern is usually formed using two or more layers of conductor films.
すなわちまず第一層の導体膜に所要のパターニ
ングを施して電極・配線パターンの第一層を形成
し、その上に例えば二酸化シリコン（SiO2）、窒
化シリコン（Si3N4）等よりなる層間絶縁膜を形成
してこれに所要の開口を設ける。次いで第二層の
導体膜を設け、所要のパターニングを施して電
極・配線パターンの第二層を形成することによ
り、層間絶縁膜により交叉する配線相互間が絶縁
され、所要の接続が層間絶縁膜の開口においてな
される電極・配線パターンが形成される。 That is, first, the first layer of conductive film is patterned to form a first layer of electrode/wiring patterns, and then an interlayer of silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), etc. is formed on top of that. An insulating film is formed and required openings are provided therein. Next, a second layer of conductive film is provided and required patterning is performed to form a second layer of electrode/wiring patterns, thereby insulating the intersecting wires with the interlayer insulating film and making the necessary connections through the interlayer insulating film. An electrode/wiring pattern is formed in the opening.
(3) 従来技術と問題点
前記の如く電極・配線パターンを交叉させる場
合において、第一層の電極・配線によりその上に
形成された層間絶縁膜に段差を生じ、第二層の配
線パターンは一般にこの段差を横断する形状とな
るから、段差のエツジ部分で第二層の配線パター
ンの断面を生じ易い。(3) Prior art and problems When the electrodes and wiring patterns intersect as described above, the electrodes and wiring in the first layer create a step in the interlayer insulating film formed thereon, and the wiring pattern in the second layer Since the shape generally crosses this step, a cross section of the second layer wiring pattern is likely to occur at the edge of the step.
この断線に対する対策として、層間絶縁膜の凹
凸部分を絶縁膜で埋め込んで段差をなくする樹脂
膜コート法と呼ばれる方法、或いは層間絶縁膜を
酸化ゲルマニウム（GeO2）を含んだ燐珪酸ガラス
によつて形成し、これに高温熱処理を施してその
形状を滑らかにする方法等が従来実施されてい
る。 As a countermeasure against this disconnection, there is a method called the resin film coating method in which uneven parts of the interlayer insulating film are filled with an insulating film to eliminate the level difference, or the interlayer insulating film is made of phosphosilicate glass containing germanium oxide (GeO 2 ). Conventionally, a method has been practiced in which the shape is smoothed by forming the shape and subjecting it to high-temperature heat treatment to make the shape smooth.
これらの既に知られている高温熱処理を含む方
法は、高温熱処理に比較的に耐えるシリンコン
（Si）を半導体材料とする場合には容易に活用で
きるが、例えばガリウム砒素（GaAs）等の化合
物半導体材料による半導体装置の製造工程におい
ては、結晶特性の劣化を発生させることなく450
℃程度以上の高温熱処理を長時間施すことは非常
に困難であるために、前記方法に代る新しい製造
方法が必要とされる。 These already known methods involving high-temperature heat treatment can be easily utilized when silicon (Si), which is relatively resistant to high-temperature heat treatment, is used as a semiconductor material; however, for example, when using compound semiconductor materials such as gallium arsenide (GaAs), In the manufacturing process of semiconductor devices using
Since it is very difficult to perform high-temperature heat treatment at a temperature of about 0.degree.
また電極・配線をパターニングするエツチング
処理は、半導体基体の損傷を抑止することが重要
であるためにイオンミリング法等の物理的エツチ
ング方法を用いず、ウエツトエツチング法あるい
はリアクテイブイオン・エツチング法等が一般に
適用されるが、これらの方法は完全にあるいは殆
ど等方性でマスク下にサイドエツチングが進行
し、ウエツトエツチングよりは異方性を得易いリ
アクテイブイオン・エツチングでも、パターン断
面は上辺がマスクより狭く、下辺が上辺より広い
裾広がりの台形となる。 In addition, since it is important to prevent damage to the semiconductor substrate in the etching process for patterning electrodes and wiring, physical etching methods such as ion milling are not used, and instead wet etching or reactive ion etching is used. However, in these methods, side etching progresses under the mask completely or almost isotropically, and even in reactive ion etching, which is easier to obtain anisotropy than wet etching, the cross section of the pattern is etched on the top edge. It is narrower than the mask, and the bottom side is wider than the top side, making it a trapezoid with a wide hem.
配線パターンの断面形状が台形となれば、裾の
拡がつた部分の導体断面積への寄与は少ないにも
かかわらず、配線間容量が底面の寸法に比例して
増大し、配線間の間隔を縮小する妨げとなる。 If the cross-sectional shape of the wiring pattern is trapezoidal, the capacitance between the wires increases in proportion to the bottom dimension, even though the widened bottom part makes little contribution to the conductor cross-sectional area. It becomes an obstacle to downsizing.
また例えばシヨツトキバリア形電界効果トラン
ジスタ素子について、ゲート電極をマスクとして
ソース及びドレイン領域に不純物イオン注入を行
うセルフアライメント（Self alignment）法を適
用する場合には、ゲート電極の側端面の傾斜が特
に問題となる。すなわち台形断面のゲート電極を
マスクとして不純物注入を行つた場合には不純物
の一部がその裾の部分を透過し、マスク効果の不
完全な領域が意図した不純物注入領域に連続して
形成されて、ソース領域及びドレイン領域が不明
確にぼかされ、半導体装置完成後においてゲート
耐電圧の低下をもたらす結果となる。 For example, when applying the self-alignment method of implanting impurity ions into the source and drain regions using the gate electrode as a mask for a shotgun barrier type field effect transistor element, the slope of the side end faces of the gate electrode becomes a particular problem. Become. In other words, when impurity implantation is performed using a gate electrode with a trapezoidal cross section as a mask, a portion of the impurity passes through the bottom part of the gate electrode, and a region with an incomplete mask effect is formed continuously in the intended impurity implantation region. , the source region and the drain region become unclear and blurred, resulting in a reduction in gate withstand voltage after the semiconductor device is completed.
(4) 発明の目的
本発明は、前記の断線障害等を排除した交叉配
線パターンを高温熱処理を行うことなく形成し、
併せて電極・配線パターン断面の台形化を抑止し
て半導体装置の特性を向上する製造方法を得るこ
とを目的とする。(4) Purpose of the Invention The present invention forms a cross-wiring pattern that eliminates the above-mentioned disconnection problems without performing high-temperature heat treatment,
Another object of the present invention is to obtain a manufacturing method that improves the characteristics of a semiconductor device by suppressing trapezoidalization of the cross section of an electrode/wiring pattern.
(5) 発明の構成
本発明の前記目的は、半導体基体上の導体膜上
に設けたマスクを用いて、該導体膜に効果が垂直
方向に大きい異方性の第一のエツチングを施し、
電極及び／もしくは第一層の配線パターンを形成
する工程と、該マスクを除去して該第一のエツチ
ングより異方性を強めた第二のエツチングを施
し、該電極及び／もしくは第一層の配線パターン
の肩の部分を丸みをおびた滑らかな形状とし、か
つその側端面の勾配を急峻にする工程と、所要の
開口を設けた層間絶縁膜を該半導体基体上に被着
する工程と、該層間絶縁膜上に第二層の配線パタ
ーンを形成する工程とを有する本発明による半導
体装置の製造方法により達成される。(5) Structure of the Invention The above-mentioned object of the present invention is to perform anisotropic first etching on the conductor film, which has a large effect in the vertical direction, using a mask provided on the conductor film on a semiconductor substrate,
A process of forming an electrode and/or a wiring pattern of the first layer, removing the mask and performing a second etching with stronger anisotropy than the first etching, and forming a wiring pattern of the electrode and/or the first layer. A step of forming the shoulder portion of the wiring pattern into a rounded and smooth shape and making the slope of the side end surface steep, and a step of depositing an interlayer insulating film with a required opening on the semiconductor substrate, This is achieved by the method for manufacturing a semiconductor device according to the present invention, which includes the step of forming a second layer wiring pattern on the interlayer insulating film.
(6) 発明の実施例
以下に本発明を実施例により、図面を参照して
具体的に説明する。(6) Examples of the invention The present invention will be specifically described below using examples with reference to the drawings.
第１図乃至第９図はGaAs集積回路における本
発明の実施例を示す断面図であり、各図を通じて
同一符号は同一対象部分を示す。また第１０図及
び第１１図はそれぞれ従来技術と本実施例のエツ
チングを説明する模式断面図である。 1 to 9 are cross-sectional views showing an embodiment of the present invention in a GaAs integrated circuit, and the same reference numerals indicate the same parts throughout the figures. Further, FIGS. 10 and 11 are schematic sectional views illustrating the etching of the prior art and this embodiment, respectively.
第１図に示す如く、半絶縁性GaAs基板１上に
例えばSiO2によりマスク２を設けて、Siもしくは
錫（Sn）等の選択的イオン注入を行い、温度700
℃乃至900℃程度の酸素を含まない雰囲気中で15
分間程度の熱処理を施してｎ型活性層３を形成す
る。 As shown in FIG. 1, a mask 2 made of, for example, SiO 2 is provided on a semi-insulating GaAs substrate 1, and selective ions such as Si or tin (Sn) are implanted at a temperature of 700°C.
15°C to 900°C in an oxygen-free atmosphere
A heat treatment is performed for about a minute to form an n-type active layer 3.
次に第２図に示す如く、前記選択的イオン注入
に用いたマスク２を除去し、基板１の全表面にゲ
ート電極及び第一層配線の材料となる高融点金属
珪化物、例えばチタン／タングステン・シリサイ
ドよりなる第一の導体膜４を、厚さ600nm程度に
スパツタ法もしくはMO―CVD法等により形成す
る。 Next, as shown in FIG. 2, the mask 2 used for the selective ion implantation is removed, and the entire surface of the substrate 1 is covered with a high melting point metal silicide, such as titanium/tungsten, which will be the material for the gate electrode and the first layer wiring. - A first conductor film 4 made of silicide is formed to a thickness of about 600 nm by sputtering or MO-CVD.
次に第３図に示す如く、前記導体膜４にゲート
電極及び第一層配線のパターニングを行うための
マスク５をSiO2等により形成する。このマスク
５の形成は、CVD法等により形成されたSiO2膜
上に一旦レジストよりなるマスク（図には表示を
省略）を設け、ドライもしくはウエツトエツチン
グを施すものである。 Next, as shown in FIG. 3, a mask 5 made of SiO 2 or the like is formed on the conductor film 4 for patterning the gate electrode and the first layer wiring. The mask 5 is formed by first providing a resist mask (not shown in the figure) on the SiO 2 film formed by CVD or the like, and then performing dry or wet etching.
次いで前記導体膜４をエツチングし、ゲート電
極６及び第一層の配線パターン７を形成するが、
このエツチング処理は、本発明ではその肩の部分
を丸みをおびた滑らかな形状とすることを意図
し、かつ上述の様に半導体基体の損傷と断面形状
が裾広がりの台形となることを抑止する必要があ
る。 Next, the conductor film 4 is etched to form a gate electrode 6 and a first layer wiring pattern 7.
In the present invention, this etching treatment is intended to give the shoulder portion a rounded and smooth shape, and to prevent damage to the semiconductor substrate and the cross-sectional shape from becoming a trapezoid with a wide base as described above. There is a need.
この様な断面形状を実現するために、本発明で
は、第１０図の従来技術に対比して第１１図ａ，
ｂに模式的に示す如く、特性が異なる２回の異方
性エツチング処理を下記の様に実施する。この様
にエツチング特性を制御するには、化学反応によ
るリアクテイブ・エツチング効果と、イオン・エ
ツチング技術の特質である異方性エツチング効果
とを有するリアクテイブイオン・エツチング法が
最も適している。 In order to realize such a cross-sectional shape, in the present invention, in contrast to the prior art shown in FIG.
As schematically shown in Fig. b, two anisotropic etching treatments with different characteristics are carried out as follows. In order to control the etching characteristics in this manner, the most suitable method is the reactive ion etching method, which has a reactive etching effect based on a chemical reaction and an anisotropic etching effect, which is a characteristic of ion etching technology.
なおこのリアクテイブイオン・エツチング処理
には平行平板型装置が適しており、また導体膜４
に例えばチタン／タングステン・シリサイドを用
いた本実施例では、炭化水素を弗素を主とするフ
ルオルクロル置換体、例えば四弗化炭素（CF4）
を主成分とするガスがエツチヤントに適する。 A parallel plate type device is suitable for this reactive ion etching process, and the conductor film 4
In this example, in which titanium/tungsten silicide is used for example, the hydrocarbon is a fluorochlorosubstituted compound containing mainly fluorine, such as carbon tetrafluoride (CF 4 ).
A gas containing as the main component is suitable as an etchant.
すなわち第一のエツチング処理ではエツチング
速度を考慮してガス圧力は通常さほど低くせず、
バイアス電圧を高めて垂直方向の異方性を強めて
おり、第１１図ａのの如く、従来例よりサイドエ
ツチングが少ないが、なお裾が拡がつた台形とな
つている。 In other words, in the first etching process, the gas pressure is usually not so low considering the etching speed.
By increasing the bias voltage, the anisotropy in the vertical direction is strengthened, and as shown in FIG. 11a, there is less side etching than in the conventional example, but it still forms a trapezoid with a widened base.
次いで第二のエツチング処理では高真空リアク
テイブイオン・エツチング技術を用いて更に垂直
方向の異方性を強め、かつマスク５を除去して、
第１１図ｂに示す如く、ゲート電極６の裾の部分
を除去するとともにそのパターンの肩の部分のエ
ツチングを進行させる。なお半導体基体の損傷を
考慮して、通常前記第一のエツチングよりバイア
ス電圧を低くする。 Next, in a second etching process, the vertical anisotropy is further strengthened using high vacuum reactive ion etching technology, and the mask 5 is removed.
As shown in FIG. 11b, the bottom portion of the gate electrode 6 is removed, and the shoulder portion of the pattern is etched. Note that in consideration of damage to the semiconductor substrate, the bias voltage is usually lower than that in the first etching.
すなわち本実施例では、第４図に示す如き前記
導体膜４からゲート電極６及び第一層の配線パタ
ーン７を形成する前記第一のエツチングを、例え
ば下記例の如き条件のリアクテイブイオン・エツ
チング法により、サイドエツチングがさほど進行
しない程度に実施する。 That is, in this embodiment, the first etching for forming the gate electrode 6 and the first layer wiring pattern 7 from the conductor film 4 as shown in FIG. According to the method, the side etching should be carried out to the extent that side etching does not progress much.
エツチヤントガス組成：
CF4＋O2＝80sccm＋20sccm
エツチヤントガス圧力： 2pa
セルフバイアス電圧： 230V
高周波電力： 100W
エツチング速度： 約470Å／分
次に第５図に示す如く、前記マスク５を除去し
た後に例えば下記例の如き条件で異方性を強めた
前記第二のエツチングを短時間実施し、前記ゲー
ト電極６及び配線パターン７の裾の部分を除去す
るとともにその肩の部分を丸みをおびた滑らかな
形状とする断面形状の整形を行う。 Etching gas composition: CF 4 + O 2 = 80 sccm + 20 sccm Etching gas pressure: 2 pa Self-bias voltage: 230 V High frequency power: 100 W Etching rate: Approximately 470 Å/min Next, as shown in FIG. A cross section in which the second etching is performed for a short period of time with enhanced anisotropy under certain conditions to remove the bottom portions of the gate electrode 6 and the wiring pattern 7, and to make the shoulder portions into a rounded and smooth shape. Perform shape shaping.
エツチヤントガス組成：
CF4＋He＝80sccm＋20sccm
エツチヤントガス圧力： 0.5pa
セルフバイアス電圧： 100V
高周波電力： 50W
エツチング速度： 約85Å／分
次に第６図に示す如く、ソース高濃度領域及び
ドレイン高濃度領域の形成を行う。すなわちレジ
ストを塗布し、イオン注入を行う範囲に開口を設
けるパターニングを施してマスク８を形成した後
に、ゲート電極６及び該マスク８をマスクとし
て、SiもしくはSn等の選択的イオン注入を行
い、前記と同様の熱処理を施して、キヤリア濃度
が表面で３×1017cm-3程度のソース高濃度領域９
及びドレイン高濃度領域１０が形成される。 Etchant gas composition: CF 4 +He = 80sccm + 20sccm Etchant gas pressure: 0.5pa Self-bias voltage: 100V Radio frequency power: 50W Etching rate: Approximately 85 Å/min Next, as shown in Figure 6, the source high concentration region and drain high concentration region were formed. conduct. That is, after coating a resist and performing patterning to provide an opening in the ion implantation range to form a mask 8, selective ion implantation of Si or Sn is performed using the gate electrode 6 and the mask 8 as a mask. The source high concentration region 9 with a carrier concentration of about 3×10 17 cm -3 at the surface was subjected to the same heat treatment as
And a drain high concentration region 10 is formed.
次に第７図に示す如く、マスク８を除去した後
に本実施例ではゲート電極６等に第三のエツチン
グを実施し、その後にソース高濃度領域９及びド
レイン高濃度領域１０にオーミツク接触する電極
１１及び１２を形成する。 Next, as shown in FIG. 7, after removing the mask 8, a third etching is performed on the gate electrode 6 and the like in this embodiment, and then the electrodes that come into ohmic contact with the high concentration source region 9 and the high concentration drain region 10 are etched. 11 and 12 are formed.
このイオン注入後にゲート電極６等に施す第三
のエツチングは、例えば前記第二のエツチングと
同様な条件の異方性リアクテイブイオン・エツチ
ング法を適用して、第１１図ｃに示す模式図の如
く、その表面の前記イオン注入の結果Siが過剰と
なり損傷が発生している部分を厚さ10〜100Å程
度除去するものであり、その上にCVD法による
SiO2の層間絶縁膜などを設けるとき、ゲート電
極６等の面上で成長条件によつてはこれが異常成
長して段差が拡大されることを防止し、また後段
の工程で形成する第二層配線との間のコンタクト
抵抗の上昇を防止する効果を有する。 The third etching performed on the gate electrode 6 etc. after this ion implantation is performed, for example, by applying an anisotropic reactive ion etching method under the same conditions as the second etching, as shown in the schematic diagram shown in FIG. As shown in the figure, the part of the surface where Si is excessive and damaged as a result of the ion implantation is removed to a thickness of about 10 to 100 Å.
When providing an interlayer insulating film of SiO 2, etc., depending on the growth conditions, this can be prevented from growing abnormally and increasing the level difference on the surface of the gate electrode 6, etc., and also prevents the second layer to be formed in a later step. This has the effect of preventing an increase in contact resistance with wiring.
次に第８図に示す如く層間絶縁膜１３を設け
る。 Next, as shown in FIG. 8, an interlayer insulating film 13 is provided.
この層間絶縁膜１３は例えばCVD法による
SiO2とし、厚さ600nm程度とする。本実施例にお
いては以上説明した如く、ゲート電極６及び配線
パターン７の肩の部分が丸みをおびた滑らかな形
状に整形され、更にイオン注入後にもゲート電極
６の表面がエツチングされているために、この層
間絶縁膜１３はゲート電極６或いは配線パターン
７上の段差部分においても滑らかな形状となる。 This interlayer insulating film 13 is formed by, for example, the CVD method.
It is made of SiO 2 and has a thickness of about 600 nm. In this embodiment, as explained above, the shoulder portions of the gate electrode 6 and wiring pattern 7 are shaped into rounded and smooth shapes, and the surface of the gate electrode 6 is etched even after ion implantation. , this interlayer insulating film 13 has a smooth shape even at the step portion on the gate electrode 6 or wiring pattern 7.
次に第９図に示す如く、前記層間絶縁膜１３に
所要の開口、例えば１４及び１５をリソグラフイ
法により設けた後、第二層の導体膜を形成し、所
要のパターニングを実施して第二層の配線パター
ン１６を得る。 Next, as shown in FIG. 9, after forming required openings, for example 14 and 15, in the interlayer insulating film 13 by lithography, a second layer of conductive film is formed, and required patterning is carried out. A two-layer wiring pattern 16 is obtained.
この第二層の配線パターン１６の形成は第４図
を参照して説明した第一層の配線パターン７の形
成方法に準じて実施することが可能であつて、更
に第三層の配線パターンを設けるなど、第二層の
配線パターン１６の整形を必要とする場合には、
第二層の配線パターン１６形成のためのマスク除
去後に、第５図を参照して説明したエツチングを
重ねて実施する。 The formation of the second layer wiring pattern 16 can be carried out according to the method of forming the first layer wiring pattern 7 described with reference to FIG. When it is necessary to shape the second layer wiring pattern 16, such as when
After removing the mask for forming the second layer wiring pattern 16, the etching described with reference to FIG. 5 is repeated.
(7) 発明の効果
本発明は以上説明した如く、半導体装置の製造
工程において、導体膜に特性が異なる２回の異方
性エツチング処理を実施し、特にその第二回の処
理では異方性を強め、マスクを除去することによ
り、肩の部分が丸みをおびた滑らかな形状で、側
端面が急峻な電極・配線パターンを得て、その上
を被覆する層間絶縁膜の段差のエツジ部分を丸み
をおびた滑らかな形状とし、層間絶縁膜上に形成
する電極・配線パターンの第二層の断線等の障害
を排除するものであつて、同目的に対する従来技
術の如く高温度の熱処理を必要とせず、広い適用
範囲を有する。(7) Effects of the Invention As explained above, the present invention performs two anisotropic etching processes with different characteristics on a conductor film in the manufacturing process of a semiconductor device, and in particular, in the second process, the anisotropic etching process is performed twice. By strengthening the mask and removing the mask, an electrode/wiring pattern with a smooth rounded shoulder and steep side edges was obtained, and the edge of the step in the interlayer insulating film covering it was obtained. It has a rounded and smooth shape to eliminate problems such as disconnection of the second layer of electrodes and wiring patterns formed on the interlayer insulating film, and requires high-temperature heat treatment like conventional technology for the same purpose. It has a wide range of application.
また電極・配線パターンの側端面が急峻となる
ことにより、配線間容量を減少するなどの効果が
得られ、ゲート電極をマスクとしてイオン注入を
行う電界効果トランジスタを含む場合には、その
ゲート耐電圧を向上せしめる効果を有する。 In addition, by making the side end faces of the electrode/wiring pattern steep, effects such as reducing inter-wiring capacitance can be obtained, and when including a field effect transistor that performs ion implantation using the gate electrode as a mask, its gate withstand voltage It has the effect of improving
第１図乃至第９図は本発明の実施例を示す断面
図、第１０図は従来技術によるエツチングの模式
断面図、第１１図は本実施例のエツチングを説明
する模式断面図である。
図において、１は基板、２はマスク、３はｎ型
活性層、４は導体膜、５はマスク、６はゲート電
極、７は配線パターン、８はマスク、９はソース
高濃度領域、１０はドレイン高濃度領域、１１は
ソース電極、１２はドレイン電極、１３は層間絶
縁膜、１４は開口、１５は開口、１６は第二層の
配線パターンを示す。
1 to 9 are cross-sectional views showing an embodiment of the present invention, FIG. 10 is a schematic cross-sectional view of etching according to the prior art, and FIG. 11 is a schematic cross-sectional view illustrating the etching of this embodiment. In the figure, 1 is a substrate, 2 is a mask, 3 is an n-type active layer, 4 is a conductor film, 5 is a mask, 6 is a gate electrode, 7 is a wiring pattern, 8 is a mask, 9 is a source high concentration region, and 10 is a 11 is a source electrode, 12 is a drain electrode, 13 is an interlayer insulating film, 14 is an opening, 15 is an opening, and 16 is a second layer wiring pattern.
Claims (1)
いて、該導体膜に効果が垂直方向に大きい異方性
の第一のエツチングを施し、電極及び／もしくは
第一層の配線パターンを形成する工程と、 該マスクを除去して該第一のエツチングより異
方性を強めた第二のエツチングを施し、該電極及
び／もしくは第一層の配線パターンの肩の部分を
丸みをおびた滑らかな形状とし、かつその側端面
の勾配を急峻にする工程と、 所要の開口を設けた層間絶縁膜を該半導体基体
上に被着する工程と、 該層間絶縁膜上に第二層の配線パターンを形成
する工程とを有することを特徴とする半導体装置
の製造方法。[Claims] 1. Using a mask provided on a conductor film on a semiconductor substrate, the conductor film is subjected to an anisotropic first etching with a large effect in the vertical direction, thereby forming an electrode and/or a first layer. forming a wiring pattern; and removing the mask and performing a second etching with stronger anisotropy than the first etching to remove the shoulder portions of the electrode and/or the first layer wiring pattern. a step of forming a rounded and smooth shape with a steep side end surface; a step of depositing an interlayer insulating film with a required opening on the semiconductor substrate; and a step of depositing a third layer on the interlayer insulating film. A method for manufacturing a semiconductor device, comprising the step of forming a two-layer wiring pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18339481A JPS5885567A (en) | 1981-11-16 | 1981-11-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18339481A JPS5885567A (en) | 1981-11-16 | 1981-11-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5885567A JPS5885567A (en) | 1983-05-21 |
| JPS6257265B2 true JPS6257265B2 (en) | 1987-11-30 |
Family
ID=16135003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18339481A Granted JPS5885567A (en) | 1981-11-16 | 1981-11-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5885567A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53125777A (en) * | 1977-04-08 | 1978-11-02 | Nec Corp | Manufacture for field effect transistor |
-
1981
- 1981-11-16 JP JP18339481A patent/JPS5885567A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53125777A (en) * | 1977-04-08 | 1978-11-02 | Nec Corp | Manufacture for field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5885567A (en) | 1983-05-21 |
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