JPS6352472B2 - - Google Patents
Info
- Publication number
- JPS6352472B2 JPS6352472B2 JP324679A JP324679A JPS6352472B2 JP S6352472 B2 JPS6352472 B2 JP S6352472B2 JP 324679 A JP324679 A JP 324679A JP 324679 A JP324679 A JP 324679A JP S6352472 B2 JPS6352472 B2 JP S6352472B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- mos
- switch
- semiconductor substrate
- paired regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特にデイジタル−
アナログ変換（以下DA変換と略す）回路を含む
絶縁ゲート型集積回路（以下MOS ICと略す）に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, particularly digital devices.
This invention relates to an insulated gate integrated circuit (hereinafter referred to as MOS IC) that includes an analog conversion (hereinafter referred to as DA conversion) circuit.
デイジタル回路に於て発展してきたMOS IC
も、性能、集積度が向上し制御すべきアナログ量
を直接入力として、IC内部でデイジタル量に変
換した後デイジタル処理をし、さらにこれを再び
アナログ量に変換して出力する様なマイクロコン
ピユータも出現しつつある。このためには、デイ
ジタル回路と共存出来るDA変換器をMOS ICに
含むことが必要不可欠である。バイポーラ型の
DA変換器では、ラダー抵抗網と電流切換スイツ
チを組合せる方法がしばしば採られているが、
MOS ICに於てはその構造上スイツチと抵抗を一
体とすることが可能なため、第１図に示す様な
DA変換回路が提案されている。すなわちこの
DA変換回路は第１図ｂに示すように一本の抵抗
１１をｎ＋１（ｎビツトの場合）個の等しい抵抗
Ｒに分割して各々の分割箇所にスイツチ１５−１
〜１５−ｎを設けて、デイジタル入力１４−１〜
１４−ｎに応じてスイツチを選択することにより
アナログ出力１６−１〜１６−ｎを得る。この回
路は第１図ａの如く実現され、ラダー抵抗に比べ
てスイツチの数は圧倒的に多くなるが抵抗１１の
分割個所がスイツチとしてのMOSトランジスタ
と一体化されているため、チツプの占有面積はデ
コーダを入れてもより小さくなり、回路も比較的
簡単なもので済むという利点を持つ。 MOS IC has developed in digital circuits
With improved performance and integration, there are also microcomputers that directly input analog quantities to be controlled, convert them to digital quantities within the IC, perform digital processing, and then convert them back to analog quantities for output. It is emerging. To this end, it is essential that the MOS IC include a DA converter that can coexist with digital circuits. bipolar type
DA converters often use a combination of a ladder resistance network and a current selection switch.
In MOS IC, it is possible to integrate a switch and a resistor due to its structure, so it is possible to integrate a switch and a resistor as shown in Fig.
A DA conversion circuit has been proposed. In other words, this
As shown in FIG. 1b, the DA conversion circuit divides one resistor 11 into n+1 (in the case of n bits) equal resistors R, and connects a switch 15-1 to each divided point.
~15-n is provided, and digital input 14-1~
Analog outputs 16-1 to 16-n are obtained by selecting a switch according to 14-n. This circuit is realized as shown in Figure 1a, and although the number of switches is overwhelmingly larger than that of a ladder resistor, since the dividing point of the resistor 11 is integrated with the MOS transistor as a switch, it occupies less space on the chip. has the advantage of being smaller even if a decoder is included, and requiring a relatively simple circuit.
しかしながらこの構造には精度の点から二つの
大きな欠点を有している。その一つは抵抗１１と
スイツチであるMOSトランジスタとの分岐点に
おいて抵抗の形状が不均一になることによるリニ
アリテイの劣化である。この点は抵抗とMOSト
ランジスタを別々に造り配線で結べばある程度ま
で改善されるが、チツプ面積の増化を招き望まし
くないし、拡散抵抗と配線金属との接触部分の抵
抗による誤差は依然として残る。他の欠点は、拡
散抵抗と基板との逆バイアス効果により層抵抗値
がその位置により変つてしまうことである。抵抗
の長さ方向の電位分布を第１図ｃに定性的に示し
てあるが明らかにこの効果によりリニアリテイは
劣化してしまう。これ等の欠点により高ビツトの
精度をもつDA変換器を従来技術でMOS ICチツ
プ上に実現することは非常に困難であつた。 However, this structure has two major drawbacks in terms of accuracy. One of them is the deterioration of linearity due to non-uniformity in the shape of the resistor at the branch point between the resistor 11 and the MOS transistor serving as a switch. This problem can be improved to some extent by building the resistor and MOS transistor separately and connecting them with wiring, but this increases the chip area, which is undesirable, and errors still remain due to the resistance of the contact portion between the diffused resistor and the wiring metal. Another drawback is that the layer resistance varies with position due to the reverse bias effect between the diffused resistor and the substrate. Although the potential distribution in the length direction of the resistor is qualitatively shown in FIG. 1c, it is clear that this effect deteriorates the linearity. Due to these drawbacks, it has been extremely difficult to implement a DA converter with high bit accuracy on a MOS IC chip using conventional technology.
本発明の目的は上記欠点を改善したMOS ICに
内蔵されるDA変換器を提供することである。さ
らに従来のMOS ICの製造工程を変えることなく
前述のDA変換器を実現することにある。 An object of the present invention is to provide a DA converter built into a MOS IC that improves the above-mentioned drawbacks. Another objective is to realize the above-mentioned DA converter without changing the manufacturing process of conventional MOS ICs.
本発明によるＤ／Ａ変換装置は、抵抗体によつ
て分割された電位を絶縁ゲート型電界効果トラン
ジスタのゲートに供給し、該トランジスタにて上
記電位に対応して得られる電流又は電圧出力を選
択的に用いてＤ／Ａ変換を行なうことを特徴とす
る。 A D/A converter according to the present invention supplies a potential divided by a resistor to the gate of an insulated gate field effect transistor, and selects a current or voltage output obtained from the transistor corresponding to the potential. It is characterized in that it is used to perform D/A conversion.
本発明によれば抵抗体（例えばポリシリコン）
を絶縁膜であるシリコン酸化膜上に設け、この抵
抗体の電流が流れる方向に沿つてほぼ等間隔にこ
の抵抗体の一部をゲートとする絶縁ゲート
（MOS）トランジスタを造ることにより抵抗列と
MOSトランジスタを一体化した半導体装置が得
られる。この場合は、抵抗とスイツチは容量で結
合されているため、従来技術の欠点であつたスイ
ツチと抵抗列の接点における精度の劣化は生じな
い。 According to the invention, a resistor (e.g. polysilicon)
is formed on a silicon oxide film, which is an insulating film, and by creating insulated gate (MOS) transistors using part of this resistor as a gate at approximately equal intervals along the direction in which current flows through this resistor, a resistor array can be created.
A semiconductor device with integrated MOS transistors can be obtained. In this case, since the resistor and the switch are coupled through capacitance, there is no deterioration in accuracy at the contact point between the switch and the resistor string, which was a drawback of the prior art.
又、抵抗体は接合を有していないため逆バイア
ス効果は存在しない。 Also, since the resistor does not have a junction, there is no reverse bias effect.
次に本発明の一実施例を第２図ａ，ｂを参照し
て説明する。 Next, one embodiment of the present invention will be described with reference to FIGS. 2a and 2b.
第２図ａに示すように抵抗体２１は抵抗値Ｒ毎
にMOSトランジスタ２５−ｎ，………２５−２，
２５−１のゲート電位として供給される。この
MOSトランジスタのドレインは共通にされて配
線２４によつて電源＋Ｖに接続される。各MOS
トランジスタ２５−１〜２５−ｎのソースは夫々
スイツチＳ１〜Snを介してアナログ出力２６と
して導出される。ここでスイツチS1〜Soはそれぞ
れデイジタル入力２４−１〜２４−ｎによつて開
閉が制御されるもので具体的にはMOSトランジ
スタ等によるトランスフアーゲート、電流スイツ
チ回路、リレー等のものを用いることができる。
ここでは抵抗で分割された電位をソースフオロワ
ー形式の出力として取り出し、この出力をスイツ
チS1〜Soを介して総和を取るようにしている。 As shown in FIG. 2a, the resistor 21 has MOS transistors 25-n, . . . 25-2,
It is supplied as the gate potential of 25-1. this
The drains of the MOS transistors are made common and connected to the power supply +V by a wiring 24. Each MOS
The sources of transistors 25-1 to 25-n are led out as analog outputs 26 via switches S1 to Sn, respectively. Here, the switches S 1 to S o are controlled to open and close by digital inputs 24-1 to 24-n, respectively, and specifically include transfer gates, current switch circuits, relays, etc. using MOS transistors, etc. Can be used.
Here, the potential divided by the resistors is taken out as a source follower output, and this output is summed via switches S 1 to S o .
次に第２図ｂに第２図ａの点線枠内部の実現例
を示す。ここではポリシリコン抵抗体２１がシリ
コン酸化膜上に設けられ、その両端２２，２３は
夫々金属導体で接地（GND）及び基準電位VREF
に接続されている。この抵抗体２１がほぼｎ等分
された部分の酸化膜は薄くなつてMOSトランジ
スタのチヤンネルが形成され抵抗体２１をはさん
で両側に拡散層（この場合はＰ型）２５−１〜２
５−ｎ及び２４が設けられて夫々ソースドレイン
領域となつている。 Next, FIG. 2b shows an example of implementation inside the dotted line frame in FIG. 2a. Here, a polysilicon resistor 21 is provided on a silicon oxide film, and its both ends 22 and 23 are grounded (GND) and reference potential V REF with metal conductors, respectively.
It is connected to the. The oxide film in the portion where this resistor 21 is divided into approximately n equal parts is thinned to form a channel of a MOS transistor, and diffusion layers (P type in this case) 25-1 to 25-2 are formed on both sides of the resistor 21.
5-n and 24 are provided to serve as source and drain regions, respectively.
次に本発明の第２実施例を第３図により示す。 Next, a second embodiment of the present invention is shown in FIG.
本実施例では上述の第２図の実施例のように構
成された抵抗２１とMOSトランジスタ２５−１
〜２５−ｎを含み、ここではトランジスタ２５−
１〜２５−ｎの各ドレインをスイツチS1〜S11を
介して一端が電源＋Ｖに結合された負荷抵抗５２
の他端に接続させ、この共通接続端５４を演算増
幅器（オペアンプ）５０の反転入力（−）に導入
する。MOSトランジスタ２５−１〜２５−ｎの
各ソースは共通に電流源ISを介して接地される。
MOSトランジスタ５１は増幅器５０の出力がゲ
ートに入力され、ドレインは一端が電源＋Ｖに結
合された負荷抵抗５３の他端に接地される。この
他端は増幅器５０の正転入力（＋）に接続されて
いる。かくして得られるボルテージフオロワーの
反転入力を入力として反転入力端子（−）に入力
し、アナログ出力２６′を得るものである。 In this embodiment, a resistor 21 and a MOS transistor 25-1 configured as in the embodiment shown in FIG.
~25-n, here transistor 25-
Each drain of 1 to 25-n is connected to a load resistor 52 whose one end is connected to the power supply +V via switches S1 to S11 .
This common connection end 54 is introduced into the inverting input (-) of an operational amplifier (op-amp) 50. The sources of the MOS transistors 25-1 to 25-n are commonly grounded via a current source IS.
The output of the amplifier 50 is input to the gate of the MOS transistor 51, and the drain is grounded to the other end of a load resistor 53 whose one end is coupled to the power supply +V. The other end is connected to the normal input (+) of the amplifier 50. The inverted input of the voltage follower thus obtained is inputted to the inverted input terminal (-) to obtain an analog output 26'.
なお、以上の実施例により精度は非常に改善さ
れるが、未だポリシリコンと導体金属との接続点
２１，２２における抵抗値が精度を悪くしてい
る。従つてさらに高精度を求める場合は第４図の
様に、チヨツパー等でオフセツト電圧を補償され
た二つのオペアンプじ３２，３３で帰還をかけ、
夫々の反転入力素子を、電圧分割スイツチと同様
なMOSトランジスタで形成すればよい。この場
合にはVREF−GND間のポリシリコン抵抗体は全
く均一となる。 Although the accuracy is greatly improved by the above embodiments, the resistance values at the connection points 21 and 22 between the polysilicon and the conductive metal still deteriorate the accuracy. Therefore, if higher accuracy is desired, as shown in Fig. 4, feedback should be applied using two operational amplifiers 32 and 33 whose offset voltages are compensated for by a chopper or the like.
Each inverting input element may be formed of a MOS transistor similar to a voltage division switch. In this case, the polysilicon resistor between V REF and GND becomes completely uniform.
以上の説明から理解出来る様に本発明の構造は
原理的に抵抗列とスイツチの接触抵抗及び抵抗体
の逆バイアス効果を有していないので、DA変換
器の精度向上に著しい効果をもつ。又、従来のシ
リコンゲートICの製造方法と全く同じ工程で実
現出来るため、従来のデイジタル回路と両立する
点においても全く制約がない。 As can be understood from the above explanation, the structure of the present invention does not have the contact resistance between the resistor array and the switch and the reverse bias effect of the resistor in principle, so it has a remarkable effect on improving the accuracy of the DA converter. Furthermore, since it can be realized using the same process as conventional silicon gate IC manufacturing methods, there are no restrictions in terms of compatibility with conventional digital circuits.
説明では抵抗体としてポリシリコンを用いた
が、抵抗体としてモリブデン等の金属を使用して
も本発明の効果が発揮出来ることは明らかであ
る。 In the description, polysilicon is used as the resistor, but it is clear that the effects of the present invention can be achieved even if a metal such as molybdenum is used as the resistor.
第１図ａは従来技術によるMOS型DA変換器の
平面図、第１図ｂはその等価回路図、第１図ｃは
抵抗内の電流々路に沿つた電位分布を示す図であ
る。第２図ａは本発明の第１の実施例を示す等価
回路図、第２図ｂはその平面図を示す。第３図は
本発明の第２の実施例を示す等価回路図、第４図
は本発明の変更例を示す等価回路図である。
１１……抵抗体、１２……GND側端子、１３
……VREF側端子、１４−ｎ……ｎ番目のデイジタ
ル入力ゲート、１５−ｎ……ｎ番目のアナログ出
力、２１……ポリシリコン抵抗体、２２……
GND端子、２３……VREF端子、２４……共通ド
レイン領域、２５−ｎ……ｎ番目の入力選択及び
出力、３２，３３，５０……オペアンプ。
FIG. 1a is a plan view of a conventional MOS type DA converter, FIG. 1b is an equivalent circuit diagram thereof, and FIG. 1c is a diagram showing a potential distribution along a current path in a resistor. FIG. 2a is an equivalent circuit diagram showing the first embodiment of the present invention, and FIG. 2b is a plan view thereof. FIG. 3 is an equivalent circuit diagram showing a second embodiment of the invention, and FIG. 4 is an equivalent circuit diagram showing a modification of the invention. 11...Resistor, 12...GND side terminal, 13
...V REF side terminal, 14-n...n-th digital input gate, 15-n...n-th analog output, 21...polysilicon resistor, 22...
GND terminal, 23...V REF terminal, 24...Common drain region, 25-n...n-th input selection and output, 32, 33, 50... operational amplifier.
Claims (1)
して載置された抵抗体と、該抵抗体の両端間に一
定の固定電圧を印加する手段と、前記抵抗体をは
さんで前記半導体基板に形成されたドレイン領域
とソース領域との複数の対領域と、該対領域の各
一方に共通に電流を供給する手段と、出力端子
と、前記対領域の各地方と前記出力端子との間に
それぞれ接続された複数のスイツチ手段と、入力
デイジタル信号に応じて前記複数のスイツチ手段
の開閉を制御する手段とを有することを特徴とす
るＤ／Ａ変換回路。1. A semiconductor substrate, a resistor placed on the semiconductor substrate via an insulating film, means for applying a fixed voltage across both ends of the resistor, and a resistor placed on the semiconductor substrate with the resistor sandwiched therebetween. a plurality of paired regions of a drain region and a source region formed in a plurality of paired regions, means for commonly supplying current to each one of the paired regions, an output terminal, and a connection between each region of the paired regions and the output terminal; 1. A D/A conversion circuit comprising: a plurality of switch means respectively connected to the switch means; and means for controlling opening/closing of the plurality of switch means according to an input digital signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP324679A JPS5595354A (en) | 1979-01-11 | 1979-01-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP324679A JPS5595354A (en) | 1979-01-11 | 1979-01-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5595354A JPS5595354A (en) | 1980-07-19 |
| JPS6352472B2 true JPS6352472B2 (en) | 1988-10-19 |
Family
ID=11552092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP324679A Granted JPS5595354A (en) | 1979-01-11 | 1979-01-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5595354A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2727910B2 (en) * | 1993-04-09 | 1998-03-18 | 日本電気株式会社 | Semiconductor integrated circuit device |
-
1979
- 1979-01-11 JP JP324679A patent/JPS5595354A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5595354A (en) | 1980-07-19 |
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