JPS6350119A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6350119A
JPS6350119A JP61192659A JP19265986A JPS6350119A JP S6350119 A JPS6350119 A JP S6350119A JP 61192659 A JP61192659 A JP 61192659A JP 19265986 A JP19265986 A JP 19265986A JP S6350119 A JPS6350119 A JP S6350119A
Authority
JP
Japan
Prior art keywords
circuit
power supply
supply voltage
inverter
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61192659A
Other languages
Japanese (ja)
Inventor
Yoji Watanabe
陽二 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61192659A priority Critical patent/JPS6350119A/en
Publication of JPS6350119A publication Critical patent/JPS6350119A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain an integrated circuit device having a large input voltage margin, by biasing a high potential side of an inverter for receiving an external input signal, to a lower level than an external power supply voltage. CONSTITUTION:A circuit for causing a prescribed voltage drop is inserted between a power supply voltage VCC and an inverter. For instance, this circuit is constituted of a P type MOSFET 12 and an N type MOSFET 13. A voltage dropping circuit 11 for setting an operating voltage of a CMOS inverter to a lower level by VF than the external power supply voltage VCC is provided. According to this circuit constitution, th larger VF is made, the smaller a (gate width/gate length) ratio becomes, the potential dependency of VSS of VTC can be suppressed smaller. That is to say, by lowering the operating power supply voltage of the inverter to a lower level than the external power supply voltage, an aimed circuit threshold value can be obtained even if BR is made smaller. In such a way, an inputting circuit whose circuit threshold value is scarcely influenced by a variation of the VSS potential is obtained.

Description

【発明の詳細な説明】 ［発明の目的コ （産業上の利用分野） 本発明は、半導体集積回路装置における入力回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to an input circuit in a semiconductor integrated circuit device.

（従来技術） 半導体メモリで代表される様なＭＯＳ）ランジスタを集
積した半導体集積回路装置においても、ＴＴＬレベルで
入出力を保証するために入力電圧が２６４ｖ以上なら“
Ｈｏ、０．８ｖ以下なら“Ｌ。(Prior art) Even in semiconductor integrated circuit devices integrated with MOS (MOS) transistors, such as semiconductor memory, if the input voltage is 264V or higher, in order to guarantee input/output at TTL level,
Ho, “L” if 0.8v or less.

をそれぞれ内部に取り込まなければならない。must be incorporated into each.

この様な入力回路としては、一般にインバータ回路が用
いられる。第７図にＣＭＯＳインバータ型の入力回路の
一列を示す。この回路では、Ｐチャンネルトランジスタ
７１とＮチャンネルトラリ、回路しきい値、ＶＴｃを任
意の値に設定できる。An inverter circuit is generally used as such an input circuit. FIG. 7 shows a row of CMOS inverter type input circuits. In this circuit, the P-channel transistor 71, the N-channel transistor, the circuit threshold value, and VTc can be set to arbitrary values.

通常、電源電圧（Ｖ　ｃｃ）が５■±　０．５ｖで動作
する集積回路においては、ＴＴＬ入カシカレベルＨ”側
（Ｖ　　　　”）と“Ｌ“側（Ｖ　　　　）に対するＩ
Ｈｍ１ｎ　　　　　　　　　ＩＬ　ｗａｘマージンを等
しくするために、ＶＴｃをｖｃｃ−５ｖで１．８Ｖにな
る様にβＲを設定する。Normally, in an integrated circuit that operates with a power supply voltage (Vcc) of 5±0.5V, the I
In order to equalize the Hm1n IL wax margin, βR is set so that VTc becomes 1.8V at vcc-5v.

しかしながら、この種の入力回路では、次の様な問題が
あった。一般に集積回路では、複数個の入力回路をもつ
が、それらのチップ上のレイアウトは、パターン的な制
約を受け、自由な配置位置はとり得ない。Ｖｃｃパッド
あるいは、ｖｓｓパッドから遠い位置に配置された入力
回路は電源線のインピーダンスが大きいため、内部回路
動作に伴う■　あるいはｖｓｓノイズの影響を受は易い
。第７Ｃ 図に示した入力回路では、■　あるいはｖｓｓが変Ｇ 動じた場合、回路しきい値ｖＴｏは概ね第８図および第
９図に示す様に変化してしまう。この回路構成テハｖ　
　−ｓ　ｖ、　ｖｓｓ−ｏ　ｖの条件下テｖＴｃをＣ １，８Ｖに設定するためにβ２を大きくせざるを得ない
。このため、■　変動に対するＶＴｃの変化率Ｃ は比較的小さい反面、■ｓｓ変動に対するそれは非常に
大きくなってしまう。従って、この揮の入力回路を■ｓ
ｓパッドから遠い所に配置した場合、電源線ノイズによ
りわずかにｖｓｓ電位が浮いてもｖＴｏが大きく上昇す
るため、本来“Ｈ′としして取り込まなければならない
２．４■の入力信号をＬ”と誤認識する可能性がある。However, this type of input circuit has the following problems. Generally, an integrated circuit has a plurality of input circuits, but the layout of these on a chip is subject to pattern constraints and cannot be freely arranged. An input circuit located far from the Vcc pad or the vss pad has a large impedance of the power supply line, so it is easily affected by the noise or vss noise associated with internal circuit operation. In the input circuit shown in FIG. 7C, if (1) or vss changes, the circuit threshold value vTo changes approximately as shown in FIGS. 8 and 9. This circuit configuration is
-s v, vss-o v In order to set te vTc to C 1.8V, β2 has to be increased. Therefore, while the rate of change C in VTc with respect to (1) fluctuations is relatively small, on the other hand, the rate of change C with respect to (2) ss fluctuations becomes extremely large. Therefore, this input circuit is
If it is placed far from the s pad, even if the vss potential slightly floats due to power line noise, vTo will rise significantly, so the input signal of 2.4 square meters, which should originally be taken in as "H", is changed to "L". There is a possibility of erroneous recognition.

（発明が解決しようとする問題点） 以上のように、従来型の入力回路では、Ｖｓｓ電位の変
動による回路しきい値の変化が著しい、という問題があ
った。本発明は、上記した点に鑑みなされたもので、回
路しきい値がｖｓ８電位変動の影響を受けにくい入力機
回路を提供することを目的とする。(Problems to be Solved by the Invention) As described above, the conventional input circuit has a problem in that the circuit threshold value changes significantly due to fluctuations in the Vss potential. The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide an input device circuit whose circuit threshold value is less susceptible to fluctuations in the vs8 potential.

〔発明の構成〕[Structure of the invention]

（問題点を解決するための手段） 本発明は、ｖｃｏとインバータの間に所定の電圧降下を
起こす回路を挿入することを特徴とする。(Means for Solving the Problems) The present invention is characterized by inserting a circuit that causes a predetermined voltage drop between the VCO and the inverter.

（作用） 本発明によれば、βＲの小さいインバータを用いても回
路しきい値を低い値に設定できるため、Ｖｓ８電位の変
動の影響をうけにく、い入力回路が得られる。(Function) According to the present invention, the circuit threshold value can be set to a low value even if an inverter with a small βR is used, so that an input circuit that is less susceptible to fluctuations in the Vs8 potential can be obtained.

（実施例） 以下本発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.

第１図は、一実施例の入力回路の構成を示す。FIG. 1 shows the configuration of an input circuit in one embodiment.

図において、１１は、Ｐ型ＭＯ３ＦＥ７１２とＮ型ＭＯ
ＳＦＥＴ１３とで構成するＣＭＯＳインバータの動作電
圧を外部電源電圧■　よりＶＦだけ低いレベルに設定す
Ｃ るための電圧降下回路である。この回路構成では、■　
を大きくする程、Ｖ　ｃｃ”　５　ＶでＶＴｏ−１，６
Ｖとなるβ　は小さくなり、ＶＴｃのＶｓｓ電位依存性
のＶ　の依存性とｖ８８依存性をほぼ等しくするこＣ とができ、電源電位の変動に対する入力回路の動作マー
ジンが向上する。更に、回路の配置位置によっては、■
　電位は安定で、ｖｓｓ電位のみが変Ｃ 動しやすい場合がある。このような場合は、Ｖｐを更に
大きくし、βＲの小さなインバータを用いることによっ
て、Ｖ８８ノイズに対し充分安定な入力回路を実現する
ことができる。In the figure, 11 is a P-type MO3FE712 and an N-type MO3FE712.
This is a voltage drop circuit for setting the operating voltage of the CMOS inverter configured with SFET 13 to a level lower than the external power supply voltage by VF. In this circuit configuration, ■
The larger the value, the more VTo-1,6
β which becomes V becomes small, and the dependence of V on the Vss potential of VTc and the dependence on v88 can be made almost equal, and the operating margin of the input circuit against fluctuations in the power supply potential is improved. Furthermore, depending on the location of the circuit, ■
The potential is stable, and only the vss potential may change easily. In such a case, by further increasing Vp and using an inverter with small βR, it is possible to realize an input circuit that is sufficiently stable against V88 noise.

第７図は、第１図の電圧降下回路を、ＰＮ接合ダイオー
ドの順方向電圧を利用して実現した回路例である。FIG. 7 is an example of a circuit in which the voltage drop circuit of FIG. 1 is realized using the forward voltage of a PN junction diode.

第５図は、第１図の電圧降下回路をＮ型ＭＯＳＦＥＴの
しきい値電圧を利用して実現した回路列である。FIG. 5 is a circuit array in which the voltage drop circuit of FIG. 1 is realized using the threshold voltage of an N-type MOSFET.

この回路でＮ型ＭＯＳＦＥＴの基板電位は全て”ＢＢに
固定しておく。ノードＮ１の電位は、ＭＯＳＦＥＴ　５
１．５２のしきい鎖骨だけｖｃｃより低い電位に設定さ
れるため、βＲの小さなインバータを用いることができ
る。更に、ｖｃｃが下がると、基板バイアス効果により
　ＭＯＳＦＥＴ　５１．５２のしきい値は小さくなるた
め、ノードＮ１の電位降下は、ｖｃｃのそれに比べ小さ
く抑えられる。従ってｖｃｃ低下によるＶＴｃ変動も第
６図に示すように小さく抑えることができる。ｖｓｓの
変動に対しては、基板バイアスに影響しないため第３図
に示した特性を保持することができる。In this circuit, the substrate potential of all N-type MOSFETs is fixed at "BB".The potential of node N1 is
Since the threshold clavicle of 1.52 is set to a potential lower than vcc, an inverter with a small βR can be used. Furthermore, when vcc decreases, the thresholds of MOSFETs 51 and 52 decrease due to the substrate bias effect, so the potential drop at node N1 is suppressed to be smaller than that at vcc. Therefore, the VTc fluctuation due to the decrease in vcc can also be suppressed to a small level as shown in FIG. With respect to fluctuations in vss, the characteristics shown in FIG. 3 can be maintained because the substrate bias is not affected.

以上のようにして、この実施例による入力回路では、イ
ンバータの動作電源電圧を外部電源電圧より低いレベル
に下げることにより、βＲを小さくしでもねらい目の回
路しきい値を得ることができる。これによりｖ８８電位
の変動に対して回路しきい値が影響を受けにくい入力回
路が得られる。As described above, in the input circuit according to this embodiment, by lowering the operating power supply voltage of the inverter to a level lower than the external power supply voltage, it is possible to obtain the desired circuit threshold value even if βR is made small. This provides an input circuit whose circuit threshold is less susceptible to fluctuations in the v88 potential.

本発明は上記した実施例に限られるものではない。例え
ば、第４図、第５図では、ＰＮ接合ダイオード、Ｎ型Ｍ
Ｏ９ＦＥＴを２個ずつ直例して挿入しているが、必要な
特性によってそれぞれ１個あるいは、３個以上でもよい
。また、第１図の電圧降下回路としては、ドレインとゲ
ートを接続したＰ型１４０ｓＦＥＴを面倒に挿入しても
よい。あるいは、定電圧発生回路を用いてもよい。更に
インバータはＣＭＯ８型に限定されるものではない。The present invention is not limited to the embodiments described above. For example, in FIGS. 4 and 5, a PN junction diode, an N type M
Although two O9FETs are directly inserted, one or three or more O9FETs may be inserted depending on the required characteristics. Furthermore, as the voltage drop circuit shown in FIG. 1, a P-type 140sFET with its drain and gate connected may be inserted without any trouble. Alternatively, a constant voltage generation circuit may be used. Furthermore, the inverter is not limited to the CMO8 type.

その池水発明は、その趣旨を逸脱しない範囲で種々変形
して実施することができる。The pond water invention can be implemented with various modifications without departing from the spirit thereof.

［発明の効果コ 以上述べたように、本発明によれば、ｖｓｓ”位の変動
に対して回路しきい値が影響を受けにくい入力回路が得
られ、入力電圧マージンの大きな集積回路装置を提供す
ることができる。[Effects of the Invention] As described above, according to the present invention, it is possible to obtain an input circuit whose circuit threshold is less affected by fluctuations of the order of "vss", and to provide an integrated circuit device with a large input voltage margin. can do.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の入力回路の概略構成を示す
図、第２図はその入力特性のＶ。０依存性を示す図、第
３図は同■８８依存性を示す図、第４図は具体的な構成
例を示す図、第５図は変形例を示す図、第６図はその特
性を示す図、第７図は従来の入力回路の構成図、第８図
および第９図はその特性を示す図である。FIG. 1 is a diagram showing a schematic configuration of an input circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing the input characteristic V of the input circuit. 3 is a diagram showing the 88 dependence, Figure 4 is a diagram showing a specific configuration example, Figure 5 is a diagram showing a modified example, and Figure 6 is a diagram showing its characteristics. FIG. 7 is a block diagram of a conventional input circuit, and FIGS. 8 and 9 are diagrams showing its characteristics.

Claims (4)

【特許請求の範囲】[Claims] （１）外部入力信号を受けるインバータの高電位側が外
部電源電圧に比べ低いレベルにバイアスされていること
を特徴とする半導体集積回路装置。(1) A semiconductor integrated circuit device characterized in that a high potential side of an inverter receiving an external input signal is biased to a level lower than an external power supply voltage. （２）前記バイアスは、外部電源電圧線と、前記インバ
ータとの間に１個または複数個のＰＮ接合ダイオードを
順方向に直列接続し挿入することにより行うことを特徴
とする特許請求の範囲第１項記載の半導体集積回路装置
。(2) The biasing is performed by connecting and inserting one or more PN junction diodes in series in the forward direction between the external power supply voltage line and the inverter. The semiconductor integrated circuit device according to item 1. （３）前記バイアスは、外部電源電圧線と前記インバー
タとの間に、ゲート電極をドレイン電極とを接続したＭ
ＯＳＦＥＴを１個または複数個直列し挿入することによ
り行うことを特徴とする特許請求の範囲第１項記載の半
導体集積回路装置。(3) The bias is connected between the external power supply voltage line and the inverter by connecting the gate electrode and the drain electrode.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed by inserting one or more OSFETs in series. （４）前記ＭＯＳＦＥＴはＮ型であり、その基板電位は
固定されていることを特徴とする特許請求の範囲第３項
記載の半導体集積回路装置。(4) The semiconductor integrated circuit device according to claim 3, wherein the MOSFET is of N type and its substrate potential is fixed.
JP61192659A 1986-08-20 1986-08-20 Semiconductor integrated circuit device Pending JPS6350119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61192659A JPS6350119A (en) 1986-08-20 1986-08-20 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61192659A JPS6350119A (en) 1986-08-20 1986-08-20 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6350119A true JPS6350119A (en) 1988-03-03

Family

ID=16294909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61192659A Pending JPS6350119A (en) 1986-08-20 1986-08-20 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6350119A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0417895A2 (en) * 1989-09-12 1991-03-20 Samsung Semiconductor, Inc. Voltage level translation circuit
US5139704A (en) * 1991-02-12 1992-08-18 Hughes Aircraft Company Fluxless solder

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0417895A2 (en) * 1989-09-12 1991-03-20 Samsung Semiconductor, Inc. Voltage level translation circuit
US5139704A (en) * 1991-02-12 1992-08-18 Hughes Aircraft Company Fluxless solder

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