JPS6347331B2 - - Google Patents
Info
- Publication number
- JPS6347331B2 JPS6347331B2 JP58082507A JP8250783A JPS6347331B2 JP S6347331 B2 JPS6347331 B2 JP S6347331B2 JP 58082507 A JP58082507 A JP 58082507A JP 8250783 A JP8250783 A JP 8250783A JP S6347331 B2 JPS6347331 B2 JP S6347331B2
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- alignment mark
- alignment
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000013078 crystal Substances 0.000 claims description 21
- 238000000926 separation method Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 5
- 235000012431 wafers Nutrition 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000007517 polishing process Methods 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000003746 feather Anatomy 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 125000001449 isopropyl group Chemical group [H]C([H])([H])C([H])(*)C([H])([H])[H] 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Description
【発明の詳細な説明】
（技術分野）
この発明は、誘電体分離ウエハの単結晶島上に
精度よく素子を形成するための半導体集積回路装
置用合せマークに関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to alignment marks for semiconductor integrated circuit devices for forming elements with high precision on single crystal islands of dielectrically separated wafers.
（従来技術）
従来の誘電体分離形集積回路装置では、通常研
摩したウエハの表面即ち、誘電体分離ウエハの単
結晶島上には基準となる拡散用の位置合せマーク
が刻まれていないため、第１層目の拡散層を形成
するための位置合せ精度は非常に悪く歩留り低下
要因の一つとなつていた。(Prior art) In conventional dielectrically separated integrated circuit devices, alignment marks for diffusion that serve as a reference are not etched on the surface of the polished wafer, that is, on the single crystal islands of the dielectrically separated wafer. The alignment accuracy for forming the first diffusion layer has been extremely poor and has been one of the causes of lower yields.
たとえば、グリツドラインを目標にして位置合
せをするにしても、誘電体分離ウエハは研摩量が
ウエハ内で５〜10μｍ近くもバラツクこともあ
り、表面に表われるグリツドライン巾は一定でな
く大かれ少なかれ、バラツキがあるものであり、
位置合せの基準とはなり得ない場合が多かつた。 For example, even if alignment is performed with the grid line as the target, the polishing amount of a dielectric separated wafer may vary by as much as 5 to 10 μm within the wafer, and the width of the grid line appearing on the surface is not constant and may be larger or smaller. There are variations,
In many cases, it could not be used as a reference for alignment.
このような欠点を改良する試みとして、研摩バ
ラツキを考慮して複数個の形状の異なる基準パタ
ーンを埋めこんでおく、特開昭55−158633のよう
な工夫もあるが、この方法では基準パターン形成
のため、余分なスペースを必要とするとか他の島
の形状をそこねることなく深さの異なる複数個の
溝を同時に精度よく実現するのが実際には困難で
あるなどの問題が多かつた。 In an attempt to improve this drawback, there is a method such as that disclosed in Japanese Patent Application Laid-Open No. 158633 (1982), in which multiple reference patterns of different shapes are buried in consideration of polishing variations, but this method Therefore, there were many problems, such as the need for extra space and the difficulty of simultaneously realizing multiple grooves of different depths with high accuracy without damaging the shape of other islands.
（発明の目的）
この発明は、上記従来の欠点を除去するために
なされたもので、誘電体分離ウエハの単結晶島の
所定の位置に精度よく素子を形成できる半導体集
積回路装置用合せマークを提供することを目的と
するものである。(Object of the Invention) The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and provides an alignment mark for semiconductor integrated circuit devices that can form elements with high accuracy at predetermined positions on single crystal islands of dielectrically separated wafers. The purpose is to provide
（発明の構成）
この発明の半導体集積回路装置用合せマーク
は、先端部分にストライプ状の複数の羽根を有す
る「＋」字形合せマークを該複数の羽根のいずれ
かが誘電体分離壁に囲まれた単結晶島の分離壁を
またぐようにしたものである。(Structure of the Invention) The alignment mark for a semiconductor integrated circuit device of the present invention includes a "+"-shaped alignment mark having a plurality of striped blades at its tip, and one of the plurality of blades is surrounded by a dielectric separation wall. It is designed to straddle the separation wall of single crystal islands.
（実施例）
以下、この発明の半導体集積回路装置用合せマ
ークの実施例について図面に基づき説明する。第
１図はその一実施例に適用される誘電体分離ウエ
ハの製造工程中の一断面図である。(Embodiments) Hereinafter, embodiments of alignment marks for semiconductor integrated circuit devices according to the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view during the manufacturing process of a dielectrically isolated wafer applied to one embodiment.
この第１図の形状に至る迄には、まず面方位
（100）の単結晶シリコン１の一方の主表面に絶縁
膜（図示せず）を形成し、これをマスクとしてこ
の一方の主表面側に分離溝２を形成する。 To reach the shape shown in Fig. 1, an insulating film (not shown) is first formed on one main surface of single crystal silicon 1 with a plane orientation of (100), and this is used as a mask to coat the surface of this one main surface. Separation grooves 2 are formed in.
分離溝２の形成のためのエツチング液として、
たとえば、KOH−イソプロピルアルコール−水
の混合液を用いると、エツチング速度が最も遅い
（111）面で囲まれたＶ字型断面の分離溝２が形成
される。 As an etching solution for forming the separation groove 2,
For example, when a mixture of KOH-isopropyl alcohol-water is used, a separation groove 2 having a V-shaped cross section surrounded by (111) planes having the slowest etching rate is formed.
分離溝２を形成した後、マスクに用いた絶縁膜
を除去し、絶縁分離用のSiO2膜３に新たに形成
する。 After forming the isolation trench 2, the insulating film used as a mask is removed, and a new SiO 2 film 3 for insulating isolation is formed.
その後、支持体となる多結晶シリコン４をシリ
コン単結晶１の一方の主表面側に気相化学反応法
によりシリコン単結晶１とほぼ同じ厚さに成長さ
せる。ここ迄の工程で第１図に示す形状の断面図
になる。 Thereafter, polycrystalline silicon 4 serving as a support is grown on one main surface side of silicon single crystal 1 to approximately the same thickness as silicon single crystal 1 by a vapor phase chemical reaction method. The steps up to this point result in a cross-sectional view of the shape shown in FIG.
次に、単結晶シリコン１をその裏面からＶ字型
溝２の先端に達するまで（点線Ａで示す部分ま
で）研摩除去し、第２図（誘電体分離ウエハ完成
後の平面図）に示すような誘電体分離された単結
晶島５ａ，５ｂ，５ｃ…５ｎを形成する。 Next, the single crystal silicon 1 is polished and removed from its back surface until it reaches the tip of the V-shaped groove 2 (to the part indicated by dotted line A), and as shown in FIG. Dielectrically isolated single crystal islands 5a, 5b, 5c...5n are formed.
次に、単結晶島にコレクタ領域、ベース領域、
エミツタ領域などの拡散を行い、トランジスタな
どの素子を形成する。その素子形成のための最初
の拡散パターンの位置合せに当つて、誘電体分離
ウエハでそれぞれに分離された単結晶島５ａ〜５
ｎの一つを基準パターン用単結晶島として選定
（ここでは島５ｂを選定）し、この単結晶島５ｂ
を画する辺、つまり、絶縁分離用のSiO2膜３に
第３図に示すような拡散領域を形成するための基
準パターンとしてのストライプ状の複数の羽根６
ａ，６ｂ，６ｃを持つた十字型合せマーク６を単
結晶島５ｂの中心にくるように合わせる。 Next, the collector region, base region,
Diffusion is performed in the emitter region, etc., to form elements such as transistors. During the initial alignment of the diffusion pattern for forming the element, single crystal islands 5a to 5 each separated by a dielectric separation wafer are used.
One of n is selected as a single crystal island for the reference pattern (here, island 5b is selected), and this single crystal island 5b
A plurality of striped blades 6 serve as a reference pattern for forming a diffusion region as shown in FIG. 3 in the SiO 2 film 3 for insulation isolation.
Align the cross-shaped alignment mark 6 having a, 6b, and 6c so that it is centered on the single crystal island 5b.
ここで、十字型合せマーク６は羽根６ａ，６
ｂ，６ｃにいずれかが単結晶島５ｂの表面に露出
したSiO2膜３をまたぐ程度の大きさであり、羽
根６ａ，６ｂ，６ｃとSiO2膜３の位置関係によ
り正確な位置合せをするものである。第２図にお
けるSiO2膜３および多結晶シリコン４部分の巾
は、研摩工程を経て形成されるため、大かれ、少
なかれバラツキがある。第４図に示されるように
単結晶島５ｂが研摩工程でのバラツキにより大き
いとき即ち、SiO2膜３および多結晶シリコン４
部分の巾が狭いときは外側の羽根６ａまたは中央
の羽根６ｂで位置合せをし、逆に第５図に示され
るように、単結晶島５ｂの寸法が小さくなつたと
き即ち、SiO2膜３および多結晶シリコン４部分
の巾が広いときは内側の羽根６ｃで位置合せをす
るものである。 Here, the cross-shaped alignment mark 6 is the blade 6a, 6
Either of the blades b and 6c is large enough to straddle the SiO 2 film 3 exposed on the surface of the single crystal island 5b, and accurate alignment is achieved by the positional relationship between the blades 6a, 6b, 6c and the SiO 2 film 3. It is something. The widths of the SiO 2 film 3 and polycrystalline silicon 4 portions in FIG. 2 vary more or less because they are formed through a polishing process. As shown in FIG. 4, when the single crystal islands 5b are large due to variations in the polishing process, that is, the SiO 2 film 3 and the polycrystalline silicon 4
When the width of the portion is narrow, alignment is performed using the outer blade 6a or the central blade 6b, and conversely, as shown in FIG . When the width of the polycrystalline silicon 4 portion is wide, alignment is performed using the inner blade 6c.
また、各羽根を連絡している十字パターンは合
せマークとして全体パターンからより早く見つけ
やすくなるのである方が好ましい。 Further, it is preferable that the cross pattern connecting each blade is used as a matching mark and is easier to find from the overall pattern.
以上説明したように、第１の実施例では羽根つ
き合せマークを誘電体分離されて表面に露出した
単結晶島に精度よく合わせることが容易であるた
め、素子形成のための拡散パターンを単結晶島に
精度よく合わせることができる。 As explained above, in the first embodiment, it is easy to accurately align the blade alignment marks with the single crystal islands exposed on the surface of the dielectrically separated diffusion pattern. It can be precisely matched to the island.
したがつて、研摩工程による表面に露出した単
結晶島のバラツキがあつても、第４，５図に示す
ように位置決めすれば、精度よく単結晶島へ素子
形成のための拡散パターンを位置合せすることが
できる。 Therefore, even if there are variations in the single crystal islands exposed on the surface due to the polishing process, by positioning them as shown in Figures 4 and 5, the diffusion pattern for element formation can be accurately aligned to the single crystal islands. can do.
さらに、特定の基準パターンを作成するために
必要な広い分離領域を形成する必要もなく、チツ
プサイズの縮少もできる利点がある。 Further, there is an advantage that there is no need to form a wide separation region necessary for creating a specific reference pattern, and the chip size can be reduced.
さらに、第１の実施例では、誘電体分離（完全
絶縁物分離）形集積回路について説明したが、た
とえば、一般にポリプレーナ形と称される集積回
路についても、ウエハ研摩工程を中間工程として
有するので、この発明が適用できる。 Further, in the first embodiment, a dielectric-isolated (completely insulator-isolated) type integrated circuit has been described, but for example, since an integrated circuit generally called a polyplanar type also has a wafer polishing process as an intermediate process, This invention is applicable.
また、第３図で示した合せマーク６はＸ、Ｙお
よびＺ方向のズレに対する基準パターンとして機
能すればよいのであるから、四角形のみだけでな
く、たとえば三角形の各辺の一部、あるいは円の
各円周の一部を残したものに限らず、この発明の
精神を逸脱しない範囲であればどのような形状で
もよいことを理解すべきである。 Furthermore, since the alignment mark 6 shown in FIG. 3 only needs to function as a reference pattern for deviations in the It should be understood that any shape may be used as long as it does not depart from the spirit of the invention, and is not limited to the shape in which a portion of each circumference is left.
（発明の効果）
以上のように、この発明の半導体集積回路装置
用合せマークによれば、羽根つき十字型合せマー
クを素子の拡散層形成のための基準パターンとし
て用意して誘電体分離ウエハの単結晶島の誘電体
分離壁をまたぐように形成して位置合せに使用す
るようにしたので、誘電体分離ウエハに特有な研
摩工程バラツキがあつても、単結晶島上の所定の
場所に素子を精度よく形成できるものである。(Effects of the Invention) As described above, according to the alignment mark for a semiconductor integrated circuit device of the present invention, a winged cross-shaped alignment mark is prepared as a reference pattern for forming a diffusion layer of an element, and a dielectrically separated wafer is formed. Since it is formed so as to straddle the dielectric separation wall of the single crystal island and used for alignment, even if there are variations in the polishing process peculiar to dielectric separation wafers, it is possible to place the device at a predetermined location on the single crystal island. It can be formed with high precision.
第１図はこの発明の半導体集積回路装置用合せ
マークに適用される誘電体分離ウエハの半成品の
断面図、第２図は誘電体分離ウエハの完成後の平
面図、第３図はこの発明の半導体集積回路装置用
合せマークの一実施例を示す平面図、第４図およ
び第５図は第３図の半導体集積回路装置用合せマ
ークによる位置合せ状態を示す平面図である。
１……単結晶シリコン、２……分離溝、３……
SiO2膜、４……単結晶シリコン、５ａ〜５ｎ…
…単結晶島、６……十字型合せマーク、６ａ〜６
ｃ……羽根。
FIG. 1 is a sectional view of a semi-finished product of a dielectrically separated wafer applied to the alignment mark for a semiconductor integrated circuit device of the present invention, FIG. 2 is a plan view of the completed dielectrically separated wafer, and FIG. FIGS. 4 and 5 are plan views showing one embodiment of an alignment mark for a semiconductor integrated circuit device. FIGS. 4 and 5 are plan views showing an alignment state using the alignment mark for a semiconductor integrated circuit device of FIG. 3. 1... Single crystal silicon, 2... Separation groove, 3...
SiO 2 film, 4...single crystal silicon, 5a to 5n...
...Single crystal island, 6...Cross-shaped alignment mark, 6a-6
c... Feather.
Claims (1)
成する工程に用いる合せマークにおいて、 先端にストライプ状の複数の羽根を有する十字
形合せマークの該複数の羽根のいずれかが、前記
単結晶島の前記誘電体分離壁をまたぐように形成
したことを特徴とする半導体集積回路装置用合せ
マーク。[Claims] 1. In an alignment mark used in the process of forming an element on a single crystal island surrounded by a dielectric separation wall, a cross-shaped alignment mark having a plurality of striped blades at its tip includes a plurality of blades. An alignment mark for a semiconductor integrated circuit device, characterized in that one of the marks is formed so as to straddle the dielectric separation wall of the single crystal island.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58082507A JPS59208722A (en) | 1983-05-13 | 1983-05-13 | Alignment mark for semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58082507A JPS59208722A (en) | 1983-05-13 | 1983-05-13 | Alignment mark for semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59208722A JPS59208722A (en) | 1984-11-27 |
| JPS6347331B2 true JPS6347331B2 (en) | 1988-09-21 |
Family
ID=13776417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58082507A Granted JPS59208722A (en) | 1983-05-13 | 1983-05-13 | Alignment mark for semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59208722A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6077421A (en) * | 1983-10-05 | 1985-05-02 | Fujitsu Ltd | Alignment pattern |
| JPS60160122A (en) * | 1984-01-30 | 1985-08-21 | Rohm Co Ltd | Method for alignment of mask |
| JP2751214B2 (en) * | 1988-06-24 | 1998-05-18 | ソニー株式会社 | Semiconductor substrate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50153862U (en) * | 1974-06-07 | 1975-12-20 |
-
1983
- 1983-05-13 JP JP58082507A patent/JPS59208722A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59208722A (en) | 1984-11-27 |
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