JPS59182538A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To remove generation of abnormal etching at flattening etching time when interelement isolation is to be performed by digging a groove in a semiconductor substrate, and filling up an insulator therein by a method wherein the groove is buried with a first insulator of SiO2, PSG, BSG, lead glass, etc. at first, and then a second insulator of Si3N4 or polycrystalline Si, etc. is buried in the central part thereof. CONSTITUTION:A collector buried layer 5 is formed by diffusion on the surface layer part of an Si substrate 4, a layer 6 to act as the active layer part of a transistor is grown epitaxially, and the surface is covered with an SiO2 film 7. Then photo etching is performed to provide an opening in the film 7, and a perpendicular groove 8 to get into the substrate 4 is formed according to the reactive sputter etching method using the film 7 as a mask. After then, a channel stopper 9 is formed according to ion implantation in the substrate 4 exposed on the underside of the groove 8, the film 7 is removed, and a thin SiO2 film 10 is adhered on the whole surface containing the groove 8. Then the groove 8 is buried 8 is buried with a first insulator 11 of SiO2, etc., a fine recess part 12 is dug at the central part thereof, and the part thereof is buried with a second insulator of good quality such as Si3N4, etc.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体基板に形成された溝に絶縁物を充填し
て、複数の半導体素子を互いに電気的に分離する半導体
装置およびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device in which a plurality of semiconductor elements are electrically isolated from each other by filling a groove formed in a semiconductor substrate with an insulating material, and a method for manufacturing the same. .

〔背景技術〕[Background technology]

半導体基板に溝を形成して溝内に絶縁物を充填して半導
体素子間の絶縁分離（アイソレーション）を行なう方法
は、従来の選択酸化法に比べて、所要面積と寄生容量が
非常に小さく、高集積・高速ＬＳＩに適した方法である
。ところが、溝の充填に酸化膜等の絶縁物を用いる場合
、（、ＶＤ（化学気相成長）法やスパッタ法で形成した
膜は、堆積時の境界の膜質が悪い欠点を持っている。第
１図に示すように、Ｓ五基板１に溝を形成し、ＣＶＤ法
で酸化膜２を形成すると、堆積時の境界３は膜質が悪く
、平坦化エツチングの際に異常エツチングが起って、第
２図に示すように酸化膜の中央に凹部４が発生し、後の
工程に悪影響を与える。The method of forming a trench in a semiconductor substrate and filling the trench with an insulator to isolate semiconductor elements requires a much smaller area and parasitic capacitance than the conventional selective oxidation method. This method is suitable for highly integrated and high-speed LSIs. However, when using an insulating material such as an oxide film to fill the trench, films formed by VD (chemical vapor deposition) or sputtering have the disadvantage of poor film quality at the boundaries during deposition. As shown in Fig. 1, when grooves are formed in the S5 substrate 1 and an oxide film 2 is formed by the CVD method, the film quality is poor at the boundary 3 during deposition, and abnormal etching occurs during planarization etching. As shown in FIG. 2, a recess 4 is generated in the center of the oxide film, which adversely affects subsequent steps.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、以上述べた従来技術の欠点を除去し、
平坦性が良くて後の工程に悪影響を与えない絶縁物アイ
ソレーションをそなえた半導体装置およびその製造方法
を提供することにある。The purpose of the present invention is to eliminate the drawbacks of the prior art described above,
An object of the present invention is to provide a semiconductor device having insulator isolation that has good flatness and does not adversely affect subsequent steps, and a method for manufacturing the same.

〔発明の概要〕[Summary of the invention]

上記目的を達成するために、本発明は第３図に示すよう
にアイソレーション溝の中央付近の膜質の悪い部分に他
の絶縁物あるいは誘電体材料１９を充填することによっ
て異常エツチングを防止し、平坦な表面を得るものであ
る。To achieve the above object, the present invention prevents abnormal etching by filling the poor film quality part near the center of the isolation groove with another insulator or dielectric material 19, as shown in FIG. This will give you a flat surface.

〔発明の実施例〕[Embodiments of the invention]

以下、バイポーラ集積回路に関する実施例を用いて本発
明の詳細な説明する。Hereinafter, the present invention will be described in detail using embodiments related to bipolar integrated circuits.

実施例１ 第４図に示すように、周知の方法を用いてＳｉ基板４の
表面にコレクタ埋込層５を設け、その上にトランジスタ
の能動部分となるＳｉエピタキシャル層６（厚さ０．５
〜１．５μｍ）を形成した後、その表面を酸化して５ｊ
０２膜７を形成した。Example 1 As shown in FIG. 4, a collector buried layer 5 is provided on the surface of a Si substrate 4 using a well-known method, and an Si epitaxial layer 6 (thickness 0.5
~1.5 μm), the surface is oxidized to form 5j
02 film 7 was formed.

次に、通常のホトエツチング技術を用いて５ｉ０２膜７
をバターニングし、この８１０２膜７をマスクにして反
応性スパッタ法でＳｔ　６＋　５＋　４’ｔエツチング
して、Ｓｉ基板４に達する垂直な溝８を形成した。そし
て、イオン打込法によって溝の底部にチャネル防止用の
拡散層（チャネルストッパ）９を形、成した（第５図）
。Next, the 5i02 film 7 is etched using a normal photoetching technique.
was patterned, and using this 8102 film 7 as a mask, St 6+ 5+ 4't etching was performed by reactive sputtering to form a vertical groove 8 reaching the Si substrate 4. Then, a channel-preventing diffusion layer (channel stopper) 9 was formed at the bottom of the groove by ion implantation (Figure 5).
.

表面に残った８１０２膜７を除去した後、熱酸化を行な
って５ｊ０２膜１０（厚さ５０〜２００　ｎ　ｍ　）を
形成し、その上にＣＶＤ法で溝の深さとほぼ同じ厚さの
５ｊ０２膜１１を堆積した（第６図）。After removing the 8102 film 7 remaining on the surface, thermal oxidation is performed to form a 5j02 film 10 (thickness 50 to 200 nm), and a 5j02 film 10 (thickness 50 to 200 nm) is formed on top of the 5j02 film 10 with a thickness approximately the same as the depth of the groove. 11 was deposited (Figure 6).

次に、８１０２膜１１をフッ化水素酸系のエツチング液
で膜厚の１／２〜２／３エツチングすると、溝中心部は
膜質が悪いのでエツチングが進んで幅の狭い四部１２が
発生する。そこで、５ｊ３Ｎ４膜１３をＣＶＤ法で形成
すると細い凹部１２はＳｉ３Ｎ４膜で埋ってしまう（第
７図）。ここで、先の５ｉ０２エツチングはドライエツ
チングでもかまわないが、最後にウェットエツチングを
追加して膜質の悪い部分をエツチングしておく必要があ
る。Next, when the 8102 film 11 is etched by 1/2 to 2/3 of its thickness using a hydrofluoric acid-based etching solution, the film quality is poor at the center of the groove, so etching progresses and four narrow portions 12 are formed. Therefore, if the 5j3N4 film 13 is formed by the CVD method, the narrow recess 12 will be filled with the Si3N4 film (FIG. 7). Here, the previous 5i02 etching may be dry etching, but it is necessary to add wet etching at the end to etch the parts with poor film quality.

次に、５ｉｓＮ＜膜１３と５ｉＯｚ膜１２のエツチング
速度がほぼ等しいドライエツチング法を用いて、熱酸化
膜１０の表面までエツチングし、平坦な表面を得た（第
８図）。この構造では、膜質の悪い部分がＳ　ｉ　３　
Ｎ　４膜に置き替っているので、後の工程で溝の中央部
が異常にエツチングされる恐れがなくなり、酸化膜埋込
みアイソレーションを用いたバイポーラＬＳＩが歩留り
良く製作可能となり、信頼性も向上した。Next, the surface of the thermal oxide film 10 was etched using a dry etching method in which the etching rates of the 5isN< film 13 and the 5iOz film 12 were approximately equal, to obtain a flat surface (FIG. 8). In this structure, the portion with poor film quality is S i 3
Since it is replaced with an N4 film, there is no risk that the central part of the groove will be abnormally etched in later processes, making it possible to manufacture bipolar LSIs using oxide film buried isolation with a high yield and improving reliability. did.

実施例２ 次に、溝中央部の凹部に多結晶シリコンを充填する場合
について述べる。Example 2 Next, a case will be described in which the recessed portion at the center of the groove is filled with polycrystalline silicon.

第５図までは実施例１と同じである。チャネルストッパ
層９を形成した後、Ｓ　ｉ０２膜７を除去し、熱酸化を
行なって５Ｉ０２膜１０を形成し、その上に５ｉａＮ４
膜１４を被着し、さらにＣＶＤ法で溝の深さとほぼ同じ
厚さのＳ　ｒ　０２膜１５を堆積した（第９図）。The steps up to FIG. 5 are the same as in the first embodiment. After forming the channel stopper layer 9, the Si02 film 7 is removed, thermal oxidation is performed to form a 5I02 film 10, and a 5iaN4 film is formed on it.
After the film 14 was deposited, an S r 02 film 15 having a thickness approximately the same as the depth of the groove was further deposited by CVD (FIG. 9).

次に、ＳｉＯ２膜１５全１５ットエツチングあるいは、
ドライエツチング＋ウェットエツチングで、Ｓｉ３Ｎ４
膜１４の表面が出るまでエツチングした。Next, all 15 etchings of the SiO2 film 15 or
Si3N4 by dry etching + wet etching
Etching was performed until the surface of the film 14 was exposed.

このとき、溝中央部に凹部１６が発生した。次に１ＣＶ
Ｄ法で多結晶シリコン１７を形成すると、凹部１６に多
結晶シリコンが充填されて表面がほぼ平坦になった（第
１０図）。At this time, a recess 16 was generated in the center of the groove. Next 1CV
When the polycrystalline silicon 17 was formed by the D method, the recessed portion 16 was filled with polycrystalline silicon and the surface became almost flat (FIG. 10).

次に１．多結晶シリコンをＳｉ３Ｎ４膜１４の表面が出
るまで均一にエツチングし、熱酸化を行なうと、四部に
残った多結晶シリコンの表面に酸化膜１８が形成された
。最後に表面の８ｉ３Ｎ４膜１４を除去して平坦な表面
が得られ、アイソレーション工程が完了した（第１１図
）。Next 1. When the polycrystalline silicon was uniformly etched until the surface of the Si3N4 film 14 was exposed and thermal oxidation was performed, an oxide film 18 was formed on the surface of the polycrystalline silicon remaining in the four parts. Finally, the 8i3N4 film 14 on the surface was removed to obtain a flat surface, completing the isolation process (FIG. 11).

本実施例では、最後に多結晶シリコンの表面を酸化する
必要があるが、ＳｉＯ２膜１５全１５チングあるいは多
結晶シリコン１７のエツチングが容易に行なえる（エッ
チ速度の制御が容易、エツチングの終点判定が容易）の
で、再現性良く製作することが可能である。In this example, it is necessary to oxidize the surface of the polycrystalline silicon at the end, but etching the entire SiO2 film 15 or etching the polycrystalline silicon 17 can be easily performed (the etch rate can be easily controlled, and the end point of etching can be determined). (easy), it can be manufactured with good reproducibility.

以上の実施例では埋込用酸化膜１１．１５としては５ｊ
Ｏ２膜を用いているが、埋込材料としては、この他に、
Ｓｉを含有した８ｉ０２膜（Ｓｉｘ０２゜ｘ）１）、Ｐ
ＳＧ（リンガラス）膜、ＢＳＧ（ボロンガラス）膜、鉛
ガラス膜等を用いることが可能である。In the above embodiment, the buried oxide film 11.15 is 5j.
Although O2 film is used, other embedding materials include:
8i02 film containing Si (Six02°x)1), P
It is possible to use an SG (phosphorus glass) film, a BSG (boron glass) film, a lead glass film, or the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図〜第３図は本発明の原理を示す工程図、第４図〜
第８図は本発明の実施例を示すｆ程図、第９図〜第１１
図は本発明の他の実施例を示す工程図である。 １・・・シリコン基板、２・・・酸化膜、３・・・境界
、４゜１２．１６・・・凹部、１９・・・絶縁物あるい
は誘電体材料、５・・・コレクタ埋込層、６・・・エピ
タキシャル成長層、７，１０・・・８１０２膜、１１．
１５・・・酸化膜、１３．１４・・・５ｊ３Ｎ４膜、１
７・・・多結晶シリ第１図 第　Ｚ　　図 第　３　図 第　　４　図 第　５　図 第　６ＵｉＪ 芳７図 ｑ 第３図 イ Ｚ　ｑ　図 第　１０　　　口 第　ｔｒ　　図Figures 1 to 3 are process diagrams showing the principle of the present invention, and Figures 4 to 3 are process diagrams showing the principle of the present invention.
FIG. 8 is a diagram showing an embodiment of the present invention, and FIGS. 9 to 11.
The figure is a process diagram showing another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Oxide film, 3... Boundary, 4°12.16... Recessed part, 19... Insulator or dielectric material, 5... Collector buried layer, 6...Epitaxial growth layer, 7,10...8102 film, 11.
15...Oxide film, 13.14...5j3N4 film, 1
7... Polycrystalline silicon Figure 1 Z Figure 3 Figure 4 Figure 5 Figure 6 UiJ Yoshi 7 Figure q Figure 3 A Z q Figure 10 Figure tr

Claims (1)

【特許請求の範囲】 １、半導体基板に形成された溝内に絶縁物を充填して素
子間の絶縁分離を行なうものにおいて、上記分離溝の中
央部に第二の絶縁物あるいは誘電体材料の領移を有する
ことを特徴とする半導体装置。 ２、上記溝充填用の第一の絶縁物として５ｉ０２膜。 Ｓｉ含有ＳｉＯ２膜（８１ＸＯ２，Ｘ＞１）、ＰＳＧ膜
、ＢＳＧ膜、鉛ガラス膜のいずれかを用い、溝中央部の
第二の材料として８１３Ｎ４膜あるいは多結晶シリコン
と８１０２の二層膜のいずれかを用いることを特徴とす
る半導体装置およびその製造方法。[Claims] 1. In a device that performs insulation isolation between elements by filling a groove formed in a semiconductor substrate with an insulator, a second insulator or dielectric material is provided in the center of the isolation groove. A semiconductor device characterized by having territory transfer. 2. 5i02 film as the first insulator for filling the trench. Either a Si-containing SiO2 film (81XO2, A semiconductor device and a method for manufacturing the same, characterized by using the following.