JPS60160122A - Method for alignment of mask - Google Patents
Method for alignment of maskInfo
- Publication number
- JPS60160122A JPS60160122A JP59018056A JP1805684A JPS60160122A JP S60160122 A JPS60160122 A JP S60160122A JP 59018056 A JP59018056 A JP 59018056A JP 1805684 A JP1805684 A JP 1805684A JP S60160122 A JPS60160122 A JP S60160122A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- key
- width
- alignment
- sides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 5
- 239000004575 stone Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 6
- 239000000919 ceramic Substances 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003909 pattern recognition Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はフォトエツチングの露光の際に使用するマス
クの位置合わせ方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for aligning a mask used during photoetching exposure.
周知のよりにこの種マスクは、パタニングシヨりとする
半導体ウェファ、セラミック等の基板の表面に塗ったレ
ジストの表面に配置し、その上面から紫外線を照射する
ことによって露光するのに使用する。普通数回忙わたる
拡散、フォトエツチング等を行なりので、その前処でき
ているパターンに高精廖をもってこのマスクを位置合わ
せすることづｔ必要である。As is well known, this type of mask is placed on the surface of a resist coated on the surface of a substrate such as a semiconductor wafer or ceramic that is to be patterned, and is used for exposure by irradiating ultraviolet rays from above. Since diffusion, photoetching, etc. are usually performed several times, it is necessary to align the mask with the pre-prepared pattern with high precision.
たとえばサーマにプリントヘッドの製作に際しても、こ
の種マスクを使用してフォトエツチングを行へことがあ
る。すなわち第１−０第２図に示すよりに、セラミック
等の基板１０表面に突条状のグレーズ層２を設け、その
頂面に抵抗層８による発熱部４を設置し、Ｗに抵抗層８
に導電層５を重ね合わせて通電用のす１＋ ｙとする。For example, when manufacturing a thermal printhead, this type of mask is sometimes used for photoetching. That is, as shown in FIGS. 1-0 and 2, a protruding glaze layer 2 is provided on the surface of a substrate 10 made of ceramic or the like, a heat generating portion 4 made of a resistance layer 8 is provided on the top surface of the glaze layer 2, and a resistance layer 8 is provided on the W.
A conductive layer 5 is superimposed on the conductive layer 5 to form a conductive layer 1+y.
この種のサーマルプリントヘッドにおいては、まず抵抗
層８を、又その表面に導電層５をそれぞれ蒸着等により
薄−として形成し、これを所要のパターンどおりに処理
する。そして発熱部４ｆ形成するために、グレーズ層２
０頂面にｂｕて、抵抗層８０表面にある導電層５をエツ
チングで除去する。除去されたあとに露出する抵抗層部
分が発熱部４となる。In this type of thermal print head, first a resistive layer 8 and a thin conductive layer 5 are formed on the surface of the resistive layer 8 by vapor deposition or the like, and then processed into a desired pattern. Then, in order to form the heat generating part 4f, the glaze layer 2
The conductive layer 5 on the surface of the resistor layer 80 is removed by etching on the top surface of the resistor layer 80. The portion of the resistance layer exposed after being removed becomes the heat generating portion 4.
なお５Ａは個別リード、５Ｂは共通リードで、前記のよ
らにバターニングによって形成される。Note that 5A is an individual lead and 5B is a common lead, which are formed by patterning as described above.
ところで前′記したよりに発熱部４はグレーズ層２０頂
面に位置してｂることが重要で、もしこれ赤いずれか一
方の側縁＃Ｃかたよった位置に形成されるよりなことが
あると、往復印字の際に印字濃廖が異なってしまりより
になる。そのため発熱部４の形成のｋめのエツチングに
際してはその露出の際に使用するマスクをグレーズ層２
に対して高精廖に位置合わせすることが要求される。一
般にこの種の位置合わせにはアラインメントキーが使用
される。これはマスク忙露光のためのパターンとともに
予めパタニングされて込る。By the way, as mentioned above, it is important that the heat generating part 4 is located on the top surface of the glaze layer 20, and if it is formed in a position that is offset from one of the side edges #C. Then, when printing back and forth, the print density will be different and it will become stiffer. Therefore, when performing the kth etching to form the heat generating part 4, the mask used for exposing the heat generating part 4 is set to the glaze layer 2.
High-precision alignment is required. Alignment keys are generally used for this type of alignment. This is patterned in advance together with the pattern for mask exposure.
第５図は従来のマスクのアラインメントキー６を示し、
その幅Ｗをグレーズ層２の幅にほぼ等しく設定されであ
る。アラインメントキー６渭グレーズ層２とその幅にか
いて合致したとき、発熱部４のパターンＢグレーズ層２
０頂面と合致するよりにしである。しかし実際問題とし
てグレーズ層２のパターンは常に同じ精廖で形成される
わけではな（１図のよりにその幅に広狭の誤差が生ずる
のは避けられない。そのため図のよりに両者の幅に差が
生ずる。従来では両側の幅の差Ｍｌ ＠ Ｍｌを目視し
て両差が等しくなるように基板又はマスクを位置調整し
ている。しかしこれでは両差の比較０欅があいまｂとな
らざるを得ないので、どすしてもｌＯ〜８０μ程廖の調
整誤差づ；生じていた。FIG. 5 shows a conventional mask alignment key 6,
The width W is set approximately equal to the width of the glaze layer 2. When the alignment key 6 matches the width of the glaze layer 2, the pattern B of the heat generating part 4 glaze layer 2
It is better to match the 0 top surface. However, as a practical matter, the pattern of glaze layer 2 is not always formed with the same precision (as shown in Figure 1, it is inevitable that there will be errors in the width of both widths. A difference occurs. Conventionally, the position of the substrate or mask is adjusted by visually observing the width difference Ml @ Ml on both sides so that both differences are equal. However, in this case, the comparison of the two differences does not result in an ambiguous result. Therefore, an adjustment error of about 10 to 80 μm occurred no matter what.
この発明はマスクの位置合わせ精廖を、簡単な方法で向
上させることを目的とする。The purpose of this invention is to improve the precision of mask alignment using a simple method.
この発明の実施例を第８図、第４図によって鮮明する。An embodiment of the invention is clearly illustrated in FIGS. 8 and 4.
、１１はマスク、１２け発熱部４の形成のためのパター
ンとする。この発明にしたゴー、マスク１１にパターニ
ングされるアラインメントキー１８として規定のグレー
ズ層２の幅より僅かに狭い幅の主キー１４と、その両側
に位置する細幅の副キー１５の複数とにより形成する。, 11 is a mask, and 12 is a pattern for forming the heat generating portion 4. In this invention, the alignment key 18 patterned on the mask 11 is formed by a main key 14 having a width slightly narrower than the prescribed width of the glaze layer 2, and a plurality of narrow sub-keys 15 located on both sides of the main key 14. do.
副キー１６けそのピッチを、マスクの希望する位置合わ
せ精廖に応じて設定されである。たとえば前記した差Ｍ
＊、Ｍｍの調整誤差を２〜６μ程膚としたー場合は、副
キー１５の各輻及びその間隔（スリット幅）をそれぞれ
１０−２０μとするとよい。The pitch of the auxiliary keys 16 is set according to the desired alignment precision of the mask. For example, the difference M
If the adjustment error of * and Mm is about 2 to 6 microns, each radius of the sub key 15 and the interval (slit width) between them should be set to 10 to 20 microns.
マスクの位置合わせ状部を拡大して示したの−Ａ！第４
図である。グレーズ層２と７ラインメントキー１８との
幅に差があるとき、グレーズ層２の側面からはみ出て位
置する副キー１５の数を読むことによって−あたかも目
盛を入れたときと同じよらにして、差Ｍｌ ｍ Ｍ、を
めることがマきる。したがって両差がと本に等しくなる
よりにするためのマスク又は基板の位置調整は容易とな
る。々か副キー１ｆ＋の数の読みは従来のよりに目視に
よってもよいが、これに代えて電電光学的にパターン認
識するようにすれば自動位置合わせも可能となる。The alignment part of the mask is shown enlarged-A! Fourth
It is a diagram. When there is a difference in width between the glaze layer 2 and the 7-linement key 18, by reading the number of sub-keys 15 located protruding from the side of the glaze layer 2 - as if the scale was inserted, It is possible to calculate the difference Ml m M. Therefore, it is easy to adjust the position of the mask or the substrate so that the difference between the two sides is equal to that of the original. The numbers of the subkeys 1f+ may be read visually rather than conventionally, but if pattern recognition is performed electro-electronically instead, automatic positioning becomes possible.
実際には、１枚のセラミック基板から多数のサーマＶプ
リントヘッドを同時に製作するのを普通としている。し
た値ぶって１枚のマスクには多数個の同じパターンガ会
列されて−るので、この場合でもこの発明は適用される
。更にマスクの位置合わせ精廖を高めるために顕像鏡の
分割耕野を用いるとと渭ある−７５１、この場合でもこ
の発明の適用が可能であることはｂうまでもな−。In practice, it is common to fabricate multiple Therma-V printheads simultaneously from a single ceramic substrate. Since a large number of identical patterns are arranged in one mask, the present invention can be applied to this case as well. Furthermore, it is possible to use a divided field of the microscope to improve the accuracy of mask alignment, and it goes without saying that the present invention can be applied in this case as well.
以上詳述したよりにこの発明によれば−単にアラインメ
ントキーの形状に変更を加えるだけで一マスクとその前
にできてｂるパターンとを高精廖に位置合わせができる
よりになるといった効果を奏する。As detailed above, according to the present invention, it is possible to achieve high-precision alignment between one mask and the pattern formed before it simply by changing the shape of the alignment key. play.
＠１図はサーマルプリントヘラＦの平面図、第２図は同
断面ば、第８図はこの発明による位置合わせ状綿を示す
平面図、第４図は第８図の一部の拡大図、第５図は従来
例の一部の拡大平面図である。
１１−・・・・・マスク、１ｇ・・・・・・アラインメ
ントキー。@ Figure 1 is a plan view of the thermal print spatula F, Figure 2 is a cross section of the same, Figure 8 is a plan view showing the aligned cotton according to the present invention, Figure 4 is an enlarged view of a part of Figure 8, FIG. 5 is an enlarged plan view of a part of the conventional example. 11-...Mask, 1g...Alignment key.
Claims (1)
主キーと、その画＠に並ぶ複数の細巾の副キーとにより
構成し、前にできてｂるパターンの画側面からはみ出る
前記副キーの配列状況省一致するよりに前記マスクを前
記パターンに位置ずけるよらにしたマスクの位置合わせ
方法。The stone alignment key is formed in the shape of WX, and is composed of a wide main key and a plurality of narrow sub-keys lined up in the pattern @, and the sub-keys protrude from the side of the image of the pattern formed in front. A method for positioning a mask in which the mask is positioned on the pattern in a manner that matches the arrangement condition of the mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59018056A JPS60160122A (en) | 1984-01-30 | 1984-01-30 | Method for alignment of mask |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59018056A JPS60160122A (en) | 1984-01-30 | 1984-01-30 | Method for alignment of mask |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60160122A true JPS60160122A (en) | 1985-08-21 |
| JPH023534B2 JPH023534B2 (en) | 1990-01-24 |
Family
ID=11961036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59018056A Granted JPS60160122A (en) | 1984-01-30 | 1984-01-30 | Method for alignment of mask |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60160122A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52144973A (en) * | 1976-05-28 | 1977-12-02 | Hitachi Ltd | Positioning method of semiconductor wafers |
| JPS59208722A (en) * | 1983-05-13 | 1984-11-27 | Oki Electric Ind Co Ltd | Alignment mark for semiconductor integrated circuit device |
| JPS6077421A (en) * | 1983-10-05 | 1985-05-02 | Fujitsu Ltd | Alignment pattern |
-
1984
- 1984-01-30 JP JP59018056A patent/JPS60160122A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52144973A (en) * | 1976-05-28 | 1977-12-02 | Hitachi Ltd | Positioning method of semiconductor wafers |
| JPS59208722A (en) * | 1983-05-13 | 1984-11-27 | Oki Electric Ind Co Ltd | Alignment mark for semiconductor integrated circuit device |
| JPS6077421A (en) * | 1983-10-05 | 1985-05-02 | Fujitsu Ltd | Alignment pattern |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH023534B2 (en) | 1990-01-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |