JPS633459A - Formation of diffused well - Google Patents
Formation of diffused wellInfo
- Publication number
- JPS633459A JPS633459A JP61147518A JP14751886A JPS633459A JP S633459 A JPS633459 A JP S633459A JP 61147518 A JP61147518 A JP 61147518A JP 14751886 A JP14751886 A JP 14751886A JP S633459 A JPS633459 A JP S633459A
- Authority
- JP
- Japan
- Prior art keywords
- type
- well
- impurity
- conductivity type
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title claims description 5
- 239000012535 impurity Substances 0.000 claims abstract description 38
- 238000009792 diffusion process Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 24
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 11
- 239000011574 phosphorus Substances 0.000 claims abstract description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052796 boron Inorganic materials 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000009826 distribution Methods 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 9
- 238000002955 isolation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体素子の製造時等に利用される拡散ウェル
の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming a diffusion well used in the manufacture of semiconductor devices.
（従来の技ｆｉ）
半導体素子の製造時等には、半導体基板にウェル領域を
形成することが重要な工程として含まれることが多い。(Conventional Technique) When manufacturing semiconductor devices, forming a well region in a semiconductor substrate is often included as an important step.
従来、ウェル領域を形成する方法としては、
（１）不純物をイオン注入して、基板表面に導入し、そ
れらを押込み拡散する方法や
（２）エピタキシャル層を堆積させる方法等が知られて
いる。Conventionally, known methods for forming a well region include (1) ion implantation of impurities, introducing them into the substrate surface, and pushing and diffusing them; and (2) depositing an epitaxial layer.
第２図は、前記（１）の方法によって、ｐ型基板にリン
をイオン注入し、押込み拡散した形成したｎ型拡散ウェ
ルの不純物分布の例を示している。ウェルの不純物は第
２図の様にガウス分布、もしくは、コンプリメンタリ−
エラー分布となることが知られている。FIG. 2 shows an example of the impurity distribution of an n-type diffusion well formed by ion-implanting phosphorus into a p-type substrate and intruding it into the well by the method (1). The impurities in the well have a Gaussian distribution or complementary distribution as shown in Figure 2.
It is known that this results in an error distribution.
第３図（ａ）、 （ｂ）、 （ｃ）は前記（２）の方法
によるウェル形成の例を示している。第３図（ａ）は、
１のｐ型基板に、５の砒素ドープｎ十型領域を形成した
断面図を示している。（ｂ）は、その上に、６のｎ型エ
ピタキシャル層を堆積させた図である。（Ｃ）は、さら
に、ｎ型エピタキシャル層６を貫通する様に７のｐ生型
分離拡散領域を形成し、８のｎ型ウェル領域を形成した
図である。FIGS. 3(a), 3(b), and 3(c) show an example of well formation by the method (2) above. Figure 3(a) is
1 is a cross-sectional view in which arsenic-doped n-type region 5 is formed on a p-type substrate 1; (b) is a diagram on which a 6 n-type epitaxial layer is deposited. (C) is a diagram in which a p-type isolation diffusion region 7 is further formed to penetrate the n-type epitaxial layer 6, and an n-type well region 8 is formed.
（発明が解決しようとする問題点）
しかしながら、例えば、ｐ型基板にｎ型ウェルを形成し
て０ＭＯ８を製造する場合を考えると、ｎ型ウェル中に
ＰＭＯ８）ランジスタが形成される。第２図に示した様
な不純物分布を有するウェルでは、ウェル表面のｎ型不
純物濃度が高く、基板内はど不純物濃度が低くなってい
る。そのため、ウェル中のＰＭＯ８）ランジスタについ
て考えた場合、ｐ型基板とｎ型ウェルとの界面からの空
乏層が拡がりやすいから、ｐ型基板とＰＭＯ８）ランジ
スタがパンチスルーしやすいという欠点や、表面濃度が
高くなるためＰＭＯ８）ランジスタの閾値電圧制御卸し
にくい等の欠点がある。(Problems to be Solved by the Invention) However, for example, if we consider the case where an n-type well is formed on a p-type substrate to manufacture OMO8, a PMO8 transistor is formed in the n-type well. In a well having an impurity distribution as shown in FIG. 2, the n-type impurity concentration on the well surface is high, and the impurity concentration inside the substrate is low. Therefore, when considering the PMO8) transistor in the well, the depletion layer from the interface between the p-type substrate and the n-type well tends to spread, so there are drawbacks such as easy punch-through between the p-type substrate and the PMO8) transistor, and the surface concentration There are disadvantages such as difficulty in controlling the threshold voltage of the PMO8) transistor because the voltage becomes high.
これらの欠点を克服する手段として、前記（２）の方法
が用いられる。この方法を用いると、表面では低不純物
濃度、深部では高不純物濃度を有するウェルとなるから
、０ＭＯ８を製造する場合や、バイポーラトランジスタ
を製造する場合、前記（１）の方法に比較して欠点は少
ない。しかしながら、第３図（Ｃ）に示される様に、エ
ピタキシャル層を貫通する様に分離拡散領域を形成しな
ければならないと言う欠点がある。The method (2) above is used as a means to overcome these drawbacks. If this method is used, the well will have a low impurity concentration on the surface and a high impurity concentration in the deep part, so when manufacturing 0MO8 or bipolar transistors, there are no disadvantages compared to method (1) above. few. However, as shown in FIG. 3(C), there is a drawback in that an isolation diffusion region must be formed to penetrate the epitaxial layer.
本発明は、前記の問題点を解決し、エピタキシャル層を
貫通する分離拡散領域を形成することなしに、表面では
低不純物濃度、深部では高不純物濃度と言うような不純
物分布を有する拡散ウェルの形成方法を提供することを
目的とする。The present invention solves the above problems and forms a diffusion well having an impurity distribution such as a low impurity concentration on the surface and a high impurity concentration in the deep part without forming an isolation diffusion region penetrating the epitaxial layer. The purpose is to provide a method.
（問題点を解決するための手段）
上記した問題を解決するため、本発明では、第１導電型
半導体基板上に第２導電型不純物を導入した領域を形成
し、該第１導電型半導体基板上に第１導電型エピタキシ
ャル層を堆積させ、該第２導電型不純物を導入した領域
から第２導電型不純物を該第１導電型エピタキシャル層
中に熱拡散させることを特徴とする第２導電型拡散ウェ
ルの形成方法を提供する。(Means for Solving the Problems) In order to solve the above-described problems, in the present invention, a region doped with a second conductivity type impurity is formed on a first conductivity type semiconductor substrate, and a region is formed on the first conductivity type semiconductor substrate. A second conductivity type, characterized in that a first conductivity type epitaxial layer is deposited thereon, and the second conductivity type impurity is thermally diffused into the first conductivity type epitaxial layer from the region into which the second conductivity type impurity is introduced. A method of forming a diffusion well is provided.
（作用）
第１図は本発明の作用を示す拡散ウェルの形成方法の断
面図である。ここでは第１導電型半導体基板としてｐ型
基板を用い、第２導電型不純物としてリンを導入した場
合を示す。第１図（ａ）は１のｐ型基板に、２のリンを
導入した領域を形成した図である。(Function) FIG. 1 is a sectional view of a method for forming a diffusion well showing the function of the present invention. Here, a case is shown in which a p-type substrate is used as the first conductivity type semiconductor substrate and phosphorus is introduced as the second conductivity type impurity. FIG. 1(a) is a diagram in which a phosphorus-introduced region (2) is formed on a p-type substrate (1).
第１図（ｂ）は、その上に３のｐ型エピタキシャル層を
堆積させた図である。第１図（Ｃ）は、リンを導入した
領域２から、リンをｐ型エピタキシャル層中に拡散させ
ることにより、４のｎ型拡散ウェルを形成した図である
。第１図の拡散ウェルの形成方法では、エピタキシャル
層を貫通させて形成する分離拡散領域を必要としない。FIG. 1(b) shows a p-type epitaxial layer 3 deposited thereon. FIG. 1(C) is a diagram in which an n-type diffusion well 4 is formed by diffusing phosphorus into the p-type epitaxial layer from the region 2 into which phosphorus is introduced. The method of forming a diffusion well shown in FIG. 1 does not require an isolation diffusion region formed through the epitaxial layer.
さらに、表面では低不純物濃度、深部では高不純物濃度
を有する様な不純物分布の拡散ウェルとなる。Further, the diffusion well has an impurity distribution such that the impurity concentration is low at the surface and high at the deep portion.
（実施例）
第４図は本発明の実施例を示している拡散ウェルの不純
物分布図である。第４図は、６×１０１４１ｃｍ３のホ
ウ素を含むｐ型シリコン基板に、ドーズ量２Ｘ１０１５
１ｃｍ２のリンをイオン注入によって導入した後、６
Ｘ １０１４／ａｍ３のホウ素を含むｐ型エピタキシャ
ル層を低温で厚さ６ｐｍ堆積させ、１２００°Ｃ１４時
間の熱拡散を行って本発明による拡散ウェルを形成した
ものである。(Example) FIG. 4 is an impurity distribution diagram of a diffusion well showing an example of the present invention. Figure 4 shows a p-type silicon substrate containing 6 x 10141 cm3 of boron at a dose of 2 x 1015 cm3.
After introducing 1 cm2 of phosphorus by ion implantation, 6
A p-type epitaxial layer containing boron of x 1014/am3 was deposited at a low temperature to a thickness of 6 pm, and thermal diffusion was performed at 1200° C. for 14 hours to form a diffusion well according to the present invention.
第５図は本発明の別の実施例を示している拡散ウェルの
不純物分布図である。第５図は、６ Ｘ １０１４／ｃ
ｍ３のホウ素を含むｎ型シリコン基板、ドーズ量２Ｘ１
０１５１ｃｍ２のリンをイオン注入によって導入した後
、６×１０１４１ｃｍ３のリンを含むｎ型エピタキシャ
ル層を低温で厚さ匈ｍ堆積させ、１２００°Ｃ１３時間
の熱拡散を行って本発明による拡散ウェルを形成したも
のである。FIG. 5 is an impurity distribution diagram of a diffusion well showing another embodiment of the present invention. Figure 5 shows 6 x 1014/c
n-type silicon substrate containing m3 boron, dose amount 2X1
After 0151 cm2 of phosphorus was introduced by ion implantation, an n-type epitaxial layer containing 6 x 10141 cm3 of phosphorus was deposited at a low temperature to a thickness of 1 cm, and thermal diffusion was performed at 1200°C for 13 hours to form a diffusion well according to the present invention. It is something.
本発明において、ウェルを不純物の熱拡散により形成す
るから、半導体としてシリコンを用いる場合には、不純
物として、す、ン、ホウ素、アルミニウムを不純物の拡
散源とすれば、ウェル形成に要する拡散時間を短くする
ことが可能である。In the present invention, since the well is formed by thermal diffusion of impurities, when using silicon as the semiconductor, if the impurity diffusion source is carbon, boron, or aluminum, the diffusion time required for well formation is It is possible to make it shorter.
上記の実施例では、熱拡散を行う温度として１２００°
Ｃを例にとり説明したが、本発明は、約８００°Ｃから
約１３００°Ｃの温度範囲で熱拡散を行って容易に実施
できることは、上記の説明により明らかである。さらに
、実施例では、エピタキシャル層厚を６ｐｍとして説明
したが、よりエピタキシャル層が厚い高耐圧用ウェルの
形成方法として特に重要である。In the above example, the temperature for heat diffusion is 1200°.
Although the explanation has been made using C as an example, it is clear from the above description that the present invention can be easily implemented by performing thermal diffusion in a temperature range of about 800°C to about 1300°C. Further, in the embodiment, the epitaxial layer thickness is 6 pm, but this method is particularly important as a method for forming a high breakdown voltage well with a thicker epitaxial layer.
（発明の効果）
本発明によれば、従来の方法よりも簡単な形成プロセス
で、表面では低不純物濃度、深部では高不純物濃度を有
する様な不純物分布の拡散ウェルを自己整合的に形成で
きるようになるから、本発明によるウェル中にＭＯＳ
）ランジスタを形成したり、本発明のウェルをバイポー
ラトランジスタのコレクタに適用すれば、ＣＭＯＳデバ
イスや各種バイポーラデバイス等の低価格化・高集積化
等が可能となる。(Effects of the Invention) According to the present invention, a diffusion well with an impurity distribution having a low impurity concentration on the surface and a high impurity concentration in the deep part can be formed in a self-aligned manner with a formation process that is simpler than the conventional method. Therefore, the MOS in the well according to the present invention
) By forming a transistor or applying the well of the present invention to the collector of a bipolar transistor, it becomes possible to lower the cost and increase the integration of CMOS devices and various bipolar devices.
第１図（ａ）〜（Ｃ）は、本発明の作用を示す拡散ウェ
ルの形成方法を説明した断面図、第２図は従来例の拡散
ウェルの不純物濃度分布図、第３図は従来例の拡散ウェ
ルの形成方法を説明した断面図である。また第４図は本
発明の実施例の拡散ウェルの不純物濃度分布図、第５図
は本発明の別の実施例の拡散ウェルの不純物濃度分布図
である。
１・・・ｐ型基板
２・・・リンを導入した領域
３・・・ｐ型エピタキシャル層
４・・・ｎ型拡散ウェル領域
５・・・砒素ドープｎ串型領域
６・・・ｎ型エピタキシャル層
７・・・ｐ串型分離拡散領域
芽 １ 目
等 ３（！ｒ
＄４ Ｔ５！Ｊ
うソゴンｉで 〔Ｐメ〕Figures 1 (a) to (C) are cross-sectional views illustrating the method of forming a diffusion well showing the effects of the present invention, Figure 2 is an impurity concentration distribution diagram of a conventional diffusion well, and Figure 3 is a conventional example. FIG. 3 is a cross-sectional view illustrating a method of forming a diffusion well. 4 is an impurity concentration distribution diagram of a diffusion well according to an embodiment of the present invention, and FIG. 5 is an impurity concentration distribution diagram of a diffusion well according to another embodiment of the present invention. 1... P-type substrate 2... Region into which phosphorus is introduced 3... P-type epitaxial layer 4... N-type diffusion well region 5... Arsenic-doped n-shaped region 6... N-type epitaxial layer Layer 7...P skewer type separation and diffusion region bud 1 Eye etc. 3 (!r $4 T5!J Usogon i [P me]
Claims (3)
入した領域を形成し、該第１導電型半導体基板上に第１
導電型エピタキシャル層を堆積させ、該第２導電型不純
物を導入した領域から第２導電型不純物を該第１導電型
エピタキシャル層中に熱拡散させることを特徴とする第
２導電型拡散ウェルの形成方法。(1) A region doped with a second conductivity type impurity is formed on a first conductivity type semiconductor substrate, and a first conductivity type impurity is formed on the first conductivity type semiconductor substrate.
Formation of a second conductivity type diffusion well characterized by depositing a conductivity type epitaxial layer and thermally diffusing the second conductivity type impurity from the region into which the second conductivity type impurity is introduced into the first conductivity type epitaxial layer. Method.
素を導入することを特徴とする特許請求の範囲第１項に
記載の拡散ウェルの形成方法。(2) The method for forming a diffusion well according to claim 1, wherein aluminum or boron is introduced into an n-type silicon substrate.
する特許請求の範囲第１項に記載の拡散ウェルの形成方
法。(3) The method for forming a diffusion well according to claim 1, which comprises introducing phosphorus into a p-type silicon substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61147518A JPS633459A (en) | 1986-06-23 | 1986-06-23 | Formation of diffused well |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61147518A JPS633459A (en) | 1986-06-23 | 1986-06-23 | Formation of diffused well |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS633459A true JPS633459A (en) | 1988-01-08 |
Family
ID=15432144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61147518A Pending JPS633459A (en) | 1986-06-23 | 1986-06-23 | Formation of diffused well |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS633459A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55128828A (en) * | 1979-03-28 | 1980-10-06 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS60101964A (en) * | 1983-11-08 | 1985-06-06 | Iwatsu Electric Co Ltd | Integrated circuit comprising complementary type field effect transistor |
-
1986
- 1986-06-23 JP JP61147518A patent/JPS633459A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55128828A (en) * | 1979-03-28 | 1980-10-06 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS60101964A (en) * | 1983-11-08 | 1985-06-06 | Iwatsu Electric Co Ltd | Integrated circuit comprising complementary type field effect transistor |
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