JPS6245065A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6245065A JPS6245065A JP18531185A JP18531185A JPS6245065A JP S6245065 A JPS6245065 A JP S6245065A JP 18531185 A JP18531185 A JP 18531185A JP 18531185 A JP18531185 A JP 18531185A JP S6245065 A JPS6245065 A JP S6245065A
- Authority
- JP
- Japan
- Prior art keywords
- region
- emitter
- nitride film
- forming
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、バイポーラトランジスタのエミッタをイオン
注入により形成する製造方法に関し、特に、イオン注入
に起因して発生する結晶欠陥によるリーク１１ｔ流を防
止する購造を作る製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a manufacturing method for forming the emitter of a bipolar transistor by ion implantation, and in particular to a method for preventing leakage 11t flow due to crystal defects caused by ion implantation. Concerning manufacturing methods for making purchases.
従来バイポーラトランジスタのエミッタをイオン注入で
形成し、イオン注入に起因して発生する結晶欠陥金除去
する手段として、種々のアニールおよび薄い改化模を介
してイオン注入を行う方法などがある。Conventionally, the emitter of a bipolar transistor is formed by ion implantation, and methods for removing crystal defects caused by the ion implantation include performing ion implantation through various types of annealing and thin modification.
上記した従来の技術では、イオン注入に起因する結晶欠
陥をある程度除去することが可能であるが、完全に結晶
欠陥を除去することができず、バイポーラトランジスタ
のベース、エミッタ接合に微少のリーク電流を発生させ
る欠点がめる。Although the above-mentioned conventional technology can remove crystal defects caused by ion implantation to some extent, it cannot completely remove crystal defects and causes a small amount of leakage current in the base and emitter junctions of bipolar transistors. Acknowledge the shortcomings that occur.
このリーク電流は、半導体の表面近傍でベース。This leakage current is based near the surface of the semiconductor.
エミッタ接合近傍にある結晶欠陥により発生するもので
あり、ベース、エミッタ接合の空乏ノーより離才した結
晶欠陥はリーク電流には寄与しない。This is caused by crystal defects near the emitter junction, and crystal defects separated from the depletion node at the base and emitter junctions do not contribute to leakage current.
本発明の目的は、イオン注入に起因する半導体我面の結
晶欠陥がベース、エミッタ接合のリーク電流に影響しな
いような構造を作る製造方法を提供するものである。An object of the present invention is to provide a manufacturing method for creating a structure in which crystal defects on the surface of a semiconductor caused by ion implantation do not affect leakage current at the base and emitter junctions.
本発明の半導体装置の製造方法は、第１導￥Ｌ壓の半導
体領域に反対導電型のベース領域および半導体領域上に
酸化膜を形成した後、浅い第１導電型の第２の領域を形
成すべき部分の酸化膜を除去し、窒化膜を成長し、異方
性のドライエッチにより窒化膜をエツチングし、前記酸
化膜の内側に窒化膜を残した構造を形成した後、第１導
電壓の不純物をイオン注入で打ち込み、熱処理を行って
深い第１導亀型のエミッタ領域を形成する工程と、前記
窒化膜を選択的に除去し、第１４電型の不純物を拡散し
、深い第１４電型のエミッタ領域より広く、戊い第１４
屯型の第２の領域を形成する工程とを有している。In the method for manufacturing a semiconductor device of the present invention, after forming an oxide film on a base region of an opposite conductivity type and the semiconductor region in a semiconductor region of a first conductivity type, a shallow second region of the first conductivity type is formed. After removing the oxide film in the desired area, growing a nitride film, and etching the nitride film by anisotropic dry etching to form a structure in which the nitride film remains inside the oxide film, a first conductive film is formed. A step of ion-implanting impurities and performing heat treatment to form a deep first conductive type emitter region, selectively removing the nitride film, diffusing 14th conduction type impurities, and forming a deep 14th conductive type emitter region. Wider than the emitter region of the electric type, the 14th
and forming a trench-shaped second region.
次に本発明を図面を用いてより詳細に説明する。 Next, the present invention will be explained in more detail using the drawings.
第１図は、本発明の製造方法によって形成されるバイポ
ーラトランジスタの一実施例の断面図である。このトラ
ンジスタは第２図および第３図に示すようにして形成さ
れる。FIG. 1 is a cross-sectional view of an embodiment of a bipolar transistor formed by the manufacturing method of the present invention. This transistor is formed as shown in FIGS. 2 and 3.
すなわち、まず第２図に示すように、バイポーラトラン
ジスタのコレクタであるＮ型半導体領域１に、Ｐ型のベ
ース領域２を形成し、酸化膜５を設け、浅い第１導電型
の第２の領域４を形成すべき部分の酸化膜を除去し、例
えばプラズマ法により膜厚１〜２μ程度の窒化膜６を成
長させる。その後、第３図に示す様に、異方性のドライ
エッチ（例えば几ＩＥ等）によって窒化膜をエツチング
し、酸化膜５の内側に窒化膜６が残る構造を形成し、Ｎ
型不純物をイオン注入で打ち込み、熱処理を行って深い
エミッタ領域３を形成する。久に、窒化膜６をホットリ
ン酸等の手段で窒化膜６を選択的に除去し、Ｎ型不純物
を約８００″Ｃ！程度の低温で拡散し、浅い第１導電型
の第２の領域を形成する。この結果、第１図に示した構
造が得られる。That is, as shown in FIG. 2, first, a P-type base region 2 is formed in an N-type semiconductor region 1, which is the collector of a bipolar transistor, an oxide film 5 is provided, and a shallow second region of the first conductivity type is formed. The oxide film 4 is removed from the portion where the nitride film 4 is to be formed, and a nitride film 6 having a thickness of about 1 to 2 μm is grown by, for example, a plasma method. Thereafter, as shown in FIG. 3, the nitride film is etched by anisotropic dry etching (for example, IE etching) to form a structure in which the nitride film 6 remains inside the oxide film 5.
A type impurity is implanted by ion implantation, and a deep emitter region 3 is formed by performing heat treatment. After a while, the nitride film 6 was selectively removed using hot phosphoric acid or the like, and N-type impurities were diffused at a low temperature of about 800"C! to form a shallow second region of the first conductivity type. As a result, the structure shown in FIG. 1 is obtained.
以上、詳細に説明したように、本発明の製造方法により
イオン注入による深いエミッタ領域と、拡散による浅い
エミッタ領域を持つ構造を形成することにより、イオン
注入に起因して発生する結晶欠陥がバイポーラトランジ
スタのエミッタ、ベース接合より離され、エミッタ、ベ
ース接合のリーク電流を防止できる効果がある。As described above in detail, by forming a structure with a deep emitter region by ion implantation and a shallow emitter region by diffusion using the manufacturing method of the present invention, crystal defects caused by ion implantation can be removed from the bipolar transistor. The emitter and base junctions are separated from each other, which has the effect of preventing leakage current at the emitter and base junctions.
第１図は本発明の一実施例によるトランジスタの断面図
、第２図および第３図は、製造工程途中の断面図である
。
１・・・・・・Ｎ型半導体領域、２・・・・・・ベース
領域（Ｐ型）、３・・・・・・イオン注入で形成される
深いエミッタ領域、４・・・・・・浅い第１導電型の第
２の領域、５・・・・・・酸化膜、６・・・・・・窒化
膜。
、５（２−二′二・・・・・、
代理人 弁理士 内 原 日１・ ・第２ 図FIG. 1 is a cross-sectional view of a transistor according to an embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views during the manufacturing process. 1...N-type semiconductor region, 2...Base region (P-type), 3...Deep emitter region formed by ion implantation, 4... Shallow second region of the first conductivity type, 5... oxide film, 6... nitride film. , 5 (2-2'2..., Agent Patent Attorney Uchihara Day 1... Figure 2)
Claims (1)
一部を除いて第１の絶縁膜を形成する工程と、前記ベー
ス領域の一部および前記第１の絶縁膜を覆うように第２
の絶縁膜を形成する工程と、前記第２の絶縁膜を選択的
エッチングして前記第１の絶縁膜の内側に部分的に前記
第２の絶縁膜を残す工程と、前記第１の絶縁膜および残
った第２の絶縁膜をマスクに不純物をイオン注入してエ
ミッタ領域を形成する工程と前記残った第２の絶縁膜を
除去し、不純物を拡散して前記エミッタ領域よりも広く
かつ浅い領域を形成する工程とを有することを特徴とす
る半導体装置の製造方法。forming a base region in the collector region, forming a first insulating film except for a part of the base region; and a second insulating film covering a part of the base region and the first insulating film.
forming an insulating film; selectively etching the second insulating film to partially leave the second insulating film inside the first insulating film; and forming the first insulating film. and forming an emitter region by ion-implanting impurities using the remaining second insulating film as a mask, and removing the remaining second insulating film and diffusing the impurities into a region wider and shallower than the emitter region. 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18531185A JPS6245065A (en) | 1985-08-22 | 1985-08-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18531185A JPS6245065A (en) | 1985-08-22 | 1985-08-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6245065A true JPS6245065A (en) | 1987-02-27 |
Family
ID=16168628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18531185A Pending JPS6245065A (en) | 1985-08-22 | 1985-08-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6245065A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02181933A (en) * | 1989-01-09 | 1990-07-16 | Toshiba Corp | Semiconductor device provided with bipolar transistor and manufacture thereof |
| JP2006196550A (en) * | 2005-01-11 | 2006-07-27 | Denso Corp | Method of manufacturing semiconductor device |
-
1985
- 1985-08-22 JP JP18531185A patent/JPS6245065A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02181933A (en) * | 1989-01-09 | 1990-07-16 | Toshiba Corp | Semiconductor device provided with bipolar transistor and manufacture thereof |
| JP2006196550A (en) * | 2005-01-11 | 2006-07-27 | Denso Corp | Method of manufacturing semiconductor device |
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