JPS63308384A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS63308384A JPS63308384A JP62145489A JP14548987A JPS63308384A JP S63308384 A JPS63308384 A JP S63308384A JP 62145489 A JP62145489 A JP 62145489A JP 14548987 A JP14548987 A JP 14548987A JP S63308384 A JPS63308384 A JP S63308384A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- current
- metallic
- thin film
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims description 2
- 238000000137 annealing Methods 0.000 abstract description 17
- 239000010408 film Substances 0.000 abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 9
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 4
- 230000003449 preventive effect Effects 0.000 abstract 2
- 239000007769 metal material Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明は、絶縁ゲート型薄膜トランジスタのドレイン電
極及びソース電極を、金属層、絶縁物薄層、コンタクト
層の積層構造としたことにより、金属材料のコンタクト
層への拡散を阻止し、オフ電流がアニールによって変化
することを防止したものである。[Detailed Description of the Invention] [Summary] The present invention provides a drain electrode and a source electrode of an insulated gate thin film transistor with a laminated structure of a metal layer, an insulator thin layer, and a contact layer. This prevents the off-state current from changing due to annealing.
本発明は液晶駆動用薄膜トランジスタ（ＴＰＴ）に関す
る。The present invention relates to a thin film transistor (TPT) for driving a liquid crystal.
ＴＰＴ駆動液晶ディスプレイは大容量、高品質の表示が
実現できることから、ポータプルＴＶ。TPT-driven liquid crystal displays are popular for portable TVs because of their large capacity and high quality display.
ＯＡ端末機用など各方面において実用に供されるように
なっている。It has come to be put into practical use in various fields, such as for office automation terminals.
ＴＰＴはゲート電圧による５〜７桁のコンダクタンスの
変化を利用し、液晶のスイッチングを行うが、オフ状態
で十分な高抵抗が得られることが必要である。しかしな
がらオフ電流を再現性よく制御することは困難であり、
特に製造工程において熱処理が加えられると、ソース・
ドレイン電極材料の金属が拡散し、その影響でオフ電流
が増大する。TPT switches the liquid crystal by utilizing a change in conductance of 5 to 7 orders of magnitude depending on the gate voltage, but it is necessary to obtain a sufficiently high resistance in the off state. However, it is difficult to control the off-current with good reproducibility;
Especially when heat treatment is applied during the manufacturing process, the source
The metal of the drain electrode material diffuses, resulting in an increase in off-state current.
第３図は従来のＴＰＴのアニールによるオフ電流の変化
、即ち、ゲート電圧Ｖ６に対するドレイン電流■。特性
のアニール温度依存性を示す図である。同図に見られる
ように、アニール温度が高いほどオフ電流の増加も大き
くなる。FIG. 3 shows the change in off-state current due to annealing of a conventional TPT, that is, the drain current vs. gate voltage V6. FIG. 3 is a diagram showing the dependence of characteristics on annealing temperature. As seen in the figure, the higher the annealing temperature, the greater the increase in off-state current.
第４図は従来のＴＰＴの構造を示す要部断面図である。FIG. 4 is a sectional view of a main part showing the structure of a conventional TPT.
従来のＴＰＴは、絶縁性基板１上にＴｉ（チタン）等か
らなるゲート電極６を形成し、これを被覆するゲート絶
縁膜として５ｉＮ（窒化シリコン）Ｎ２を形成し、その
上に半導体層としてａ−３ｉ１３．コンタクト層として
のｎ”Ｓｉ層４、ドレイン及びソース電極材料のＡｆの
ような金属層５を積層する。In conventional TPT, a gate electrode 6 made of Ti (titanium) or the like is formed on an insulating substrate 1, 5iN (silicon nitride) N2 is formed as a gate insulating film covering this, and a semiconductor layer is formed on top of the gate electrode 6. -3i13. An n''Si layer 4 as a contact layer and a metal layer 5 such as Af as a drain and source electrode material are laminated.
Ｌ記構造でオーミックコンタクト部はａ−３ｉ（アモル
ファスシリコン）層３．ｎ’ ＳｉＮ４゜金属層５の積
層構造を有するため、熱処理により金属層５の材料がｎ
”ｓｉ層４に拡散し、ａ−３ｉ層３とｎ”Ｓｉ層４との
界面に達すると、正孔に対する電流バスができてＴＰＴ
のオフ電流が増大する。金属の拡散する量はアニール温
度とともに増大し、アニール温度の増大とともに正孔電
流が増すため、前記第３図に示した如くアニール温度が
高くなるほどオフ電流が増大していく。In the L structure, the ohmic contact portion is an a-3i (amorphous silicon) layer 3. Since it has a laminated structure of n' SiN4° metal layer 5, the material of metal layer 5 changes to n' by heat treatment.
When it diffuses into the "Si layer 4" and reaches the interface between the a-3i layer 3 and the "n" Si layer 4, a current bus is created for the holes and the TPT
The off-state current increases. The amount of metal diffusion increases with the annealing temperature, and the hole current increases as the annealing temperature increases, so as shown in FIG. 3, the higher the annealing temperature, the more the off-state current increases.
ＴＰＴの製造工程においては３００°Ｃ程度の熱処理は
工程上不可欠であるため、凡そ３００°Ｃ程度のアニー
ルによってオフ電流が増大しないＴＰＴ構造成いはＴＰ
Ｔの製造方法の出現が強く要望されている。In the TPT manufacturing process, heat treatment at about 300°C is essential, so the TPT structure that does not increase off-state current by annealing at about 300°C is TP.
There is a strong demand for a method for producing T.
そこで本発明においては、３００°Ｃ程度の熱処理によ
るオフ電流の増大を防止できるようにすることを目的と
する。Therefore, an object of the present invention is to prevent an increase in off-state current due to heat treatment at about 300°C.
〔問題点を解決するための手段］
本発明においては、上述の金属の拡散によるオフ電流の
増大を抑制するため、オーミック電極のｎ”Ｓｉ層と金
属層との間に、非常に薄い絶縁膜Ｎ（膜厚１〜５ｎｍ）
を設け、これによって金属のｎゝＳｉＮへの拡散を阻止
する。このような金属の拡散阻止層としては、ＳｉＮ、
ＰＳＧ等の拡散阻止能力が貰い絶縁層を用いる。[Means for solving the problem] In the present invention, in order to suppress the increase in off-current due to the above-mentioned metal diffusion, a very thin insulating film is provided between the n''Si layer and the metal layer of the ohmic electrode. N (film thickness 1-5 nm)
is provided to prevent metal diffusion into the nSiN. As such a metal diffusion prevention layer, SiN,
An insulating layer with diffusion blocking ability such as PSG is used.
絶縁膜の電流−電圧特性は一般に非線型性を示し、特に
膜厚が薄い場合、電流がトンネリングによって流れるた
め、低電圧（０，２Ｖ）で１μＡ程度の電流を得ること
は可能である。ＴＰＴがオフの時はチャネルは高抵抗で
あるため、ドレイン電圧ＶＤはほぼチャネルにかかるが
、ＴＰＴがオンの時はチャネルは低抵抗になって、ｖｏ
はほぼソース・ドレイン電極の絶縁膜にかかり、トンネ
リングによって上記薄い絶縁膜を貫通する電流が流れる
ため、ソース・ドレイン間の抵抗は小さくなり、オン状
態を保つことができる。The current-voltage characteristics of an insulating film generally exhibit nonlinearity, and when the film is particularly thin, current flows by tunneling, so it is possible to obtain a current of about 1 μA at a low voltage (0.2 V). When the TPT is off, the channel has a high resistance, so the drain voltage VD is almost applied to the channel, but when the TPT is on, the channel has a low resistance and the vo
is almost applied to the insulating film of the source/drain electrodes, and a current flows through the thin insulating film by tunneling, so that the resistance between the source and drain becomes small and the on state can be maintained.
ソース・ドレイン電極部の絶縁膜は厚いほど金属の拡散
阻止能力は高いが、絶縁膜の厚さが５ｎｍ以上であると
トンネル電流が流れにくくなる。The thicker the insulating film in the source/drain electrode portion is, the higher the ability to prevent metal diffusion, but if the insulating film is 5 nm or more thick, it becomes difficult for tunnel current to flow.
従って絶縁膜の厚さはこれ以下にすることが必要である
。Therefore, the thickness of the insulating film needs to be less than this.
第１図に本発明の実施例であるＴＰＴの断面図を示す。 FIG. 1 shows a sectional view of a TPT according to an embodiment of the present invention.
ガラス基板のような絶縁性基板１上にまず種子ビーム蒸
着法でＴｉ（チタン）を約７０ｎｍの厚さに形成した後
、フォトリソグラフィ工程でパターニングを行なってゲ
ート電極６を形成する。First, Ti (titanium) is formed to a thickness of about 70 nm on an insulating substrate 1 such as a glass substrate by a seed beam evaporation method, and then patterned by a photolithography process to form a gate electrode 6.
次いでＰ−ＣＶＤ （プラズマ化学気相成長）法で５ｉ
Ｎ（窒化シリコン）層２を厚さ約２００ ｎ ｍ 。Next, 5i was formed using P-CVD (plasma chemical vapor deposition) method.
N (silicon nitride) layer 2 is approximately 200 nm thick.
ａ−３ｉ（非晶質シリコン）層３を約１１００ｎ。The a-3i (amorphous silicon) layer 3 has a thickness of about 1100 nm.
ｎ″Ｓｔｂ コン）層７を約３ｎｍの厚さに同一真空中で積層する。n″Stb Con) Layer 7 is deposited to a thickness of about 3 nm in the same vacuum.
各膜の形成する際の圧力、電力の条件、及び反応ガスと
その流量は、ＳｉＮ層２が０．２Ｔｏｒｒ。The pressure and power conditions, as well as the reaction gas and its flow rate when forming each film, were 0.2 Torr for the SiN layer 2.
２００ Ｗ、 Ｓ ｉ Ｈ４／ Ｎ Ｈ３がそれぞれ５
０Ｓｃｃｍ 。200 W, S i H4/NH3 are each 5
0Sccm.
ａ−３ｉ層３は０．７ Ｔｏｒｒ、５０Ｗ、 Ｓ ｉＨ
４が２５０Ｓｃｃｍ、 ｎ” Ｓ ｉ層４はＩ Ｔｏｒ
ｒ、 ５０Ｗ、 Ｓ ｉ Ｈ４／ＰＨ，がそれぞれ１５
０／１５０ Ｓｃｃｍ、 Ｓ ｉ Ｏｚ層７は０．１５
Ｔｏｒｒ、 ５０Ｗ、 Ｓ ｉ Ｈａ ／Ｎ２０がそ
れぞれ１５ Ｓｃｃｍ／ ７５ Ｓｃｃｍである。a-3i layer 3 is 0.7 Torr, 50W, SiH
4 is 250Sccm, n”Si layer 4 is I Tor
r, 50W, S i H4/PH, are each 15
0/150 Sccm, S i Oz layer 7 is 0.15
Torr, 50W, and S i Ha /N20 are each 15 Sccm/75 Sccm.
続いて電子ビーム蒸着法で、１Ｍ（アルミニウム）等を
蒸着して金属層５を形成した後、フォトリソグラフィ工
程でパターニングを行い、金属層５゜Ｓ ｉｏｚ Ｎ７
．ｎ” Ｓ １層４をエツチングして、１０８ｍのチャ
ネル８を形成する。Subsequently, a metal layer 5 is formed by depositing 1M (aluminum) or the like using an electron beam evaporation method, and then patterning is performed using a photolithography process to form a metal layer 5°S ioz N7.
．． Etch the n'' S 1 layer 4 to form a 108m channel 8.
このようにして形成したＴＰＴのオフ電流とアニール温
度との関係を第２図に示す。同図の白丸はＬ記−実施例
で得られたＴＰＴのオフ電流を示し、黒丸は従来のＴＰ
Ｔのオフ電流の変化を示すもので、本発明と比較のため
に掲げた。同図より明らかな如く、本実施例のＴＦＴは
アニール温度によってオフ電流が変化せずに一定であり
、プロセスで不可欠な３００°Ｃの熱処理後では従来型
と比較して３桁はどオフ電流を低減でき、ＴＰＴの特性
が大きく向上する。FIG. 2 shows the relationship between the off-state current and annealing temperature of the TPT thus formed. The white circles in the figure indicate the off-state current of the TPT obtained in Example L, and the black circles indicate the off-state current of the TPT obtained in Example L.
This figure shows the change in the off-state current of T, and is included for comparison with the present invention. As is clear from the figure, the TFT of this example has a constant off-state current that does not change depending on the annealing temperature, and after the 300°C heat treatment that is essential in the process, the off-state current is three orders of magnitude higher than that of the conventional type. can be reduced, and the characteristics of TPT are greatly improved.
なお上記一実施例では金属の拡散阻止のための絶縁物薄
層７としてＳｉ２０層を用いた例を説明したが、これに
変えてＳｉＮ層を用いてもよい。In the above embodiment, an example was described in which a Si20 layer was used as the insulating thin layer 7 for preventing metal diffusion, but a SiN layer may be used instead.
また、絶縁物薄層７の厚さはトンネル効果が生じる厚さ
であることが必要で、公知の如くきわめて薄いものでな
ければならない。本発明を実施するためには、これの厚
さは凡そ５ｎｍ以下であることが必要である。一方余り
薄くすると均一に成膜できず、実用上約１ｎｍ以上のｊ
γさとすることが必要である。Further, the thickness of the insulating thin layer 7 must be such that a tunnel effect occurs, and as is well known, it must be extremely thin. In order to carry out the present invention, it is necessary that this thickness be approximately 5 nm or less. On the other hand, if it is made too thin, it will not be possible to form a uniform film, and in practical terms
It is necessary to make it γ.
以上説明した如く本発明によれば、アニール温度に関係
なく安定したオフ電流が得られ、３００°Ｃのアニール
後では従来型と比較して約３桁オフ電流を低減でき、Ｔ
ＰＴの特性が向上する。As explained above, according to the present invention, a stable off-state current can be obtained regardless of the annealing temperature, and after annealing at 300°C, the off-state current can be reduced by about three orders of magnitude compared to the conventional type.
The characteristics of PT are improved.
第１図は本発明一実施例のＴＰＴの構造を示す要部断面
図、
第２図は上記一実施例のオフ電流のアニール温度依存性
を示す図、
第３図は従来のＴＰＴのアニールによるオフ電流の変化
を示す図、
第４図は従来のＴＰＴの構造説明図である。
図において、１は絶縁性基板、２はＳｉＮ層、３はａ−
３ｉｊｉｉ、４はｎ”ｓｉ層、５は金属層、６はゲート
電極、７は絶縁薄Ｎ（Ｓ ｉ Ｏｘ ）層を示す。
ｕＥＩＨ４＃：１４ＴＦＴ４ Ｎｔｆｆｉｍ第１図
イシ谷日月−尖オ酸イ列−才フｅ；む７二一ル号【刀Ｃ
泊り５十１第２図Fig. 1 is a cross-sectional view of the main part showing the structure of a TPT according to an embodiment of the present invention, Fig. 2 is a diagram showing the annealing temperature dependence of the off-state current of the above embodiment, and Fig. 3 is a diagram showing the annealing temperature of a conventional TPT. FIG. 4 is a diagram showing changes in off-state current, and is an explanatory diagram of the structure of a conventional TPT. In the figure, 1 is an insulating substrate, 2 is a SiN layer, and 3 is a-
3ijii, 4 is an n"si layer, 5 is a metal layer, 6 is a gate electrode, and 7 is an insulating thin N (S i Ox ) layer. uEIH4#: 14TFT4 Ntffim Figure 1 Row-Saif e;mu721 [sword C
Tomari 511 Figure 2
Claims (1)
）とが積層されたドレイン電極及びソース電極を具備す
る絶縁ゲート型薄膜トランジスタにおいて、 前記コンタクト層（４）と金属層（５）との間に絶縁物
薄層（７）を介在させたことを特徴とする薄膜トランジ
スタ。[Claims] A contact layer (4) and a metal layer (5) are provided on the surface of the semiconductor layer (3).
), the insulated gate thin film transistor having a drain electrode and a source electrode stacked together, characterized in that an insulating thin layer (7) is interposed between the contact layer (4) and the metal layer (5). thin film transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62145489A JPS63308384A (en) | 1987-06-10 | 1987-06-10 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62145489A JPS63308384A (en) | 1987-06-10 | 1987-06-10 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63308384A true JPS63308384A (en) | 1988-12-15 |
Family
ID=15386444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62145489A Pending JPS63308384A (en) | 1987-06-10 | 1987-06-10 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63308384A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992006490A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Device self-alignment by propagation of a reference structure's topography |
| US5196912A (en) * | 1988-10-28 | 1993-03-23 | Casio Computer Co., Ltd. | Thin film transistor having memory function and method for using thin film transistor as memory element |
| US5202572A (en) * | 1988-09-21 | 1993-04-13 | Fuji Xerox Co., Ltd. | Thin film transistor |
| US5391902A (en) * | 1989-05-20 | 1995-02-21 | Fujitsu Limited | Semiconductor device and production method thereof |
| US6399428B2 (en) | 1997-10-21 | 2002-06-04 | Kabushiki Kaisha Advanced Display | Liquid crystal display and manufacturing process of thin film transistor used therein |
| JP2008010801A (en) * | 2005-08-17 | 2008-01-17 | Kobe Steel Ltd | Source/drain electrode, thin-film transistor substrate and manufacture method thereof, and display device |
| WO2008047726A1 (en) * | 2006-10-13 | 2008-04-24 | Kabushiki Kaisha Kobe Seiko Sho | Thin film transistor substrate and display device |
| JP2008118124A (en) * | 2006-10-13 | 2008-05-22 | Kobe Steel Ltd | Thin film transistor substrate and display device |
| WO2009128542A1 (en) * | 2008-04-18 | 2009-10-22 | 株式会社神戸製鋼所 | Wiring structure, thin film transistor substrate, method for manufacturing thin film transistor substrate, and display device |
| CN101866879A (en) * | 2009-04-17 | 2010-10-20 | 日立电线株式会社 | Interconnecting structure production method, and interconnecting structure |
| US7943933B2 (en) | 2007-06-20 | 2011-05-17 | Kobe Steel, Ltd. | Thin film transistor substrate and display device with oxygen-containing layer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62160769A (en) * | 1986-01-10 | 1987-07-16 | Hitachi Ltd | Thin film transistor element |
| JPS63185066A (en) * | 1987-01-28 | 1988-07-30 | Matsushita Electric Ind Co Ltd | Thin film transistor |
-
1987
- 1987-06-10 JP JP62145489A patent/JPS63308384A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62160769A (en) * | 1986-01-10 | 1987-07-16 | Hitachi Ltd | Thin film transistor element |
| JPS63185066A (en) * | 1987-01-28 | 1988-07-30 | Matsushita Electric Ind Co Ltd | Thin film transistor |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5202572A (en) * | 1988-09-21 | 1993-04-13 | Fuji Xerox Co., Ltd. | Thin film transistor |
| US5196912A (en) * | 1988-10-28 | 1993-03-23 | Casio Computer Co., Ltd. | Thin film transistor having memory function and method for using thin film transistor as memory element |
| US5391902A (en) * | 1989-05-20 | 1995-02-21 | Fujitsu Limited | Semiconductor device and production method thereof |
| US5468664A (en) * | 1989-05-20 | 1995-11-21 | Fujitsu Limited | Method of making semiconductor device with alignment marks |
| WO1992006490A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Device self-alignment by propagation of a reference structure's topography |
| GB2253742A (en) * | 1990-10-05 | 1992-09-16 | Gen Electric | Device self-alignment by propagation of a reference structure's topography |
| US5340758A (en) * | 1990-10-05 | 1994-08-23 | General Electric Company | Device self-alignment by propagation of a reference structure's topography |
| US6399428B2 (en) | 1997-10-21 | 2002-06-04 | Kabushiki Kaisha Advanced Display | Liquid crystal display and manufacturing process of thin film transistor used therein |
| JP2008010801A (en) * | 2005-08-17 | 2008-01-17 | Kobe Steel Ltd | Source/drain electrode, thin-film transistor substrate and manufacture method thereof, and display device |
| WO2008047726A1 (en) * | 2006-10-13 | 2008-04-24 | Kabushiki Kaisha Kobe Seiko Sho | Thin film transistor substrate and display device |
| JP2008118124A (en) * | 2006-10-13 | 2008-05-22 | Kobe Steel Ltd | Thin film transistor substrate and display device |
| KR101043508B1 (en) | 2006-10-13 | 2011-06-23 | 가부시키가이샤 고베 세이코쇼 | Thin film transistor substrate and display device |
| US8853695B2 (en) | 2006-10-13 | 2014-10-07 | Kobe Steel, Ltd. | Thin film transistor substrate including source-drain electrodes formed from a nitrogen-containing layer or an oxygen/nitrogen-containing layer |
| US7943933B2 (en) | 2007-06-20 | 2011-05-17 | Kobe Steel, Ltd. | Thin film transistor substrate and display device with oxygen-containing layer |
| TWI425640B (en) * | 2007-06-20 | 2014-02-01 | Kobe Steel Ltd | Thin film transistor substrate and display device |
| WO2009128542A1 (en) * | 2008-04-18 | 2009-10-22 | 株式会社神戸製鋼所 | Wiring structure, thin film transistor substrate, method for manufacturing thin film transistor substrate, and display device |
| JP2009278057A (en) * | 2008-04-18 | 2009-11-26 | Kobe Steel Ltd | Wiring structure, thin film transistor substrate, method for manufacturing thin film transistor substrate, and display device |
| US8299614B2 (en) | 2008-04-18 | 2012-10-30 | Kobe Steel, Ltd. | Interconnection structure, a thin film transistor substrate, and a manufacturing method thereof, as well as a display device |
| CN101866879A (en) * | 2009-04-17 | 2010-10-20 | 日立电线株式会社 | Interconnecting structure production method, and interconnecting structure |
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