JPS63185066A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS63185066A JPS63185066A JP1763387A JP1763387A JPS63185066A JP S63185066 A JPS63185066 A JP S63185066A JP 1763387 A JP1763387 A JP 1763387A JP 1763387 A JP1763387 A JP 1763387A JP S63185066 A JPS63185066 A JP S63185066A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- thin film
- film transistor
- tin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 27
- 239000010408 film Substances 0.000 claims abstract description 65
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 241000282376 Panthera tigris Species 0.000 description 1
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は薄膜トランジスターに関する。特に耐熱性に優
れ、且つ低抵抗の電極構造を有するａ（アモルファス）
−８ｉ半導体トランジスターに関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to thin film transistors. a (amorphous), which has particularly excellent heat resistance and a low-resistance electrode structure.
-Relating to an 8i semiconductor transistor.
従来の技術
従来、薄膜トランジスターにおいては第４図に示すよう
に透明基板、例えばガラス基板３１上に設けたゲート電
極３２上にゲート絶縁膜として例えば膜厚４００ｎｍの
ＳｉＮ膜３３、膜厚１１００ｎのｉ（真性）−ａ−３ｉ
膜３４を順次積層し、次にａ−３ｉ膜とのオーミック接
触を得るために、１−ａ−３ｉ膜上に高不純物濃度を有
するｎ＋−ａ−３ｉ膜３５を積層したうえに電極膜３６
を設けてソース電極３６ａとドレイン電極３６ｂを形成
していた。この電極膜材料には、Ｃｒ。2. Description of the Related Art Conventionally, in a thin film transistor, as shown in FIG. 4, a gate electrode 32 is provided on a transparent substrate, for example a glass substrate 31, and a gate insulating film, for example, an SiN film 33 with a thickness of 400 nm and an i film with a thickness of 1100 nm are formed. (Intrinsic)-a-3i
The films 34 are sequentially laminated, and then in order to obtain ohmic contact with the a-3i film, an n+-a-3i film 35 having a high impurity concentration is laminated on the 1-a-3i film, and then an electrode film 36 is formed.
were provided to form a source electrode 36a and a drain electrode 36b. This electrode film material includes Cr.
Ａｕ、Ｎｉ、Ｎｉ／Ｃｒ、Ａ Ｉ、ＩＴＯなどが用いら
れている。一般に、薄膜トランジスターを集積する場合
、浮遊容量による信号遅延を防ぐため配線抵抗の低いＡ
Ｉを主として用いている。Au, Ni, Ni/Cr, AI, ITO, etc. are used. Generally, when integrating thin film transistors, A with low wiring resistance is used to prevent signal delay due to stray capacitance.
I is mainly used.
発明が解決しようとする問題点
以上のような薄膜トランジスターの電極構造に於てＡｌ
膜を使用する場合、２５０ｏＣ以上の温度に於て薄膜ト
ランジスターを熱処理すると、Ａｌに対するＳｉの固溶
限界が大きいため熱処理によりｎ＋−ａ−８ｉｌｌが侵
食されると同時に微量のＡｌがｎ＋−ａ−８ｉ膜中に拡
散しオーミック接触を劣下させ、薄膜トランジスターと
して機能しなくなるという問題点を有していた。即ち、
従来の電極構造では例えば実装組立途中の熱処理プロセ
スないし実動作中に薄膜トランジスターが正常に動作し
なくなるという問題点を有していた。Problems to be Solved by the Invention In the electrode structure of thin film transistors as described above, Al
When using a thin film transistor, if a thin film transistor is heat-treated at a temperature of 250oC or higher, the solid solubility limit of Si in Al is large, so the heat treatment corrodes n+-a-8ill, and at the same time a small amount of Al becomes n+-a- This has the problem that it diffuses into the 8i film and degrades ohmic contact, making it no longer functional as a thin film transistor. That is,
Conventional electrode structures have had the problem that, for example, the thin film transistor does not operate normally during a heat treatment process during assembly or during actual operation.
本発明は実装組立中の熱処理プロセス或は薄膜トランジ
スターとしての実働作中の発熱による経年劣化に耐える
安定した耐熱性を有する薄膜トランジスターの電極構造
を提供するものである。The present invention provides an electrode structure for a thin film transistor that has stable heat resistance and can withstand aging deterioration due to heat treatment during assembly and assembly or heat generated during actual operation of the thin film transistor.
問題点を解決するための手段
そこで、本発明者らは、上記した目的に鑑みなされたも
のである。即ち、高不純物濃度アモルファスＳｉ半導体
からなるコンタクト開口面にコンタクトする電極構造を
有する薄膜トランジスターに於て、上記コンタクト開口
面上に設けられたＴｉＮ膜と、上記ＴｉＮ膜上に設けら
れたＡＩを主成分とする電極膜を有する構造からなるも
のである。Means for Solving the Problems Therefore, the present inventors have devised the above-mentioned object. That is, in a thin film transistor having an electrode structure in contact with a contact opening made of a highly impurity-concentrated amorphous Si semiconductor, a TiN film provided on the contact opening and an AI provided on the TiN film are mainly used. It consists of a structure having an electrode film as a component.
更に、上記ＴｉＮ膜と電極膜との間にＴｉ膜からなる中
間層を設けることにより密着性が更に良くなる。Further, by providing an intermediate layer made of a Ti film between the TiN film and the electrode film, the adhesion is further improved.
作用
以上のような本発明による薄膜トランジスターの電極構
造は、ＴｉＮ膜を例えば、ｎ＋−ａ−８ｉ膜と電極膜と
の間に設けであるので組立中での熱プロセス処理、或は
実動作中での経年劣下おいても、ｎ＋−ａ−３ｉ膜と電
極膜とがＴｉＮ膜を拡散して反応することがなく、層状
電極構造が破壊されることはない。それ故、本発明によ
る電極構造は耐熱性に優れ、コンタクト抵抗も十分低い
安定した薄膜トランジスターを実現することが出来る。In the electrode structure of the thin film transistor according to the present invention as described above, a TiN film is provided between, for example, an n+-a-8i film and an electrode film, so that thermal processing during assembly or during actual operation can be easily performed. Even if the TiN film deteriorates over time, the n+-a-3i film and the electrode film do not diffuse into the TiN film and react with each other, and the layered electrode structure is not destroyed. Therefore, the electrode structure according to the present invention has excellent heat resistance and can realize a stable thin film transistor with sufficiently low contact resistance.
実施例
以下、添付図面を参照して本発明による薄膜トランジス
ターの実施例を説明する。Embodiments Hereinafter, embodiments of a thin film transistor according to the present invention will be described with reference to the accompanying drawings.
第１図は、本発明による電極構造をゆうする薄膜トラン
ジスターの１実施例を示す要部断面図である。すなはち
、ガラス基板１１上に設けた例えばＣｒ膜からなるゲー
ト電極１２上に、ゲート絶縁膜１３として例えば膜厚４
００ｎｍのＳｉＮ膜、膜厚１１００ｎの１−ａ−８ｉ膜
１４を順次積層し、次に１−ａ−３ｉ膜とのオーミック
接触を得るために、１−ａ−８ｉ膜上に高不純物濃度を
有するｎ＋−ａ−３ｉ膜１５を５０ｎｍ積層したのち、
膜厚５０ｎｍのＴｉＮ膜上６を反応性スッパタリング法
にａ線間ｓｉターゲットを用いＡｒ−Ｎ２混合ガス中で
形成し、さらに例えばＡｌ−３％Ｓｉからなる膜厚５０
０ｎｍの電極膜１７を積層したのち、同図のごとくソー
ス電極１７ａおよびドレイン電極１７ｂをパターン形成
することにより薄膜トランジスターが形成される。FIG. 1 is a sectional view of essential parts showing one embodiment of a thin film transistor having an electrode structure according to the present invention. In other words, a gate insulating film 13 with a thickness of 4, for example, is formed on a gate electrode 12 made of, for example, a Cr film provided on a glass substrate 11.
A SiN film with a thickness of 00 nm and a 1-a-8i film 14 with a thickness of 1100 nm are sequentially laminated, and then a high impurity concentration is applied to the 1-a-8i film in order to obtain ohmic contact with the 1-a-3i film. After laminating 50 nm of n+-a-3i films 15 having
A TiN film 6 with a thickness of 50 nm is formed using a reactive sputtering method using an A-line Si target in an Ar-N2 mixed gas, and further a film with a thickness of 50 nm made of, for example, Al-3%Si is formed.
After laminating electrode films 17 of 0 nm thickness, a thin film transistor is formed by patterning a source electrode 17a and a drain electrode 17b as shown in the figure.
第３図に本発明よる電極構造にかかるＥＳＣＡの結果を
示す。同図において縦軸は各元素の任意のスケールによ
る濃度を示し、横軸に示すスッパタ時間は多層膜の表面
からの距離を示す。同図は真空中４００℃、２時間焼鈍
後の各元素の膜厚方向の濃度プロファイルを示しており
、ＡＩの濃度曲線ｅｌはｎ＋−ａ−８ｔの濃度曲線ｅ２
と重なる領域をもたず、ＴｉＮ膜が拡散バリア一層とじ
て働きｎ＋−ａ−３ｉ膜中へのＡＩの拡散を防止してお
り、本発明の効果が示された。FIG. 3 shows the results of ESCA regarding the electrode structure according to the present invention. In the figure, the vertical axis shows the concentration of each element on an arbitrary scale, and the sputtering time shown on the horizontal axis shows the distance from the surface of the multilayer film. The figure shows the concentration profile of each element in the film thickness direction after annealing at 400°C for 2 hours in vacuum, and the concentration curve el of AI is the concentration curve e2 of n+-a-8t.
The TiN film acts as a diffusion barrier to prevent the diffusion of AI into the n+-a-3i film, demonstrating the effectiveness of the present invention.
第２図に第２の実施例を示す。同図において、１１．１
２．１３．１４．１５．１６．１７．１７ａ、１７ｂは
、第１図と同一である。すなわち、第１図に示す実施例
１の構成においてＴｉＮ膜上６と電極膜であるＡｌ−３
％Ｓｉ膜１７との間にＴｉ膜２１を例えば、膜厚５０ｎ
ｍにて積層する。この場合、特にＴ ｉ ＰＩＡ ２１
とＡｌ−３％Ｓｉ膜を同一真空容器内で連続形成すると
密着性が著しく改善される。FIG. 2 shows a second embodiment. In the same figure, 11.1
2.13.14.15.16.17.17a and 17b are the same as in FIG. That is, in the structure of Example 1 shown in FIG.
For example, a Ti film 21 with a thickness of 50 nm is placed between the %Si film 17.
Laminate at m. In this case, especially T i PIA 21
When the and Al-3%Si films are successively formed in the same vacuum container, the adhesion is significantly improved.
発明の効果
以上の説明から明らかなように、本発明による薄膜トラ
ンジスターの電極構造は、ｎ” ａ−８ｉ膜からなる
コンタクト開口面とＡＩを主成分とする電極膜との間に
、ＴｉＮ膜を設けているので、きはめてコンタクト抵抗
が低く、且つ耐熱性に優れている。従って、本発明によ
れば、電極構造上コンタクト抵抗が低く且つ耐熱性の優
れた薄膜トランジスターを実現できる。Effects of the Invention As is clear from the above explanation, the electrode structure of the thin film transistor according to the present invention has a TiN film between the contact opening surface made of the n''a-8i film and the electrode film mainly composed of AI. Since the electrode structure is provided, the contact resistance is low and the heat resistance is excellent. Therefore, according to the present invention, a thin film transistor having a low contact resistance and excellent heat resistance due to the electrode structure can be realized.
第１図は本発明の一実施例にかかる薄膜トランジスター
の要部断面構造を示°す図、第２図は本発明の第２の実
施例による薄膜トランジスターの要部断面構造を示す図
、第３図は耐熱性を示す図パターン形成直後の真空中４
００℃、２時間焼鈍した後の濃度プロファイルを示す図
、第４図は従来の薄膜トランジスターの要部断面構造を
示す図である。
１１・・・・ガラス基板、１２・・・・ゲート電極、１
３・・・・ゲート絶縁膜、１４−ｉ−ａ−３ｉｌ！Ｉ、
１５−ｎ＋−ａ−８ｉ膜、１６＝・ＴｉＮ膜、１７・・
・・電極膜、２１・・・・ＴｉＮ膜。
代理人の氏名 弁理士 中尾敏男 ほか１名Ａｌｌ ７
１Ｎ ／ｆＬ＋−工−δｉ
幌と、２時間虎銑漿
スバッグ時間 （分ジ
軽
＋４
ト
褐 外のFIG. 1 is a diagram showing a cross-sectional structure of a main part of a thin film transistor according to an embodiment of the present invention, FIG. 2 is a diagram showing a cross-sectional structure of a main part of a thin film transistor according to a second embodiment of the present invention, and FIG. Figure 3 shows heat resistance in vacuum immediately after pattern formation 4
FIG. 4 is a diagram showing a concentration profile after annealing at 00° C. for 2 hours, and FIG. 4 is a diagram showing a cross-sectional structure of a main part of a conventional thin film transistor. 11...Glass substrate, 12...Gate electrode, 1
3...Gate insulating film, 14-ia-3il! I,
15-n+-a-8i film, 16=・TiN film, 17.
...Electrode film, 21...TiN film. Name of agent: Patent attorney Toshio Nakao and 1 other person All 7
1N /fL+-Eng-δi hood and 2 hours tiger pigskin subbag time (min.
Claims (2)
ト開口面にコンタクトする電極構造を有する薄膜トラン
ジスターにおいて、上記コンタクト開口面上に設けられ
たＴｉＮ膜と、上記ＴｉＮ膜上に設けられたＡｌを主成
分とする電極膜を有することを特徴とする薄膜トランジ
スター。(1) In a thin film transistor having an electrode structure in contact with a contact opening made of highly impurity-concentrated amorphous Si, the main components are a TiN film provided on the contact opening and Al provided on the TiN film. A thin film transistor characterized in that it has an electrode film.
層を設けたことを特徴とする特許請求の範囲第１項記載
の薄膜トランジスター。(2) The thin film transistor according to claim 1, characterized in that an intermediate layer made of a Ti film is provided between the TiN film and the electrode film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1763387A JPS63185066A (en) | 1987-01-28 | 1987-01-28 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1763387A JPS63185066A (en) | 1987-01-28 | 1987-01-28 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63185066A true JPS63185066A (en) | 1988-07-30 |
Family
ID=11949269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1763387A Pending JPS63185066A (en) | 1987-01-28 | 1987-01-28 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63185066A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63308384A (en) * | 1987-06-10 | 1988-12-15 | Fujitsu Ltd | Thin film transistor |
| JP2000216403A (en) * | 1994-07-30 | 2000-08-04 | Semiconductor Energy Lab Co Ltd | Active matrix circuit |
| US6448612B1 (en) | 1992-12-09 | 2002-09-10 | Semiconductor Energy Laboratory Co., Ltd. | Pixel thin film transistor and a driver circuit for driving the pixel thin film transistor |
-
1987
- 1987-01-28 JP JP1763387A patent/JPS63185066A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63308384A (en) * | 1987-06-10 | 1988-12-15 | Fujitsu Ltd | Thin film transistor |
| US6448612B1 (en) | 1992-12-09 | 2002-09-10 | Semiconductor Energy Laboratory Co., Ltd. | Pixel thin film transistor and a driver circuit for driving the pixel thin film transistor |
| US6608353B2 (en) | 1992-12-09 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having pixel electrode connected to a laminate structure |
| US7045399B2 (en) | 1992-12-09 | 2006-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
| US7061016B2 (en) | 1992-12-09 | 2006-06-13 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
| US7105898B2 (en) | 1992-12-09 | 2006-09-12 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
| US7547916B2 (en) | 1992-12-09 | 2009-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
| US7897972B2 (en) | 1992-12-09 | 2011-03-01 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
| US8294152B2 (en) | 1992-12-09 | 2012-10-23 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit including pixel electrode comprising conductive film |
| JP2000216403A (en) * | 1994-07-30 | 2000-08-04 | Semiconductor Energy Lab Co Ltd | Active matrix circuit |
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