JPS584327Y2 - amplifier circuit - Google Patents
amplifier circuitInfo
- Publication number
- JPS584327Y2 JPS584327Y2 JP1976054418U JP5441876U JPS584327Y2 JP S584327 Y2 JPS584327 Y2 JP S584327Y2 JP 1976054418 U JP1976054418 U JP 1976054418U JP 5441876 U JP5441876 U JP 5441876U JP S584327 Y2 JPS584327 Y2 JP S584327Y2
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- point
- circuit
- resistor
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Amplifiers (AREA)
Description
【考案の詳細な説明】
本考案は負帰還回路を有する増幅回路に関し、特に段間
結合用のコンデンサとして単極性のものが使用出来るよ
う出力回路を工夫した増幅回路に関する。[Detailed Description of the Invention] The present invention relates to an amplifier circuit having a negative feedback circuit, and more particularly to an amplifier circuit in which the output circuit is devised so that a unipolar capacitor can be used as an interstage coupling capacitor.
二電源方式で増幅回路の出力点より前段に負帰還を施す
ように構成された増幅回路においては、出力点を直流的
に略０■に保つ必要がある。In an amplifier circuit configured to apply negative feedback to a stage preceding the output point of the amplifier circuit using a two-power supply system, it is necessary to maintain the output point at approximately 0.times. in terms of direct current.
又、増幅回路のダイナミックレンジを大きくする為にも
出力点を０■に保たなければならない。Furthermore, in order to increase the dynamic range of the amplifier circuit, the output point must be kept at 0.
しかしながら、増幅回路の出力点の電圧は回路を構成す
る部品のバラツキ等により正負に２００ｍＶ程度の誤差
を生じる。However, the voltage at the output point of the amplifier circuit has an error of about 200 mV in the positive and negative directions due to variations in the components constituting the circuit.
すなわち前記増幅回路の出力点の電圧は、Ｏｖに設定し
たとしても、実際には正負２００ ｍＶ程度の値となる
。That is, even if the voltage at the output point of the amplifier circuit is set to Ov, it actually has a value of about 200 mV between positive and negative.
その為、前記増幅回路と後段回路とを結合するコンデン
サとしては無極性のものを使用しなければならない。Therefore, a non-polar capacitor must be used for coupling the amplifier circuit and the subsequent circuit.
無極性のコンデンサは性能的に単極性のものと比べて劣
るとともに、高価となる欠点がある。Non-polar capacitors have the disadvantage of being inferior in performance to unipolar capacitors and being more expensive.
本考案は上述の点に鑑み威されたもので、安価で性能の
良い単極性のコンデンサ、例えばタンタルコンデンサを
段間結合コンデンサとして使用出来るように出力段を改
良した増幅回路を提供せんとするものである。The present invention was developed in view of the above points, and aims to provide an amplifier circuit with an improved output stage so that an inexpensive and high-performance unipolar capacitor, such as a tantalum capacitor, can be used as an interstage coupling capacitor. It is.
以下本考案の実施例に基き、図面を参照しながら説明す
る。Embodiments of the present invention will be described below with reference to the drawings.
図は本考案に係る増幅回路をイコライザ増幅器に使用し
た一例を示すもので、１は入力端子、Ｚはエミッタが共
通接続された一対の同導電型トランジスタ３及び４から
成る第１差動増幅回路、旦は同様にエミッタが共通接続
された一対の同導電型トランジスタ６及び７から成る第
２差動増幅回路、８はイコライザ増幅器としての周波数
特性を得る為の周波数回路、９は前記第２差動増幅回路
５の負荷となる負荷抵抗、１０は前記負荷抵抗９に直列
接続された小抵抗、１１は正の電源端子、１２は負の電
源端子、１３は出力端子、１４は段間結合コンデンサで
ある。The figure shows an example in which the amplifier circuit according to the present invention is used in an equalizer amplifier, where 1 is an input terminal, and Z is a first differential amplifier circuit consisting of a pair of transistors 3 and 4 of the same conductivity type whose emitters are commonly connected. , a second differential amplifier circuit consisting of a pair of transistors 6 and 7 of the same conductivity type whose emitters are connected in common, 8 a frequency circuit for obtaining frequency characteristics as an equalizer amplifier, and 9 the second differential amplifier circuit. A load resistor serving as a load of the dynamic amplifier circuit 5, 10 a small resistor connected in series with the load resistor 9, 11 a positive power supply terminal, 12 a negative power supply terminal, 13 an output terminal, and 14 an interstage coupling capacitor. It is.
しかして前記第１差動増幅回路２の一方のトランジスタ
３のベースは抵抗１５及びコンデンサ１６を介して入力
端子１に接続され、前記第２差動増幅回路５の一対のト
ランジスタ６及び７のベースは、それぞれ前記第１差動
増幅回路２の一対のトランジスタ３及び４のコレクタに
接続されている。The base of one transistor 3 of the first differential amplifier circuit 2 is connected to the input terminal 1 via a resistor 15 and a capacitor 16, and the bases of the pair of transistors 6 and 7 of the second differential amplifier circuit 5 are connected to the input terminal 1 through a resistor 15 and a capacitor 16. are connected to the collectors of the pair of transistors 3 and 4 of the first differential amplifier circuit 2, respectively.
又、前記第２差動増幅回路５の一方のトランジスタ７の
コレクタ（点Ａ）は、単極性の段間結合コンデンサ１４
を介して出力端子１３に接続されるとともに、小抵抗１
０及び負荷抵抗９の直列回路を介して正の電源端子１１
に接続されている。Further, the collector (point A) of one transistor 7 of the second differential amplifier circuit 5 is connected to a unipolar interstage coupling capacitor 14.
is connected to the output terminal 13 via a small resistor 1.
0 and the positive power supply terminal 11 through a series circuit of the load resistor 9
It is connected to the.
更に周波数回路８は、前記小抵抗１０と負荷抵抗９との
接続中点（点Ｂ）と前記第１差動増幅回路２の他方のト
ランジスタ４のベースとの間の負帰還回路に挿入されて
いる。Further, the frequency circuit 8 is inserted into a negative feedback circuit between the connection midpoint (point B) between the small resistor 10 and the load resistor 9 and the base of the other transistor 4 of the first differential amplifier circuit 2. There is.
次に動作を説明する。Next, the operation will be explained.
入力信号端子１に印加された信号は、第１差動増幅回路
２で増幅された後第２差動増幅回路５で増幅される。A signal applied to the input signal terminal 1 is amplified by the first differential amplifier circuit 2 and then amplified by the second differential amplifier circuit 5.
しかして、前記第２差動増幅回路５の一方のトランジス
タ７のコレクタ（点Ａ）に得られた信号は、小抵抗１０
を介して周波数回路８に帰還され、該周波数回路８で所
定の周波数特性を与えられた後第１差動増幅回路２の他
方のトランジスタ４のベースに印加される。Therefore, the signal obtained at the collector (point A) of one transistor 7 of the second differential amplifier circuit 5 is transmitted through the small resistor 10.
The signal is fed back to the frequency circuit 8 via the frequency circuit 8, and after being given a predetermined frequency characteristic by the frequency circuit 8, it is applied to the base of the other transistor 4 of the first differential amplifier circuit 2.
従って前記第２差動増幅器５の一方のトランジスタ７の
コレクタ（点Ａ）から股間結合コンデンサ１４を介して
出力端子１３に所定の周波数特性（例えばＲＩＡＡ特性
）を有する出力信号が得られる。Therefore, an output signal having predetermined frequency characteristics (for example, RIAA characteristics) is obtained from the collector (point A) of one transistor 7 of the second differential amplifier 5 to the output terminal 13 via the crotch coupling capacitor 14.
従来回路の如く小抵抗１０を有しない場合は、正負２０
０ ｍＶの範囲で点Ａの電圧が変動するが、本考案の如
く小抵抗１０を設けると、点Ａの電圧は負方向にしか変
動しない。If the conventional circuit does not have a small resistance of 10, the positive and negative 20
The voltage at point A fluctuates in the range of 0 mV, but if a small resistor 10 is provided as in the present invention, the voltage at point A fluctuates only in the negative direction.
すなわち、例えば小抵抗１０として１００ 、！Ｑの抵
抗を用い、負荷抵抗９として１０にΩの抵抗を用い、正
負の電源端子１１及び１２に印加される電源電圧を±３
５Ｖとすれば、完全バランス時すなわちＢ点がＯＶの時
、Ａ点は一３５０ｍＶとなり、Ｂ点が＋２００ｍＶの時
、Ａ点は一１４８ｍＶとなり、Ｂ点が−２００ｍＶの時
、Ａ点は一５５２ｍＶとなる従って、Ａ点には負の電圧
しか表われず、段間結合コンデンサ１４としては単極性
のコンデンサを使用出来る。That is, for example, a small resistance of 10 is 100,! A resistor of Q is used, a resistor of 10 Ω is used as the load resistor 9, and the power supply voltage applied to the positive and negative power supply terminals 11 and 12 is ±3.
If the voltage is 5V, in perfect balance, that is, when point B is OV, point A is -350 mV, when point B is +200 mV, point A is -148 mV, and when point B is -200 mV, point A is -552 mV. Therefore, only a negative voltage appears at point A, and a unipolar capacitor can be used as the interstage coupling capacitor 14.
Ｂ点の電圧は小抵抗１０を挿入するしないにかかわらず
、同様の値をとるので、負帰還動作には何ら悪影響を及
ぼさない。Since the voltage at point B takes the same value regardless of whether or not the small resistor 10 is inserted, it does not have any adverse effect on the negative feedback operation.
以上述べた如く本考案に係る増幅回路を用いれば、増幅
回路の出力点の電圧極性が素子のバラツキ等によって変
化することがないので単極性のコンテ゛ンサの使用が可
能であり、コストの低減を計ることが出来る実用的なも
のである。As described above, if the amplifier circuit according to the present invention is used, the voltage polarity at the output point of the amplifier circuit will not change due to variations in the elements, so a unipolar capacitor can be used, and costs can be reduced. It is a practical thing that can be done.
尚、本考案に係る増幅回路は、実施例の如きイコライザ
増幅器ばかりでなく、様々な増幅器に使用可能である。Note that the amplifier circuit according to the present invention can be used not only for the equalizer amplifier as in the embodiment, but also for various amplifiers.
図は本考案に係る増幅回路の一実施例を示す回路図であ
る。
主な図番の説明 ２・・・・・・第１差動増幅回路、５
・・・・・・第２差動増幅回路、９・・・・・・負荷抵
抗、１０・・・・・・小抵抗、１４・・・・・・段間結
合コンデンサ。The figure is a circuit diagram showing one embodiment of an amplifier circuit according to the present invention. Explanation of main drawing numbers 2...First differential amplifier circuit, 5
...Second differential amplifier circuit, 9...Load resistance, 10...Small resistance, 14...Interstage coupling capacitor.
Claims (1)
負荷抵抗との間に小抵抗を挿入し、前記負荷抵抗と小抵
抗との接続点から前段に負帰還を施すとともに、前記出
力点と後段回路とを単極性のコンテ゛ンサで結合したこ
とを特徴とする増幅回路。In a dual power supply type amplifier circuit, a small resistor is inserted between the output point of the amplifier circuit and the load resistor, negative feedback is applied to the previous stage from the connection point between the load resistor and the small resistor, and the output point and the load resistor are connected to each other. An amplifier circuit characterized in that it is connected to a subsequent stage circuit using a unipolar capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976054418U JPS584327Y2 (en) | 1976-04-27 | 1976-04-27 | amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976054418U JPS584327Y2 (en) | 1976-04-27 | 1976-04-27 | amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52145747U JPS52145747U (en) | 1977-11-04 |
| JPS584327Y2 true JPS584327Y2 (en) | 1983-01-25 |
Family
ID=28513432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1976054418U Expired JPS584327Y2 (en) | 1976-04-27 | 1976-04-27 | amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS584327Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3366889A (en) * | 1964-09-14 | 1968-01-30 | Rca Corp | Integrated electrical circuit |
-
1976
- 1976-04-27 JP JP1976054418U patent/JPS584327Y2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3366889A (en) * | 1964-09-14 | 1968-01-30 | Rca Corp | Integrated electrical circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52145747U (en) | 1977-11-04 |
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