JPS63274153A - Substrate for mounting semiconductor device - Google Patents
Substrate for mounting semiconductor deviceInfo
- Publication number
- JPS63274153A JPS63274153A JP62110103A JP11010387A JPS63274153A JP S63274153 A JPS63274153 A JP S63274153A JP 62110103 A JP62110103 A JP 62110103A JP 11010387 A JP11010387 A JP 11010387A JP S63274153 A JPS63274153 A JP S63274153A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- substrate
- bumps
- mounting
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 229910000679 solder Inorganic materials 0.000 claims abstract description 22
- 239000011521 glass Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 9
- 239000000463 material Substances 0.000 abstract description 6
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000007767 bonding agent Substances 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 229910052759 nickel Inorganic materials 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000007598 dipping method Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920013716 polyethylene resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置実装用基板における。バンプ構造及
びその材料に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a substrate for mounting a semiconductor device. Related to bump structure and its material.
従来の導体装置実装用基板は、第２図に示すようにパッ
ケージソゲされた半導体装置７を別の基板８にあらかじ
め半１月付しておき、柔軟性のある配線材＄４９を用い
て半田付などの方法で半導体装用基板ｌと前記別の基板
２を接続していた。As shown in FIG. 2, a conventional board for mounting a conductor device is one in which a packaged semiconductor device 7 is attached to another board 8 in advance, and soldered using a flexible wiring material $49. The semiconductor mounting substrate 1 and the other substrate 2 were connected by a method such as attaching.
しかし、従来の半導体装用基板は、実装する半導体装置
がパッケージソゲされていなければならず、半導実装用
基板の他に別の基板が必要で、パッケージングレだ半導
体を実装した基板と半導体装用基板を接続する配線材料
も必要であった、したがって、材料か多く工程数も多い
ことより、半導体装置コストが高くなるという問題点を
有していた。However, with conventional semiconductor mounting boards, the semiconductor device to be mounted must be packaged and soldered, and a separate board is required in addition to the semiconductor mounting board. Wiring materials for connecting the substrates were also required, which resulted in the problem that the cost of the semiconductor device was high due to the large number of materials and the number of steps.
本発明はこの様次問題点を解決するもので、その目的と
するところは、半導体装置実装用基板に半導体装置の電
極と電気的接続を得るバンプを容易に設はパッケージン
グが前の半導体装置を基板に直接実装することより、材
料数及び工程数が少なく、実装コストが安価にできる半
導体装置実装用基板を提供することにある。The present invention is intended to solve these problems, and its purpose is to easily provide bumps for electrical connection with the electrodes of the semiconductor device on a substrate for mounting the semiconductor device, and to process the semiconductor device before packaging. It is an object of the present invention to provide a substrate for mounting a semiconductor device, which requires fewer materials and steps and can reduce mounting costs by directly mounting the semiconductor device on the substrate.
本発明の半導体装置実装用基板は、導電性を有する透明
配線パターン上に金属膜を形成したガラス基板において
、前記金属膜にレーザー照射することにより金属膜を選
択的に蒸発させて半導体装置の電極に対応した島状の金
属膜を形成し、前記ガラ基板を溶融した半田に浸すこと
により前記島状の金属膜上に半田に付着させてバンブを
形成したことを特徴とする。The substrate for mounting a semiconductor device of the present invention is a glass substrate in which a metal film is formed on a conductive transparent wiring pattern, and the metal film is selectively evaporated by irradiating the metal film with a laser to form electrodes of the semiconductor device. The present invention is characterized in that an island-shaped metal film corresponding to the above is formed, and the glass substrate is immersed in molten solder to form bumps on the island-shaped metal film by adhering the solder to the solder.
第１図は、本発明の半導体装置用実用基板の製造工程を
示した断面図である。FIG. 1 is a sectional view showing the manufacturing process of a practical substrate for a semiconductor device according to the present invention.
まずａ図の如くガラス基板ｌの表面の酸化インジウムの
透明導電膜をスパッタにより１００ＯＡ程度の厚さに形
成し、バターニングして透明導電膜の配線パターン２を
得た後、無電解ニッケルメッキを行って前記透明導電膜
の配線パターン上に３０００″Ａ程度のニッケル配線パ
ターン３を形成する。First, as shown in figure a, a transparent conductive film of indium oxide is formed on the surface of the glass substrate l to a thickness of about 100 OA by sputtering, and after patterning to obtain the wiring pattern 2 of the transparent conductive film, electroless nickel plating is applied. Then, a nickel wiring pattern 3 of about 3000''A is formed on the wiring pattern of the transparent conductive film.
次にｂ図の如く半導体装置の電極に対応した位置のニッ
ケル配線パターン４を残した他の部分に、レーザー光線
５を２００１Ｌｍ程度の幅で照射してニッケルを蒸発さ
せる。ここで、前記透明導膜の配線パターンは、レーザ
ー光線を透過するために損傷を受けずにそのまま残る。Next, as shown in Fig. b, a laser beam 5 is irradiated with a width of about 2001 Lm to evaporate the nickel onto the other part where the nickel wiring pattern 4 remains at a position corresponding to the electrode of the semiconductor device. Here, the wiring pattern of the transparent conductive film remains undamaged because it transmits the laser beam.
したがって、透明導電膜の配線パターン上における半導
体装置の電極と対応した位置に、ニッケルが島状に形成
されることになる。Therefore, nickel is formed in the form of islands on the wiring pattern of the transparent conductive film at positions corresponding to the electrodes of the semiconductor device.
次に、ｂ図で得られたガラス基板にフラックスを塗布し
て２００＠Ｃ〜２５０°Ｃに溶融したＳｎ：Ｐｂ＝６：
４の半田に１秒間〜２秒間浸すことによりニッケルの配
線パターン上に半田が溶着して、０図の如く半田バンプ
６が形成される。島状に形成されたニッケルの大きさが
１００ ｇ、ｍ角程度の場合、半田バンブの高さは５ｐ
ｍ〜１０ルｍ程度になる。半［■バンプの高さは、ガラ
ス基板を浸す時の溶融半田の温度により制御することが
できる。最後に、ガラス基板をアルコールなどで洗浄し
、フラックスを落として完成する。Next, flux was applied to the glass substrate obtained in figure b and melted at 200＠C to 250°C.Sn:Pb=6:
By dipping it in the solder No. 4 for 1 to 2 seconds, the solder is welded onto the nickel wiring pattern, forming solder bumps 6 as shown in FIG. If the size of the nickel island formed is about 100 g, m square, the height of the solder bump is 5p.
It will be about 10 m to 10 m. The height of the half [■ bump can be controlled by the temperature of the molten solder when dipping the glass substrate. Finally, the glass substrate is cleaned with alcohol and the flux is removed to complete the process.
以上の方法により完成した半導体装置実装基板に半導体
装置を実装する方法を以下に述べる。ここで、実装する
半導体は、パッケージされたものでなく、ウェハーから
切り出した状態のベアチップである。A method for mounting a semiconductor device on the semiconductor device mounting board completed by the above method will be described below. Here, the semiconductor to be mounted is not a packaged one, but a bare chip cut out from a wafer.
まずｔｌＳ３図（ａ）に示す様に前記半導体装置実装基
板ｌの半田バンプを形成した部分、すなわち、半導体装
置が位置する部分に紫外線硬化型接着剤ｌＯを塗布する
。接着剤の塗布は、スクリーン印刷法による塗布が、塗
布量、塗布範囲伴に制御し易い、また、ディスペンサー
による接着剤塗布も可能である。First, as shown in FIG. 3(a), an ultraviolet curing adhesive lO is applied to the portion of the semiconductor device mounting board l where the solder bumps are formed, that is, the portion where the semiconductor device is located. The adhesive can be applied by screen printing because it is easy to control the amount and range of application, and it is also possible to apply the adhesive by using a dispenser.
次に（Ｂ）図に示す様に基板１の半田バンプ６を半導体
装置のアルミ電極１１の位置合せを行い、電極当り５０
ｇ〜１００ｇの荷重で圧着しながら、ガラス基板１の半
導体装置とは反対側の面から紫外線１２を照射する。こ
の時、電極当たり５０ｇ〜１００ｇの荷重により半田バ
ンプ６がつぶれを起こし、半導体装置のアルミ電極と半
田バンプの接触面積を大きくするため、電気的接続が有
効にとられることになる。また、前記荷重により、半導
体装置のアルミ電極と半田バンプの間にある紫外線硬化
型接着剤は排除される。この工程において、半導体装置
のアルミ電極が半田バンプの中に拡散して消滅するのを
防ぐために、半導体装置及び基板は半田の溶融温度以上
に上げてはならない。Next, as shown in the figure (B), the solder bumps 6 of the substrate 1 are aligned with the aluminum electrodes 11 of the semiconductor device, and
The glass substrate 1 is irradiated with ultraviolet rays 12 from the surface opposite to the semiconductor device while being pressed under a load of g to 100 g. At this time, the solder bumps 6 are crushed by a load of 50 g to 100 g per electrode, increasing the contact area between the aluminum electrodes of the semiconductor device and the solder bumps, so that an effective electrical connection can be established. Moreover, the ultraviolet curing adhesive between the aluminum electrode and the solder bump of the semiconductor device is removed by the load. In this step, the temperature of the semiconductor device and substrate must not be raised above the melting temperature of the solder in order to prevent the aluminum electrodes of the semiconductor device from diffusing into the solder bumps and disappearing.
以上の様に実装された半導体装置は、紫外線硬化接着剤
の接着剤力のみによって基板上に接触・固定される。The semiconductor device mounted as described above is contacted and fixed onto the substrate only by the adhesive force of the ultraviolet curing adhesive.
この半導体装用基板はガラス基板であるが、他のポリエ
チレン樹脂などで作られた耐熱性のある透明基板におい
ても実施可能である。Although this semiconductor mounting substrate is a glass substrate, it is also possible to use a heat-resistant transparent substrate made of other polyethylene resin or the like.
また、半導体装置実装用基板が不透明の場合、半導体装
置を実装するための接着剤は熱硬化型接着剤を用いる。Further, when the semiconductor device mounting substrate is opaque, a thermosetting adhesive is used as the adhesive for mounting the semiconductor device.
ただし、この場合においても半導体装置及び基板の温度
は半田の溶融温度以上に上げてはならない。すなわち半
田の溶融温度以下で硬化する接着剤を使用する。However, even in this case, the temperature of the semiconductor device and the substrate must not be raised above the melting temperature of the solder. That is, an adhesive that hardens at a temperature below the melting temperature of the solder is used.
以上述べたように本発明によれば、半導体装置をウェハ
ーから切り出したままの状態で実装することができるの
で、半導体装置のパッケージングが不必要になる。また
、半導体装置実装用基板には容易にバンプを形成でき、
直接半導体装置を実装できるため、基板製作コストが削
減でき、さらに１外付基板が不要なことにより実装面積
を大幅に縮小することが可能となる。As described above, according to the present invention, semiconductor devices can be mounted in a state in which they are cut out from a wafer, so packaging of the semiconductor devices becomes unnecessary. In addition, bumps can be easily formed on substrates for mounting semiconductor devices.
Since semiconductor devices can be directly mounted, board manufacturing costs can be reduced, and since no external board is required, the mounting area can be significantly reduced.
装置実装用基板の一実施例を示す工程断面図。FIG. 3 is a process cross-sectional view showing an example of a device mounting board.
第２図は従来の半導体装置実装用基板を示す断面図。FIG. 2 is a sectional view showing a conventional semiconductor device mounting board.
第３図（ａ）、（ｂ）は本発明の半導体装用基板に半導
体装置を実装する工程の一実施例を示した断面図。FIGS. 3(a) and 3(b) are cross-sectional views showing an embodiment of the process of mounting a semiconductor device on a semiconductor mounting substrate of the present invention.
１・・・・・・半導体装置実装用基板
２・・・・・・透明配線パターン
３・・・・・・ニッケル配線パターン
４・・・・・・島状ニッケル配線パターン５・・・・・
・レーザー光
６・・・・・・半田バンブ
と
第２図1... Semiconductor device mounting substrate 2... Transparent wiring pattern 3... Nickel wiring pattern 4... Island-like nickel wiring pattern 5...
・Laser light 6...Solder bump and Figure 2
Claims (1)
ガラス基板において、前記金属膜にレーザー照射するこ
とにより金属膜を選択的に蒸発させて半導体装置の電極
に対応した島状の金態属膜を形成し、前記ガラス基板を
、溶融した半田に浸すことにより、前記島状の金属膜上
に半田を溶着させてバンプを形成したことを特徴とする
半導体装置実装用基板。In a glass substrate in which a metal film is formed on a conductive transparent wiring pattern, the metal film is selectively evaporated by irradiating the metal film with a laser to form an island-shaped metal film corresponding to an electrode of a semiconductor device. A substrate for mounting a semiconductor device, characterized in that the glass substrate is immersed in molten solder to weld the solder onto the island-shaped metal film to form bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62110103A JPS63274153A (en) | 1987-05-06 | 1987-05-06 | Substrate for mounting semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62110103A JPS63274153A (en) | 1987-05-06 | 1987-05-06 | Substrate for mounting semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63274153A true JPS63274153A (en) | 1988-11-11 |
Family
ID=14527113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62110103A Pending JPS63274153A (en) | 1987-05-06 | 1987-05-06 | Substrate for mounting semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63274153A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02135767A (en) * | 1988-11-17 | 1990-05-24 | Hitachi Ltd | Formation of pattern and brazing method |
-
1987
- 1987-05-06 JP JP62110103A patent/JPS63274153A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02135767A (en) * | 1988-11-17 | 1990-05-24 | Hitachi Ltd | Formation of pattern and brazing method |
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