JPS62287647A - Connecting bump semiconductor chip - Google Patents

Connecting bump semiconductor chip

Info

Publication number
JPS62287647A
JPS62287647A JP61132327A JP13232786A JPS62287647A JP S62287647 A JPS62287647 A JP S62287647A JP 61132327 A JP61132327 A JP 61132327A JP 13232786 A JP13232786 A JP 13232786A JP S62287647 A JPS62287647 A JP S62287647A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor chip
bump
alloy
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61132327A
Other languages
Japanese (ja)
Inventor
Hisako Mori
久子 森
Yoshihiro Bessho
芳宏 別所
Yasuhiko Horio
泰彦 堀尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61132327A priority Critical patent/JPS62287647A/en
Publication of JPS62287647A publication Critical patent/JPS62287647A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
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    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
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    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
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    • H01L2224/13075—Plural core members
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    • H01L2224/13082—Two-layer arrangements
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    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To establish a reliable connection between a transparent electrode and a semiconductor chip by a method wherein an electrode protruding from a pad is built of a specified alloy. CONSTITUTION:An Al electrode 2 is formed on a silicon substrate 1 and, on the Al electrode 2, an Sn plating 5 and in plating 6 are provided with the intermediary of an intermediate metal layer 4 for the formation of a bump. Heat is applied to the bump for fusion into a hemispheric in-Sn alloy bump 7. Positioning is accomplished between a semiconductor chip 13 furnished with said bump 7 and a transparent terminal electrode 12 on a glass substrate 10. A proper heating process follows wherein fusion results in the simultaneous establishment of electrical connection and mechanical adhesion. The junction is reliable because the In-Sn alloy is relatively soft and strong against thermal fatigue. In addition, there will be a lower contact resistance.

Description

【発明の詳細な説明】 ３、発明の詳細な説明 産業上の利用分野 本発明は、半導体チップに代表される、チップ状の電子
部品を基板上の端子電極群に接続する際の半導体チップ
の接続バンブ（端子）に関するものである。Detailed Description of the Invention 3. Detailed Description of the Invention Industrial Field of Application The present invention relates to the application of semiconductor chips when connecting chip-shaped electronic components, typified by semiconductor chips, to a group of terminal electrodes on a substrate. This relates to connection bumps (terminals).

従来の技術 従来、電子部品の接続端子と基板上の回路パターン端子
との接続には半田付け（Ｐｂ　−Ｓｎ半田）がよく利用
されていたが、近年、例えばＩＣフラットパッケージ等
の小型化と、接続端子の増加により接続端子間、いわゆ
るピッチ間隔が次第に狭くなり、従来の半田付は技術で
対処することが困難になってきた。また最近では電卓、
電子時計あるいは液晶デバイス等にあっては、裸の半導
体チップをガラス基板上の透明電極にフェースダウンで
直付けして実装面積の効率的使用と配線の合理化を図ろ
うとする動きがあり、従来法に代わる有効かつ微細な電
気的接続手段が望まれている。裸の半導体チップをガラ
ス基板上の透明電極に電気的に接続する方法としては、
電子材料１９８５年９月号（Ｐ　４９）に示されている
様に異方導電性シートを使った圧接方式が知られている
。Conventional technology In the past, soldering (Pb-Sn solder) was often used to connect the connection terminals of electronic components and the circuit pattern terminals on the board, but in recent years, with the miniaturization of IC flat packages, for example, With the increase in the number of connection terminals, the distance between the connection terminals, the so-called pitch interval, has gradually become narrower, making it difficult to solve the problem with conventional soldering techniques. Also recently, calculators,
For electronic watches, liquid crystal devices, etc., there is a movement to directly attach bare semiconductor chips face-down to transparent electrodes on glass substrates in order to use mounting area more efficiently and rationalize wiring. An alternative effective and fine electrical connection means is desired. As a method for electrically connecting a bare semiconductor chip to a transparent electrode on a glass substrate,
As shown in the September 1985 issue of Electronic Materials (P49), a pressure welding method using an anisotropic conductive sheet is known.

半導体チップを直接実装する、いわゆるフリップチップ
実装においては、従来からＰｂ　−Ｓｎからなる半田バ
ンプを用いたのが一般的である。液晶デバイス等のガラ
ス基板上の透明電極上へのフリップチップ実装も種々検
討されているが、その主な方法の１つとしては、透明電
極上に端子電極としてＣｒ、　Ｃｕ等の電極を形成し、
この上にＰｂ　−Ｓｎの半田バンプが形成された半導体
チップを実装する方法がある。また他の例としてはＡｕ
バンプと異方導電性シートを使った方式がある。そこで
従来例として、異方導電性シートを使った圧接方式を図
４゜５を用いて説明する。第５図で示しである様に、半
導体チップのアルミニウムパッド上に、Ａｕバンプ１６
を形成し、これと対応する電極をパネル電極上に設け１
８、パネル電極とＡｕバンプ間に凸状のこの導電性シー
トを介在させ、押さえ金具１５で圧接した構成により半
導体チップをガラス基板の透明電極上に接続している。In so-called flip-chip mounting, in which semiconductor chips are directly mounted, solder bumps made of Pb-Sn have conventionally been commonly used. Various types of flip-chip mounting on transparent electrodes on glass substrates such as liquid crystal devices have been studied, but one of the main methods is to form an electrode of Cr, Cu, etc. as a terminal electrode on the transparent electrode. ,
There is a method of mounting a semiconductor chip on which Pb-Sn solder bumps are formed. Another example is Au
There is a method that uses bumps and anisotropically conductive sheets. Therefore, as a conventional example, a pressure welding method using an anisotropic conductive sheet will be explained with reference to FIG. 4.5. As shown in FIG. 5, Au bumps 16 are placed on the aluminum pads of the semiconductor chip.
is formed, and a corresponding electrode is provided on the panel electrode 1.
8. This convex conductive sheet is interposed between the panel electrode and the Au bump, and the semiconductor chip is connected to the transparent electrode of the glass substrate by pressure contact with the presser metal fitting 15.

発明が解決しようとする問題点 しかしながら斯かる方法にあっては異方導電性シートを
別工程で作り込む必要があり、工程が複雑になる。また
Ａｕバンプを使用する為コストアップの要因となる加え
て、その精度も問題となる。Problems to be Solved by the Invention However, in such a method, it is necessary to fabricate the anisotropically conductive sheet in a separate process, which complicates the process. Furthermore, since Au bumps are used, not only is the cost increased, but also the accuracy is a problem.

また接続方式がパネル電極と回路基板との間にゼブラ状
の異方導電性シートを介在させ押さえ金具で圧接した間
接圧接方式である為、接触抵抗の増大、押さえ金具の絶
縁リークを考慮しなければならない。In addition, since the connection method is an indirect pressure welding method in which a zebra-shaped anisotropic conductive sheet is interposed between the panel electrode and the circuit board and pressed together with a holding metal fitting, consideration must be given to increased contact resistance and insulation leakage from the holding metal fitting. Must be.

本発明は上記問題点に鑑みて発明されたもので、その目
的とするところはガラス基板上に微細に形成された透明
電極と半導体チップの接続バンプを信頼性よく電気的接
続を行うことにある。The present invention was invented in view of the above-mentioned problems, and its purpose is to electrically connect a transparent electrode finely formed on a glass substrate and a connection bump of a semiconductor chip with high reliability. .

問題点を解決するための手段 上記問題点を解決するために、本発明の半導体チップの
接続バンプは、アルミニウムパッド上に中間金属層を介
してＩｎ　−Ｓｎ合金からなる突起電極を構成したこと
を特徴としている。Means for Solving the Problems In order to solve the above problems, the connection bumps of the semiconductor chip of the present invention have protruding electrodes made of an In-Sn alloy formed on the aluminum pads via an intermediate metal layer. It is a feature.

作用 本発明は上記した構成によって、従来法の様に異方導電
性シートを別工程で作るという様な、複雑な工程はなく
、Ｉｎ　−Ｓｎ合金の接続バンプ（端子）−もホトリソ
技術と蒸着法あるいはメッキ法によって構成できるので
工法も簡単で安価である。またこの接続バンプは金属材
料による合金接合であり、さらにＩｎ　−Ｓｎ合金は比
較的柔らかく熱疲労に強い為、接合部の信頼性が高くな
ると言える。加えて有機材料を使った場合に比べ接触抵
抗も低くなる。Function: Due to the above-described structure, the present invention does not require complicated processes such as creating an anisotropically conductive sheet in a separate process as in the conventional method, and connection bumps (terminals) of In-Sn alloy can also be formed using photolithography technology and vapor deposition. The construction method is simple and inexpensive because it can be constructed using a method or a plating method. Furthermore, this connection bump is an alloy bond made of a metal material, and since the In--Sn alloy is relatively soft and resistant to thermal fatigue, it can be said that the reliability of the bonded portion is high. In addition, the contact resistance is lower than when organic materials are used.

又Ｉｎ　−Ｓｎ合金は低融点の合金である為、接着時に
過大な熱および圧力がかからないという特色も備えてい
る。Furthermore, since the In--Sn alloy is an alloy with a low melting point, it also has the characteristic that excessive heat and pressure are not applied during bonding.

実施例 以下に本発明の半導体チ・ノブの接続バンプの一実施例
について図面を参照しながら説明する。第１図と第２図
は接続バンプ（端子）の構成された半導体チップの断面
図を示す。また第３図はこの接続バンプ（端子）を有す
る半導体チ・ノブをガラス基板上の透明端子電極上に実
装した時の断面図である。第４図は異方導電性シートを
用いた従来例の断面図、第５図は従来例の半導体チ・ノ
ブと異方導電性シートの断面図である。Embodiment An embodiment of a connection bump for a semiconductor chip/knob according to the present invention will be described below with reference to the drawings. 1 and 2 show cross-sectional views of a semiconductor chip configured with connection bumps (terminals). FIG. 3 is a cross-sectional view of a semiconductor chip having connection bumps (terminals) mounted on a transparent terminal electrode on a glass substrate. FIG. 4 is a cross-sectional view of a conventional example using an anisotropically conductive sheet, and FIG. 5 is a cross-sectional view of a semiconductor chip and an anisotropically conductive sheet of the conventional example.

ｌはシリコン基板、２はＡｌ電極、３は表面保護膜、４
は中間金属層、５はＳｎ層、６はＩｎＪｉｉ、７はＩｎ
　−Ｓｎ接続バンプ（端子）、１０はガラス基板、１１
は液晶、１２は透明電極、１３は半導体チップである。l is a silicon substrate, 2 is an Al electrode, 3 is a surface protective film, 4
is an intermediate metal layer, 5 is a Sn layer, 6 is InJii, 7 is In
-Sn connection bump (terminal), 10 is glass substrate, 11
1 is a liquid crystal, 12 is a transparent electrode, and 13 is a semiconductor chip.

本発明の接続ハンプ（端子）の構成法を説明する。１の
シリコン基板上にＡｌ電極２を形成し、ＳｉＯ□等の表
面保護層３を形成する。前記ＡＩ電極上にＣｒ、　Ｔｉ
等のへ１電極のバリア層とＣｕ、　Ａｕ等の密着強度強
化層からなる中間金属層４を蒸着とホトリソ技術により
形成する。次にメソキレシストをバターンニングし、Ａ
Ｉ電極上のみにＳｎメッキとＩｎメッキを行い約２０〜
３０μｍの高さのバンプを形成する。この時のメッキの
順序は適宜選択すればよい。A method of configuring the connection hump (terminal) of the present invention will be explained. An Al electrode 2 is formed on a silicon substrate 1, and a surface protection layer 3 of SiO□ or the like is formed. Cr, Ti on the AI electrode
An intermediate metal layer 4 consisting of a barrier layer of one electrode and an adhesion strength reinforcing layer of Cu, Au, etc. is formed by vapor deposition and photolithography. Next, pattern the mesochyrecyst, and
Sn plating and In plating are carried out only on the I electrode, and approximately 20~
A bump with a height of 30 μm is formed. The order of plating at this time may be selected as appropriate.

またこのバンプは蒸着法により形成してもよい。Further, this bump may be formed by a vapor deposition method.

続いてＩｎ　−Ｓｎ合金の溶融温度で加熱溶融すること
により第２図の様な半球状のＩｎ　−Ｓｎの合金バンプ
を形成する。尚Ｉｎ　−Ｓｎ合金の組成であるが、液晶
表示装置に用いる場合は１５０℃以下に液相温度をもつ
低融点の組成が適切であり、５２Ｉｎ　　４８Ｓｎの共
晶合金、あるいは５０Ｉｎ−５０Ｓｎ　（液相温度１２
５℃）５２Ｓｎ−４８Ｉｎ　（液相温度１３１℃）が適
切と言えるが、必要に応じその組成は選択すればよい。Subsequently, by heating and melting at the melting temperature of the In--Sn alloy, a hemispherical In--Sn alloy bump as shown in FIG. 2 is formed. Regarding the composition of the In-Sn alloy, when used in liquid crystal display devices, a low melting point composition with a liquidus temperature of 150°C or less is appropriate; temperature 12
5°C) 52Sn-48In (liquidus temperature 131°C) is suitable, but its composition may be selected as necessary.

前記の様にして形成された接続バンプを有する半導体チ
ップをガラス基板上の透明端子電極と位置合わせ後、適
切な加熱溶融法あるいは適切な加熱超音波法により電気
的接続と接着を同時に行う。After aligning the semiconductor chip having the connection bumps formed as described above with the transparent terminal electrodes on the glass substrate, electrical connection and adhesion are simultaneously performed by an appropriate heating melting method or an appropriate heating ultrasonic method.

発明の効果 以上の様に本発明は、半導体チップのアルミニウムパッ
ド上に中間金属層を介してＩｎ　−Ｓｎ合金からなる突
起電極を構成したことを特徴とする特許体チップの接続
バンプであり、これにより従来法の様に異方導電性シー
トを別工程で作るという様な複雑な工程はなく、Ｉｎ　
−Ｓｎ合金の接続バンプ（＠子）もメッキ法あるいは蒸
着法により構成できるので工法も簡単で安価になる。ま
た接続バンプ（端子）は金属材料による合金接合であり
、さらにＩｎ　−Ｓｎ合金は比較的柔らか（熱疲労に強
い為、接合部の信頼性も高（なる。加えて有機材料を使
った場合に比べ接触抵抗も低くなる。Ｉｎ　−Ｓｎ合金
を低融点の合金材料である為、接着時に過大な熱および
圧力がからなくなると言える。Effects of the Invention As described above, the present invention is a patented chip connection bump characterized in that a protruding electrode made of an In-Sn alloy is formed on an aluminum pad of a semiconductor chip via an intermediate metal layer. This method eliminates the complicated process of making an anisotropically conductive sheet in a separate process as in the conventional method.
-Sn alloy connection bumps (@ko) can also be constructed by plating or vapor deposition, making the construction method simple and inexpensive. In addition, the connection bumps (terminals) are alloyed with metal materials, and the In-Sn alloy is relatively soft (resistant to thermal fatigue, so the reliability of the joint is high).In addition, when organic materials are used, The contact resistance is also lower than that.Since the In--Sn alloy is an alloy material with a low melting point, it can be said that excessive heat and pressure are not applied during bonding.

【図面の簡単な説明】[Brief explanation of drawings]

第１図と第２図は接続バンプ（端子）の形成された半導
体チップの断面図、第３図はこの接続バンプ（端子）を
有する半導体チップをガラス基板上の透明端子電極上に
実装した時の断面図、第４図は異方導電性シートを用い
た実装法の断面図、第５図は従来例の半導体チップと異
方導電性シートの断面図である。 １・・・・・・シリコン基板、２・・・・・・Ａ１電極
、３・・・・・・表面保護膜、４・・・・・・中間金属
層、５・・・・・・Ｓｎ層、６・・・・・・Ｉｎ層、７
・・・・・・Ｉｎ−５ｎ接続バンプ（端子）、１０・・
・・・・ガラス基板、１１・・・・・・液晶、１２・・
・・・・透明電極、１３・・・・・・半導体チップ、１
４・・・・・・異方導電性シート、１５・・・・・・押
さえ金具、１６・・・・・・Ａｕバンブ、１７・・・・
・・ポリイミド、１８・・・・・・導電性シリコン樹脂
。 代理人の氏名　弁理士　中尾敏男　ほか１名／−−−シ
１ｊコン邑坂 ２−−−Ａｌ電境 ５−−−３ｎＪＡ 第１　図　　　　　　　　　　６−−−エ７Ｌ１７−−
−エ几−３ｒＬオ逅Δ究ンくンフ℃咋Ｓ）第２図　　７ 第３図 ／２７　　　　／２／／　　　ｙ０ 第４図 ｉ　ｓ　ｖ　　　　　／３ ！ ／？″Figures 1 and 2 are cross-sectional views of a semiconductor chip with connection bumps (terminals) formed thereon, and Figure 3 shows a semiconductor chip with connection bumps (terminals) mounted on transparent terminal electrodes on a glass substrate. 4 is a sectional view of a mounting method using an anisotropically conductive sheet, and FIG. 5 is a sectional view of a conventional semiconductor chip and an anisotropically conductive sheet. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...A1 electrode, 3...Surface protective film, 4...Intermediate metal layer, 5...Sn Layer, 6... In layer, 7
...In-5n connection bump (terminal), 10...
...Glass substrate, 11...Liquid crystal, 12...
...Transparent electrode, 13...Semiconductor chip, 1
4... Anisotropic conductive sheet, 15... Holding metal fitting, 16... Au bump, 17...
...Polyimide, 18... Conductive silicone resin. Name of agent: Patent attorney Toshio Nakao and 1 other person / --- Shi1j Kon-Usaka 2 --- Aldenkyo 5 --- 3nJA Figure 1 6--E7L17--
-E几-3rL OPENΔKUNKUNFU ℃廋S) Fig. 2 7 Fig. 3 /27 /2// y0 Fig. 4 is v /3! /? ″

Claims (1)

【特許請求の範囲】[Claims] 半導体チップのアルミニウムパッド上に中間金属層を介
してＩｎ−Ｓｎ合金からなる突起電極を構成したことを
特徴とする半導体チップの接続バンプ。A connection bump for a semiconductor chip, characterized in that a protruding electrode made of an In-Sn alloy is formed on an aluminum pad of the semiconductor chip via an intermediate metal layer.
JP61132327A 1986-06-06 1986-06-06 Connecting bump semiconductor chip Pending JPS62287647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61132327A JPS62287647A (en) 1986-06-06 1986-06-06 Connecting bump semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61132327A JPS62287647A (en) 1986-06-06 1986-06-06 Connecting bump semiconductor chip

Publications (1)

Publication Number Publication Date
JPS62287647A true JPS62287647A (en) 1987-12-14

Family

ID=15078726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61132327A Pending JPS62287647A (en) 1986-06-06 1986-06-06 Connecting bump semiconductor chip

Country Status (1)

Country Link
JP (1) JPS62287647A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000068410A (en) * 1998-08-20 2000-03-03 Nishihara Riko Kk IC PACKAGE SUCH AS BGA OR CSP WITH PLATED BUMPS AT BONDED TERMINALS, USING BONDING MATERIAL IN PLACE OF Pb
JP2004289113A (en) * 2003-03-05 2004-10-14 Mitsubishi Electric Corp Metal electrode and bonding method using same
JPWO2016056656A1 (en) * 2014-10-10 2017-09-14 石原ケミカル株式会社 Alloy bump manufacturing method
WO2022050186A1 (en) * 2020-09-04 2022-03-10 株式会社新菱 Sn-in-based low melting-point joining member, production method therefor, semiconductor electronic circuit, and mounting method therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000068410A (en) * 1998-08-20 2000-03-03 Nishihara Riko Kk IC PACKAGE SUCH AS BGA OR CSP WITH PLATED BUMPS AT BONDED TERMINALS, USING BONDING MATERIAL IN PLACE OF Pb
JP2004289113A (en) * 2003-03-05 2004-10-14 Mitsubishi Electric Corp Metal electrode and bonding method using same
JPWO2016056656A1 (en) * 2014-10-10 2017-09-14 石原ケミカル株式会社 Alloy bump manufacturing method
WO2022050186A1 (en) * 2020-09-04 2022-03-10 株式会社新菱 Sn-in-based low melting-point joining member, production method therefor, semiconductor electronic circuit, and mounting method therefor

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