JPS63272061A - Manufacture of plug-in type semiconductor device housing package - Google Patents
Manufacture of plug-in type semiconductor device housing packageInfo
- Publication number
- JPS63272061A JPS63272061A JP62106757A JP10675787A JPS63272061A JP S63272061 A JPS63272061 A JP S63272061A JP 62106757 A JP62106757 A JP 62106757A JP 10675787 A JP10675787 A JP 10675787A JP S63272061 A JPS63272061 A JP S63272061A
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- lead pin
- plug
- semiconductor device
- chamfered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 238000005498 polishing Methods 0.000 claims abstract description 25
- 238000005260 corrosion Methods 0.000 claims abstract description 15
- 230000007797 corrosion Effects 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000126 substance Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 28
- 239000011247 coating layer Substances 0.000 claims description 13
- 238000005219 brazing Methods 0.000 claims description 10
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052759 nickel Inorganic materials 0.000 abstract description 7
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 abstract description 6
- 238000009713 electroplating Methods 0.000 abstract description 6
- 229910045601 alloy Inorganic materials 0.000 abstract description 4
- 239000000956 alloy Substances 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 229910000833 kovar Inorganic materials 0.000 abstract description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000203 mixture Substances 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- 238000003860 storage Methods 0.000 description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 10
- 239000000919 ceramic Substances 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- 229910052799 carbon Inorganic materials 0.000 description 8
- 239000000843 powder Substances 0.000 description 8
- 239000006061 abrasive grain Substances 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 239000012777 electrically insulating material Substances 0.000 description 5
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011572 manganese Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 229910018106 Ni—C Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- LGQLOGILCSXPEA-UHFFFAOYSA-L nickel sulfate Chemical compound [Ni+2].[O-]S([O-])(=O)=O LGQLOGILCSXPEA-UHFFFAOYSA-L 0.000 description 1
- 229910000363 nickel(II) sulfate Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子を収納するプラグイン型半導体素子
収納用パッケージの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a plug-in type semiconductor device housing package for housing a semiconductor device.
従来、半導体素子、特に半導体集積回路素子を収納する
プラグイン型半導体素子収納用パッケージは、一般にア
ルミナセラミックス等の電気絶縁材料から成り、その上
面の略中央部に半導体集積回路素子を゛収納するための
凹部及び該凹部周辺から底面にかけて導出されたタング
ステン（賀）、モリブデン（Ｍｏ）等の高融点金属粉末
から成るメタライズ金属層を有する絶縁基体と、半導体
集積回路素子を外部回路に電気的に接続するための前記
メタライズ金属層に銀ロウ等のロウ材を介し取着された
銅（Ｃｕ）等から構成されており、絶縁基体と蓋体とか
ら成る多数の外部リードピンと蓋体とから成る絶縁容器
内部に半導体集積回路素子が収納され、気密封止されて
半導体装置となる。Conventionally, plug-in semiconductor device storage packages for storing semiconductor devices, particularly semiconductor integrated circuit devices, are generally made of electrically insulating materials such as alumina ceramics, and are generally made of electrically insulating materials such as alumina ceramics, in order to store the semiconductor integrated circuit devices approximately in the center of the top surface. An insulating substrate having a recess and a metallized metal layer made of high melting point metal powder such as tungsten or molybdenum (Mo) derived from the periphery of the recess to the bottom surface, and a semiconductor integrated circuit element are electrically connected to an external circuit. The insulator is made of copper (Cu) or the like attached to the metallized metal layer through a brazing material such as silver solder, and is composed of a large number of external lead pins and a cover, which are made up of an insulating base and a cover. A semiconductor integrated circuit element is housed inside the container and hermetically sealed to form a semiconductor device.
尚、この従来のプラグイン型半導体素子収納用パッケー
ジは外部リードピンと外部回路との電気的導通を良好と
するために、また外部リードピンが酸化腐蝕するのを防
止するために通常、前記外部リードピンの外表面にはニ
ッケル（Ｎｉ）、金（Ａｕ）等の良導電性で、耐蝕性に
優れた金属がメッキにより被着されている。In addition, in this conventional plug-in type semiconductor device storage package, in order to improve electrical continuity between the external lead pins and the external circuit, and to prevent the external lead pins from being oxidized and corroded, the external lead pins are usually The outer surface is plated with a metal such as nickel (Ni) or gold (Au) that has good conductivity and excellent corrosion resistance.
かかる従来のプラグイン型半導体素子収納用パッケージ
は通常、以下に述べる方法によって製作される。Such conventional plug-in type semiconductor device housing packages are usually manufactured by the method described below.
即ち、まず外表面にメタライズ金属層を有する絶縁基体
と柱状の外部リードピンとを準備する。That is, first, an insulating base having a metallized metal layer on its outer surface and columnar external lead pins are prepared.
前記メタライズ金属層を有する絶縁基体は高融点金属粉
末から成る金属ペーストをアルミナ（ａｔＺＯ３）の粉
末に適当な有機溶剤、溶媒を添加混合して得たグリーン
シート（生シート）上に印刷塗布し、これを還元雰囲気
中、約１６００℃の温度で焼成することによって形成さ
れる。The insulating substrate having the metallized metal layer is obtained by printing and applying a metal paste made of high melting point metal powder onto a green sheet (raw sheet) obtained by adding and mixing a suitable organic solvent and solvent to alumina (atZO3) powder, It is formed by firing this at a temperature of about 1600° C. in a reducing atmosphere.
また外部リードピンはコバール（Ｆｅ−Ｎｉ−Ｃｏ合金
）や４２Ａ１１ｏｙ（Ｆｅ−Ｎｉ合金）等から成り、伸
線により所定寸法径となした線を所定長さに切断するこ
とによって形成される。The external lead pin is made of Kovar (Fe-Ni-Co alloy) or 42A11oy (Fe-Ni alloy), and is formed by drawing a wire to a predetermined diameter and cutting it to a predetermined length.
前記外部リードピンはその自由端側（外部回路に設けた
ソケット等に挿入される側）の先端がバレル研磨等の機
械的研磨により面取りされており、外部リードピンを外
部回路に設けたソケット等に挿入接続させる際、その挿
入が容易となるよう形成されている。The tip of the external lead pin on its free end side (the side to be inserted into a socket etc. provided in an external circuit) is chamfered by mechanical polishing such as barrel polishing, and the external lead pin is inserted into a socket etc. provided in an external circuit. It is formed so that it can be easily inserted when connecting.
次に前記絶縁基体と外部リードピンを耐熱性に優れたカ
ーボンから成る治具内にセットし、絶縁基体に設けたメ
タライズ金属層上に銀ロウ等のロウ材を介して外部リー
ドピンを載置位置合わせするとともにこれを約９００℃
の温度に加熱し、ロウ材を熔融させることによってメタ
ライズ金属層上に外部リードピンをロウ付けする。Next, the insulating base and external lead pins are set in a jig made of carbon with excellent heat resistance, and the external lead pins are placed and aligned on the metallized metal layer provided on the insulating base via a brazing material such as silver solder. At the same time, heat this to about 900℃.
External lead pins are brazed onto the metallized metal layer by heating the metallized metal layer to a temperature of 100 to melt the brazing material.
そして最後に、前記ロウ付けされた外部リードピンの外
表面に電解メッキ法によりニッケル（Ｎｉ）、金（Ａｕ
）等から成る耐蝕性に優れた金属を層着させ、これによ
って製品としてのプラグイン型半導体素子収納用パッケ
ージが完成する。Finally, electrolytic plating is applied to the outer surface of the external lead pin that has been brazed with nickel (Ni) and gold (Au).
) is layered with a metal having excellent corrosion resistance, thereby completing a plug-in type semiconductor device storage package as a product.
しかし乍ら、この従来のプラグイン型半導体素子収納用
パッケージの製造方法によれば、外部リードピンはその
自由端側がバレル研磨等の機械的研磨により面取りされ
た後、すぐに絶縁基体に設けたメタライズ金属層にロウ
付は取着されることから以下に述べる欠点を有している
。However, according to this conventional manufacturing method of a plug-in type semiconductor device storage package, after the free end side of the external lead pin is chamfered by mechanical polishing such as barrel polishing, immediately after the external lead pin is chamfered by mechanical polishing such as barrel polishing, metallized Since brazing is attached to a metal layer, it has the following disadvantages.
■外部リードピンはバレル研磨を施した際、その外表面
に多量の砥粒がくい込んで付着しており、この外部リー
ドピンの外表面に耐蝕性金属から成る被覆層を層着させ
た場合、該被覆層は前記砥粒によって外部リードピンの
外表面全面に均一に層着することができず、そのため外
部リードピンの酸化腐蝕を完全に防止することができな
い。■When the external lead pin is barrel-polished, a large amount of abrasive grains are embedded and adhered to the outer surface of the external lead pin. The layer cannot be uniformly deposited on the entire outer surface of the external lead pin due to the abrasive grains, and therefore, oxidative corrosion of the external lead pin cannot be completely prevented.
■外部リードビンはバレル研磨を施した際、その外表面
に角張った凹部が多量に形成され、外部リードピンの外
表面に耐蝕性金属から成る被覆層を電解メッキ法により
層着させた場合、メッキの電流密度が前記角張った凹部
によってバラツキを生じ、外部リードピンの外表面全面
に被覆層を均一厚みに層着させることが不可となって被
覆層に密着不良を発生してしまう。■When the external lead pin is barrel-polished, a large number of angular recesses are formed on its outer surface. The current density varies due to the angular recesses, making it impossible to deposit the coating layer to a uniform thickness over the entire outer surface of the external lead pin, resulting in poor adhesion of the coating layer.
■外部リードピンはその外表面に多量の砥粒及び角張っ
た凹部が付着形成されていることから該外部リードピン
を絶縁基体に設けたメタライズ金属層にロウ付けするた
めにカーボンからなる治具内にセットした場合、砥粒及
び角張った凹部がカーボン治具を激しくけずり取って治
具の使用を短期間としてしまい、その結果、前記カーボ
ンから成る治具を使用して製作されるプラグイン型半導
体素子収納用パッケージを高価なものとしてしまう。■Since the external lead pin has a large amount of abrasive grains and angular recesses attached to its outer surface, it is set in a jig made of carbon in order to braze the external lead pin to the metallized metal layer provided on the insulating base. In such a case, the abrasive grains and the angular recesses will severely scrape off the carbon jig, reducing the use of the jig for a short period of time. This makes the packaging expensive.
■また前記０項においてけずり取られた治具の粉末（カ
ーボン粉末）は治具内にセットされている外部リードピ
ンの外表面に多量に付着することとなり、そのため外部
リードピンの外表面に耐蝕性金属から成る被覆層を層着
させた場合、該被覆層は前述の０項と同様、付着するカ
ーボン粉末によって層着に大きなムラが生じ、外部リー
ドピンの酸化腐蝕を完全に防止することができない等の
欠点を有している。■Also, a large amount of the jig powder (carbon powder) scraped off in item 0 above adheres to the outer surface of the external lead pin set in the jig, so the outer surface of the external lead pin is coated with corrosion-resistant metal. If a coating layer made of It has drawbacks.
〔発明の目的〕
本発明は上述の諸欠点に鑑み案出されたもので、その目
的は外部リードピンの外表面全面に耐蝕性に優れた金属
から成る被覆層を均一厚みで、かつ密着強度を大として
層着させることができるプラグイン型半導体素子収納用
パッケージの製造方法を提供することにある。[Object of the Invention] The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to provide a coating layer made of a metal with excellent corrosion resistance over the entire outer surface of an external lead pin with a uniform thickness and with high adhesion strength. It is an object of the present invention to provide a method for manufacturing a plug-in type semiconductor device housing package that can be layered as a large layer.
本発明のプラグイン型半導体素子収納用パッケージの製
造方法は、自由端側となる先端を機械的研磨により面取
り加工し、且つ外表面を化学的研磨により円滑となした
多数の外部リードピンを絶縁容器に設けたメタライズ金
属層にロウ材を介して取着し、しかる後、前記外部リー
ドピンの外表面を耐蝕性に優れた金属から成る被覆層で
被覆したことを特徴とするものである。The method for manufacturing a plug-in type semiconductor device housing package of the present invention is to attach a large number of external lead pins whose free ends are chamfered by mechanical polishing and whose outer surfaces are made smooth by chemical polishing to an insulating container. The external lead pin is attached to the metallized metal layer provided on the external lead pin via a brazing material, and then the outer surface of the external lead pin is covered with a coating layer made of a metal having excellent corrosion resistance.
次に、本発明を添付図面に基づき詳細に説明する。 Next, the present invention will be explained in detail based on the accompanying drawings.
第１図及び第２図は本発明の製造方法によって製作され
たプラグイン型半導体素子収納用パッケージの一実施例
を示し、１はアルミナセラミックス等の電気絶縁材料か
ら成る絶縁基体であり、２は同じく電気絶縁材料から成
る蓋体である。この絶縁基体１と蓋体２とで絶縁容器が
構成される。1 and 2 show an embodiment of a plug-in type semiconductor device storage package manufactured by the manufacturing method of the present invention, in which 1 is an insulating base made of an electrically insulating material such as alumina ceramics, and 2 is an insulating base made of an electrically insulating material such as alumina ceramics; The lid is also made of electrically insulating material. This insulating base 1 and lid 2 constitute an insulating container.
前記絶縁基体１にはその上面中央部に半導体集積回路素
子を収納するための凹部が設けてあり、凹部底面には半
導体集積回路素子３が接着材を介し取着される。The insulating substrate 1 has a recessed portion in the center of its upper surface for accommodating a semiconductor integrated circuit element, and a semiconductor integrated circuit element 3 is attached to the bottom surface of the recessed portion through an adhesive.
また前記絶縁基体１の凹部周辺部から底面にかけてメタ
ライズ金属層４が被着形成されており、メタライズ金属
Ｎ４の凹部周辺には半導体集積回路素子３の電極がワイ
ヤ５を介し電気的に接続され、また基体ｌ底面部には外
部リードピン６がロウ材７を介しロウ付けされる。Further, a metallized metal layer 4 is formed on the insulating substrate 1 from the periphery of the recess to the bottom surface, and the electrode of the semiconductor integrated circuit element 3 is electrically connected to the periphery of the recess of the metallized metal N4 via a wire 5. Further, an external lead pin 6 is soldered to the bottom surface of the base 1 via a brazing material 7.
前記絶縁基体１の底面に取着された外部リードピン６は
内部に収納される半導体集積回路素子３を外部回路と接
続する作用を為し、外部リードピン６を外部回路に設け
たソケット等に挿入接続することによって内部に収納さ
れる半導体集積回路素子３はメタライズ金属層４及び外
部リードピン６を介し外部回路と接続されることとなる
。The external lead pins 6 attached to the bottom surface of the insulating base 1 serve to connect the semiconductor integrated circuit element 3 housed inside to an external circuit, and the external lead pins 6 can be inserted into sockets etc. provided in the external circuit. As a result, the semiconductor integrated circuit element 3 housed inside is connected to an external circuit via the metallized metal layer 4 and the external lead pins 6.
尚、前記外部リードピン６の外表面には外部リードピン
６と外部回路との電気的接続を良好となすために、また
外部リードピン６が酸化腐蝕するのを防止するためにニ
ッケル（Ｎｉ）、金（Ａｕ）等の耐蝕性に優れた金属よ
り成る被覆層８が電解メッキ法もしくは無電解メッキ法
により層着されている。The outer surface of the external lead pin 6 is coated with nickel (Ni) and gold (nickel) in order to make a good electrical connection between the external lead pin 6 and the external circuit, and to prevent the external lead pin 6 from being oxidized and corroded. A coating layer 8 made of a metal with excellent corrosion resistance such as Au) is deposited by electrolytic plating or electroless plating.
かくして、このプラグイン型半導体素子収納用パッケー
ジによれば、絶縁基体ｌの凹部底面に半導体集積回路素
子３を取着固定するとともに該半導体集積回路素子３の
各電極をワイヤ５によりメタライズ金属層４に接続させ
た後、絶縁基体１と蓋体２とをガラス、樹脂等の封止部
材で取着させることによりその内部に半導体集積回路素
子３を気密に封止し、半導体装置となる。Thus, according to this plug-in type semiconductor device storage package, the semiconductor integrated circuit device 3 is attached and fixed to the bottom surface of the recess of the insulating substrate l, and each electrode of the semiconductor integrated circuit device 3 is connected to the metallized metal layer 4 by the wire 5. After connecting the insulating substrate 1 and the lid 2 with a sealing member such as glass or resin, the semiconductor integrated circuit element 3 is hermetically sealed therein, thereby forming a semiconductor device.
次に、本発明のプラグイン型半導体素子収納用パッケー
ジの製造方法について説明する。Next, a method of manufacturing a plug-in type semiconductor device storage package according to the present invention will be explained.
まず、メタライズ金属層４を有する絶縁基体１と蓋体２
と外部リードピン６を準備する。First, an insulating base 1 having a metallized metal layer 4 and a lid 2
and prepare the external lead pin 6.
前記メタライズ金属層４を有する絶縁基体１は表面及び
貫通孔内に金属ペーストを印刷塗布した未焼成セラミツ
クシート（グリーンシート）を複数枚積層するとともに
還元雰囲気中（Ｈ□−Ｎ２ガス中）約１４００〜１６０
０℃の高温で焼成することによって形成される。The insulating substrate 1 having the metallized metal layer 4 is made by laminating a plurality of unfired ceramic sheets (green sheets) each having a metal paste printed on the surface and inside the through-holes, and heated in a reducing atmosphere (in H□-N2 gas) at a temperature of about 1,400 yen. ~160
It is formed by firing at a high temperature of 0°C.
尚、前記未焼成セラミツクシートはアルミナ（＾１！０
３） 、シリカ（ＳｔＯｔ）等のセラミック原料粉末に
適当な溶剤、溶媒を添加混合して泥漿物を作り、これを
従来周知のドクターブレード法によりシート状となすこ
とによって形成され、また金属ペーストはタングステン
（Ｗ） 、モリブデン（Ｍｏ） 、マンガン（Ｍｎ）等
の高融点金属粉末に適当な溶剤、溶媒を添加混合するこ
とによって作成され、未焼成セラミツクシートの表面及
び貫通孔内に従来周知のスクリーン印刷等の厚膜手法に
よって印刷塗布される。Note that the unfired ceramic sheet is made of alumina (^1!0
3) It is formed by adding and mixing an appropriate solvent to ceramic raw material powder such as silica (StOt) to create a slurry, and forming this into a sheet shape using the conventionally well-known doctor blade method. It is created by adding and mixing an appropriate solvent to high melting point metal powder such as tungsten (W), molybdenum (Mo), manganese (Mn), etc., and is installed on the surface of an unfired ceramic sheet and in the through holes using a well-known screen. Printing is applied by thick film techniques such as printing.
また蓋体２は絶縁基体ｌと同様、セラミックスから成り
、例えばセラミックスの粉末を従来周知のプレス成形法
を採用することによって絶縁基体ｌの半導体集積回路素
子が収納される凹部を塞ぐ大きさの板状に成形するとと
もにこれを高温で焼成することによって形成される。Similarly to the insulating base l, the lid body 2 is made of ceramics, for example, a plate having a size that closes the recessed portion of the insulating base l in which the semiconductor integrated circuit element is housed, by employing a conventionally well-known press molding method using ceramic powder. It is formed by molding it into a shape and firing it at a high temperature.
更に前記外部リードピン６はコバール（Ｆｅ−Ｎｉ−Ｃ
。Further, the external lead pin 6 is made of Kovar (Fe-Ni-C).
.
合金）や４２Ａ１１ｏｙ（Ｆｅ−Ｎｉ合金）等の金属か
ら成り、従来周知の金属加工法により円柱状に形成され
る。42A11oy (Fe-Ni alloy), and is formed into a cylindrical shape by a conventionally known metal processing method.
次に、前記外部リードピン６の自由端側（外部回路に設
けたソケット等に挿入される側）の先端をバレル研磨に
より、例えば寸法が０．１５ｍａｉの円弧となるように
研磨面取りし、外部リードピン６を外部回路に設けたソ
ケット等に挿入接続させる際、その挿入が容易となるよ
うに加工する。Next, the tip of the free end side of the external lead pin 6 (the side to be inserted into a socket etc. provided in an external circuit) is polished and chamfered by barrel polishing so as to have a circular arc size of, for example, 0.15 mai, and the external lead pin 6 is processed so that it can be easily inserted into a socket or the like provided in an external circuit.
尚、前記外部リードピン６のバレル研磨としては従来一
般に使用されている回転式バレル研磨装置が用いられ、
例えば回転容器内に直径３．０〜５゜０ｍｍφのアルミ
ナ（Ａｌｘ（ｈ）系ボールから成るメディアと一端が樹
脂等で被覆された円柱状のピンを投入するとともにこれ
らを約４時間回転衝突させることによって行われる。Incidentally, for the barrel polishing of the external lead pin 6, a conventionally commonly used rotary barrel polishing device is used.
For example, a media consisting of alumina (Alx(h) balls with a diameter of 3.0 to 5°0 mmφ and a cylindrical pin whose one end is coated with resin etc. are placed in a rotating container, and these are rotated and collided for about 4 hours. It is done by
そして次に前記バレル研磨がほどこされた外部リードピ
ン６を化学的研磨し、その外表面が円滑となるように加
工する。Next, the external lead pin 6 that has been subjected to the barrel polishing is chemically polished so that its outer surface becomes smooth.
前記外部リードピン６の化学的研磨としては、外部リー
ドピン６を塩酸、硫酸、硝酸もしくはこれらの混酸等か
ら成る溶液中、具体的には塩酸：硫酸：水を容量で２：
１：１の比率となした溶液中に約１分間、浸漬すること
によって行われ、外部リードピン６の外表面の一部を腐
蝕除去することによって表面を円滑となす、この場合、
外部リードピン６はその外表面の一部が化学的研磨によ
り腐蝕除去されることから前工程のバレル研磨の際に外
部リードピン６の外表面に形成される角張った凹部は完
全に除去されるか、もしくは角部が丸みを帯びた凹部と
なすことができるとともに外部リードピン６の外表面に
くい込んで付着している砥粒を完全に脱落除去すること
が可能となる。For chemical polishing of the external lead pin 6, the external lead pin 6 is polished in a solution consisting of hydrochloric acid, sulfuric acid, nitric acid, or a mixed acid thereof, specifically, hydrochloric acid: sulfuric acid: water in a volume of 2:2.
This is done by immersing the external lead pin 6 in a solution with a ratio of 1:1 for about 1 minute, and the surface is made smooth by corroding a part of the external surface of the external lead pin 6. In this case,
Since a part of the outer surface of the external lead pin 6 is corroded and removed by chemical polishing, the angular recesses formed on the outer surface of the external lead pin 6 during the barrel polishing in the previous process are completely removed. Alternatively, it is possible to form a concave portion with rounded corners, and it is also possible to completely remove the abrasive grains embedded in and attached to the outer surface of the external lead pin 6.
そのため後述する外部リードピン６の外表面に耐蝕性に
優れた金属から成る被覆層８を電解メッキ法や無電解メ
ッキ法により層着させた場合、被覆層８はその層着にム
ラ等を生じることは一切なく、外部リードピン６の外表
面全面に均一厚みの被覆層８を層着させることができる
。Therefore, when a coating layer 8 made of a highly corrosion-resistant metal is deposited on the outer surface of the external lead pin 6 (described later) by electrolytic plating or electroless plating, the coating layer 8 may have uneven adhesion. The coating layer 8 having a uniform thickness can be deposited on the entire outer surface of the external lead pin 6 without any layer.
そして次に前記メタライズ金属Ｎ４を有する絶縁基体ｌ
と外部リードピン６をカーボンから成る治具（不図示）
内にセットし、絶縁基体１に設けたメタライズ金属層４
の露出部分に外部リードピン６の一端を銀ロウ等のロウ
材７を介し載置されるように位置合わせを行う、この場
合、外部り一ドピン６はその外表面に角張った凹部や砥
粒の付着が皆無であることから該凹部や付着砥粒による
治具のけずりが一切なく、けずり取られた治具の粉末（
カーボン粉末）が外部リードピン６の外表面に付着する
こともない。したがって、後述する外部リードピン６の
外表面に耐蝕性に優れた金属から成る被覆ＪＷ８を層着
させた場合、その層着にムラを生じることは一切なく、
同時に治具を長期間にわたり使用することが可能となり
、該治具を使用して製作されるプラグイン型半導体素子
収納用パッケージを安価となすこともできる。Then, the insulating base l having the metallized metal N4
and the external lead pin 6 using a jig made of carbon (not shown).
a metallized metal layer 4 set within and provided on the insulating substrate 1;
Position the external lead pin 6 so that it is placed on the exposed part of the external lead pin 6 through a brazing material 7 such as silver solder. Since there is no adhesion, there is no scratching of the jig due to the recesses or attached abrasive particles, and the jig powder (
Carbon powder) does not adhere to the outer surface of the external lead pin 6. Therefore, when the coating JW8 made of a metal with excellent corrosion resistance is layered on the outer surface of the external lead pin 6, which will be described later, there will be no unevenness in the layering.
At the same time, the jig can be used for a long period of time, and a plug-in type semiconductor element storage package manufactured using the jig can be manufactured at low cost.
かかる位置合わせされた絶縁基体ｌ及び外部リードピン
６は次に、約９００℃の温度に加熱された炉中に通され
、ロウ材７を加熱熔融させることによって外部リードピ
ン６をメタライズ金属層４にロウ付けする。The insulating base l and the external lead pins 6 thus aligned are then passed through a furnace heated to a temperature of about 900° C., and the external lead pins 6 are soldered to the metallized metal layer 4 by heating and melting the brazing material 7. Attach.
そして最後にメタライズ金属層４にロウ付けされた外部
リードピン６の外表面に電解メッキ法や無電解メッキ法
等によりニッケル（Ｎｉ）や金（Ａｕ）等の耐蝕性に優
れた金属から成る被覆層８を層着させ、これによって製
品としてのプラグイン型半導体素子収納用パッケージが
完成する。Finally, on the outer surface of the external lead pin 6 brazed to the metallized metal layer 4, a coating layer made of a highly corrosion-resistant metal such as nickel (Ni) or gold (Au) is formed by electrolytic plating or electroless plating. 8 is layered, thereby completing a plug-in type semiconductor device storage package as a product.
前記被覆Ｎ８は、例えばニッケルを電解メッキ法により
層着させて形成する場合、外部リードピン６がロウ付け
された絶縁基体１を硫酸ニッケル１８０〜３００ｇ／
ｌ、塩化−’−７ケＪＬ７３０〜６０ｇ／ ｌ 、ホウ
素２０〜６０ｇ／ ｌから成るニッケルメッキ浴中に浸
漬するとともに外部リードピン６に電流密度が２〜４Ａ
／ｄｓ”となるような電界を約３分間印加することによ
って形成される。When the coating N8 is formed by layering nickel by electrolytic plating, for example, the insulating base 1 to which the external lead pins 6 are brazed is coated with 180 to 300 g of nickel sulfate.
l, chloride-'-7ke JL730~60g/l, and immersed in a nickel plating bath consisting of boron 20~60g/l while applying a current density of 2~4A to the external lead pin 6.
/ds'' for about 3 minutes.
なお、この場合、被ｉ層８は外部リードピン６の外表面
に角張った凹部や砥粒等の付着形成が皆無であることか
ら外部リードピン６の外表面全面にわたって均一厚みに
密着強度を大として、層着することが可能となる。In this case, since the i-layer 8 has no angular recesses or adhesion of abrasive grains on the outer surface of the external lead pin 6, the i-layer 8 has a uniform thickness over the entire outer surface of the external lead pin 6 and has a high adhesion strength. It becomes possible to layer it.
〔発明の効果〕
かくして、本発明のプラグイン型半導体素子収納用パッ
ケージの製造方法によれば、外部リードピンの自由端側
（外部回路に設けたソケット等に挿入される側）の先端
をバレル研磨等の機械的研磨により面取り加工をした後
、化学的研磨により外部リードピンの外表面の一部を腐
蝕除去したことからバレル研磨の際に外部リードピンの
外表面に形成される角張った凹部は完全に除去されるか
、もしくは角部が丸味をおびた凹部となすことができ、
また外部リードピンの外表面にくい込んで付着している
砥粒も完全に脱落除去することができる。そのため外部
リードピンの外表面に耐蝕性に優れた金属から成る被覆
層を層着させた場合、該被覆層は外部リードピンの外表
面全面にわたり均一厚みに、密着強度を大として層着す
ることが可能となり、外部リードピンの酸化腐蝕を皆無
として信軌性が極めて高いプラグイン型半導体素子収納
用パッケージを提供することができる。[Effects of the Invention] Thus, according to the method of manufacturing a plug-in type semiconductor device storage package of the present invention, the tips of the free ends of the external lead pins (the sides to be inserted into sockets etc. provided in the external circuit) are barrel-polished. After chamfering by mechanical polishing, etc., a part of the outer surface of the external lead pin was corroded and removed by chemical polishing, so the angular recesses formed on the outer surface of the external lead pin during barrel polishing were completely removed. It can be removed or the corners can be made into rounded recesses,
Furthermore, the abrasive grains embedded in and attached to the outer surface of the external lead pin can be completely removed. Therefore, when a coating layer made of a metal with excellent corrosion resistance is deposited on the outer surface of the external lead pin, the coating layer can be deposited with a uniform thickness and high adhesion strength over the entire outer surface of the external lead pin. Therefore, it is possible to provide a plug-in type semiconductor element storage package that has extremely high reliability with no oxidation corrosion of external lead pins.
また外部リードピンの外表面が円滑であることから該外
部リードピンを絶縁基体に設けたメタライズ金属層にロ
ウ付けする場合、外部リードピンがカーボン治具をけず
り取ることが少なく、そのためカーボン治具の長期間の
使用が可能となって該カーボン治具を使用して製作され
るプラグイン型半導体素子収納用パッケージを安価とな
すことができる。In addition, since the outer surface of the external lead pin is smooth, when the external lead pin is brazed to the metallized metal layer provided on the insulating substrate, the external lead pin is less likely to scratch the carbon jig, and therefore the carbon jig will last for a long time. This makes it possible to use the carbon jig, thereby making it possible to manufacture a plug-in type semiconductor device housing package at low cost using the carbon jig.
第１図は本発明の製造方法によって製作されたプラグイ
ン型半導体素子収納用パッケージの一実施例を示す断面
図、第２図は第１図の外部リードピンのロウ付は部の部
分拡大断面図である。
１：絶縁基体 ２：蓋体
４：メタライズ金属層 ６：外部リードピン７：ロウ
材 ８：被覆層FIG. 1 is a sectional view showing an embodiment of a plug-in type semiconductor device storage package manufactured by the manufacturing method of the present invention, and FIG. 2 is a partially enlarged sectional view of the soldered portion of the external lead pin in FIG. 1. It is. 1: Insulating base 2: Lid 4: Metallized metal layer 6: External lead pin 7: Brazing material 8: Covering layer
Claims (1)
つ外表面を化学的研磨により円滑となした多数の外部リ
ードピンを絶縁容器に設けたメタライズ金属層にロウ材
を介して取着し、しかる後、前記外部リードピンの外表
面を耐蝕性に優れた金属から成る被覆層で被覆したこと
を特徴とするプラグイン型半導体素子収納用パッケージ
の製造方法。A large number of external lead pins, the free ends of which are chamfered by mechanical polishing and whose outer surfaces are made smooth by chemical polishing, are attached to the metallized metal layer provided in the insulating container via brazing material, and then A method for manufacturing a plug-in type semiconductor device housing package, characterized in that the outer surface of the external lead pin is coated with a coating layer made of a metal having excellent corrosion resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62106757A JP2554879B2 (en) | 1987-04-30 | 1987-04-30 | Manufacturing method of package for storing plug-in type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62106757A JP2554879B2 (en) | 1987-04-30 | 1987-04-30 | Manufacturing method of package for storing plug-in type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63272061A true JPS63272061A (en) | 1988-11-09 |
| JP2554879B2 JP2554879B2 (en) | 1996-11-20 |
Family
ID=14441785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62106757A Expired - Lifetime JP2554879B2 (en) | 1987-04-30 | 1987-04-30 | Manufacturing method of package for storing plug-in type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2554879B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6555757B2 (en) | 2000-04-10 | 2003-04-29 | Ngk Spark Plug Co., Ltd. | Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions |
| US6648211B2 (en) | 2000-10-13 | 2003-11-18 | Ngk Spark Plug Co., Ltd. | Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin |
| US6660946B2 (en) | 2000-04-10 | 2003-12-09 | Ngk Spark Plug Co., Ltd. | Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin |
| US6960729B2 (en) | 2001-07-27 | 2005-11-01 | Ngk Spark Plug Co., Ltd. | Upright-pin-joined resin substrate, method of producing the substrate, pins, and method of producing the pins |
| US7060534B2 (en) | 2003-01-16 | 2006-06-13 | Infineon Technologies Ag | Housing for semiconductor devices, semiconductor device pin, and method for the manufacturing of pins |
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| JPS5534485A (en) * | 1978-09-01 | 1980-03-11 | Mitsubishi Electric Corp | Manufacture of resin sealed type semiconductor |
| JPS59155950A (en) * | 1983-02-25 | 1984-09-05 | Shinko Electric Ind Co Ltd | Low melting-point glass seal type ceramic package for semiconductor device |
| JPS59211253A (en) * | 1983-05-17 | 1984-11-30 | Matsushita Electronics Corp | Electronic part package |
| JPS59225585A (en) * | 1983-06-07 | 1984-12-18 | 日本電気株式会社 | Method of machining pin of circuit board |
| JPS605546A (en) * | 1983-06-23 | 1985-01-12 | Shinko Electric Ind Co Ltd | Manufacture of ceramic package |
| JPS6010762A (en) * | 1983-06-30 | 1985-01-19 | Sumitomo Special Metals Co Ltd | Composite pin |
| JPS60146671A (en) * | 1984-01-09 | 1985-08-02 | Tipton Mfg Corp | Barrel polishing method using jointly chemicals of nature to dissolve work |
| JPS61203563U (en) * | 1985-06-10 | 1986-12-22 | ||
| JPS6265845U (en) * | 1985-10-14 | 1987-04-23 | ||
| JPS63115353A (en) * | 1986-10-31 | 1988-05-19 | Sumitomo Special Metals Co Ltd | Manufacture of ag soldered clad lead pin |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6555757B2 (en) | 2000-04-10 | 2003-04-29 | Ngk Spark Plug Co., Ltd. | Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions |
| US6660946B2 (en) | 2000-04-10 | 2003-12-09 | Ngk Spark Plug Co., Ltd. | Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin |
| US6648211B2 (en) | 2000-10-13 | 2003-11-18 | Ngk Spark Plug Co., Ltd. | Pin standing resin-made substrate, method of making pin standing resin-made substrate, pin and method of making pin |
| US6960729B2 (en) | 2001-07-27 | 2005-11-01 | Ngk Spark Plug Co., Ltd. | Upright-pin-joined resin substrate, method of producing the substrate, pins, and method of producing the pins |
| US7060534B2 (en) | 2003-01-16 | 2006-06-13 | Infineon Technologies Ag | Housing for semiconductor devices, semiconductor device pin, and method for the manufacturing of pins |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2554879B2 (en) | 1996-11-20 |
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