JPS6325947A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6325947A JPS6325947A JP61169245A JP16924586A JPS6325947A JP S6325947 A JPS6325947 A JP S6325947A JP 61169245 A JP61169245 A JP 61169245A JP 16924586 A JP16924586 A JP 16924586A JP S6325947 A JPS6325947 A JP S6325947A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- silicon layer
- groove
- substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 32
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 239000013078 crystal Substances 0.000 abstract description 9
- 230000007547 defect Effects 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 33
- 229910052814 silicon oxide Inorganic materials 0.000 description 33
- 229910052581 Si3N4 Inorganic materials 0.000 description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 25
- 238000002955 isolation Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000001020 plasma etching Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は半導体装置の製造方法に係り、特に素子の分
離方法を改良した半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which an element isolation method is improved.
（従来の技術）
半導体集積回路では同一半導体基板上にトランジスタ、
ダイオード、抵抗など種々の素子が形成されており、そ
れぞれの素子の分離が不可欠である。このような素子分
離は従来では、ＰＮ接合による分離や膜厚の厚い熱酸化
膜による選択酸化分離が用いられていた。しかし、分離
領域を縮小し、併せて奇生客員を減少させるため、近年
では基板内に溝を形成し、この溝内に絶縁膜を介して多
結晶シリコン層を埋め込むことにより素子分離を行なう
方式が用いられるようになってきた。一般にこのような
素子分離技術をトレンチアイソレーション方式と称して
いる。(Conventional technology) In semiconductor integrated circuits, transistors and
Various elements such as diodes and resistors are formed, and it is essential to separate each element. Conventionally, for such element isolation, isolation using a PN junction or selective oxidation isolation using a thick thermal oxide film has been used. However, in order to reduce the isolation area and reduce the number of random visitors, in recent years a method has been developed in which elements are isolated by forming a groove in the substrate and burying a polycrystalline silicon layer in this groove via an insulating film. has come to be used. Generally, such element isolation technology is called a trench isolation method.
第３図は従来のトレンチアイソレーション方式を用いた
半導体装置の製造方法による工程を順次示す断面図であ
る。FIG. 3 is a cross-sectional view sequentially showing steps in a method of manufacturing a semiconductor device using a conventional trench isolation method.
まず、シリコン半導体基板３１の表面を酸化して酸化膜
３２を形成した後、その上にシリコン窒化膜３３を、さ
らに基板３１をエツチングする際のマスク材料となるＣ
ＶＤ法（化学的気相成長法）によるシリコン酸化膜３４
を順次堆積し、この上にフォトレジストｖＡ３５を塗布
形成する。しかる後、フォトレジスト膜３５の露光及び
現像を行なって不要部分を除去してパターニングを行な
う （第３図（ａ））。First, the surface of a silicon semiconductor substrate 31 is oxidized to form an oxide film 32, and then a silicon nitride film 33 is deposited thereon.
Silicon oxide film 34 by VD method (chemical vapor deposition method)
are sequentially deposited, and a photoresist vA35 is applied thereon. Thereafter, the photoresist film 35 is exposed and developed to remove unnecessary portions and patterned (FIG. 3(a)).
続いて上記レジスト１Ｉ３５をエツチング用のマスクと
して、上記シリコン酸化膜３４、シリコン窒化１１３３
及び酸化１１３２を順次選択的にエツチングし、その後
、レジスト膜３５も除去する。次に上記シリコン酸化Ｄ
Ｉ３４をエツチング用のマスクとし、ＲＩＥ（反応性イ
オンエツチング）を用いた異方性エツチング技術により
基板３１を選択的にエツチングして満３６を形成する。Next, using the resist 1I35 as an etching mask, the silicon oxide film 34 and silicon nitride 1133 are etched.
Then, the resist film 35 is also removed. Next, the silicon oxide D
Using I34 as an etching mask, the substrate 31 is selectively etched by an anisotropic etching technique using RIE (reactive ion etching) to form a filler layer 36.
この後、マスクとして用いた上記シリコン酸化１Ｉ３４
を除去し、次いで満３６の内周面にシリコン酸化膜３７
を形成した後、溝３６の幅の２倍程度の厚さの多結晶シ
リコン１ｉ１３８を成長させる（第３図（ｂ））。After this, the above silicon oxide 1I34 used as a mask
is removed, and then a silicon oxide film 37 is formed on the inner circumferential surface of the full 36
After forming, polycrystalline silicon 1i 138 is grown to a thickness about twice the width of the groove 36 (FIG. 3(b)).
次に上記多結晶シリコン届３８をエツチングしていき、
シリコン窒化１Ｉ３３の表面が露出した時点でエツチン
グを止め、これにより満３６の内部にのみ多結晶シリコ
ン層３８を残す（第３図（Ｃ））。Next, etching the polycrystalline silicon report 38,
Etching is stopped when the surface of the silicon nitride 1I 33 is exposed, thereby leaving the polycrystalline silicon layer 38 only inside the silicon nitride 36 (FIG. 3(C)).
次にシリコン窒化１１３３を耐酸化マスクとして、溝１
６の内部に残されている多結晶シリコン！Ｉ３８の表面
を酸化し、そこに厚いＩｌ厚のフィールド酸化！！３９
を形成する（第３図（ｄ））。この後は、上記溝３６の
部分以外のところに素子を形成する。Next, using silicon nitride 1133 as an oxidation-resistant mask, groove 1
Polycrystalline silicon left inside 6! Oxidize the surface of I38 and apply thick Il field oxidation there! ! 39
(Fig. 3(d)). After this, elements are formed in areas other than the groove 36.
ところで、このような分離方法では次のような問題点が
ある。However, such a separation method has the following problems.
■ 溝３６を埋めるために多結晶シリコンＩ！１３８の
膜厚を厚くしなければならず、この多結晶シリコンＷＡ
Ｇ８の成長及びエツチングに長い時間が必要である。■ Polycrystalline silicon I to fill the groove 36! The film thickness of 138 must be increased, and this polycrystalline silicon WA
G8 growth and etching require a long time.
■ 多結晶シリコン層３８をエツチングする際の制御が
雌しく、溝３６のところで段差を生じ易い。(2) The etching of the polycrystalline silicon layer 38 is poorly controlled, and steps are likely to occur at the grooves 36.
例えば、上記■の問題については、溝３６の幅を１．５
μｍにすると、多結晶シリコン層３８の厚さは３μｍ程
度必要となるが、膜厚のばらつきとエツチングのばらつ
きとにより、１μｍ以上もの段差が生じる可能性がある
。For example, for the above problem (■), the width of the groove 36 is set to 1.5.
In the case of .mu.m, the thickness of the polycrystalline silicon layer 38 is required to be about 3 .mu.m, but due to variations in film thickness and variations in etching, a step difference of 1 .mu.m or more may occur.
このような問題を解決するために、特開昭５７−６０８
５１号公報に記載されている発明では、溝の上部で溝の
傾きを緩くすることにより段差が急峻になるのを防止し
ている。しかし、この方法では分離領域が溝の幅よりも
広がってしまい、分ＩＩＩの縮小には限界がある。In order to solve such problems, Japanese Patent Application Laid-Open No. 57-608
In the invention described in Japanese Patent No. 51, the slope of the groove is made gentler at the upper part of the groove, thereby preventing the step from becoming steep. However, in this method, the isolation region becomes wider than the width of the trench, and there is a limit to the reduction of the amount of the isolation region.
また、配線容量を減少させたり、集積回路の信頼性を上
げるためには、素子部以外のフィールド領域などの酸化
膜を厚く形成する必要がある。ところが、フィールド酸
化膜をシリコン基板の酸化により形成すると、溝の近傍
で結晶欠陥が生じ易いことが報告されている。第３図に
示す従来方法では、第３図（ｄ）の工程で満３６の内部
に残されている多結晶シリコン層３８の表面を酸化して
厚い膜厚のシリコン酸化膜３９を形成する際に、溝３６
の周囲付近の基板３１も同時に酸化されるため、基板３
１のこの部分に結晶欠陥が生じ易いという問題がある。Furthermore, in order to reduce the wiring capacitance and increase the reliability of the integrated circuit, it is necessary to form a thick oxide film in field regions other than the element portion. However, it has been reported that when a field oxide film is formed by oxidizing a silicon substrate, crystal defects are likely to occur near the grooves. In the conventional method shown in FIG. 3, when the surface of the polycrystalline silicon layer 38 remaining inside the polycrystalline silicon layer 38 is oxidized to form a thick silicon oxide film 39 in the step shown in FIG. groove 36
Since the substrate 31 near the periphery of the substrate 3 is also oxidized at the same time, the substrate 3
There is a problem in that crystal defects are likely to occur in this part of 1.
（発明が解決しようとする問題点）
このように従来の方法では、多結晶シリコン層の成長及
びエツチングに長い時間が必要となり、かつ表面に段差
が生じ易く、また基板に結晶欠陥が生じ易いという欠点
がある。(Problems to be Solved by the Invention) As described above, in the conventional method, a long time is required for growing and etching the polycrystalline silicon layer, steps are likely to occur on the surface, and crystal defects are likely to occur in the substrate. There are drawbacks.
この発明は上記のような事情を考慮してなされたもので
あり、その目的は多結晶シリコン層の成長及びエツチン
グを短時間で行なうことができ、また表面に段差が発生
せず、かつ基板に結晶欠陥が発生しない半導体装置の製
造方法を提供することにある。This invention was made in consideration of the above-mentioned circumstances, and its purpose is to be able to grow and etch a polycrystalline silicon layer in a short period of time, to prevent the formation of steps on the surface, and to form a substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device in which crystal defects do not occur.
［発明の構成］
（問題点を解決するための手段）
この発明の半導体装置の製造方法は、半導体基体に溝部
を形成する工程と、上記溝部の内周面及び上記基体の表
面を連続して第１の絶縁膜で被覆する工程と、上記溝部
が埋まらない程度に上記第１の絶縁膜上に第１の多結晶
シリコン層を堆積する工程と、上記第１の多結晶シリコ
ン層を第２の絶縁膜で被覆する工程と、上記溝部が埋ま
るように上記第２の絶ａｍ上に第２の多結晶シリコン層
を堆積する工程と、上記第２の多結晶シリコン層をエツ
チングしてこの第２の多結晶シリコン層を上記溝部内に
のみ残す工程と、上記基体表面上の第１の多結晶シリコ
ン層を少なくとも上記溝部の位置付近に残す工程と、上
記工程で残された第１の多結晶シリコン１層を酸化する
工程とから構成されている。[Structure of the Invention] (Means for Solving the Problems) A method for manufacturing a semiconductor device of the present invention includes a step of forming a groove in a semiconductor substrate, and a step of continuously forming an inner circumferential surface of the groove and a surface of the substrate. a step of depositing a first polycrystalline silicon layer on the first insulating film to such an extent that the trench is not filled; a step of depositing a second polycrystalline silicon layer on the second layer so as to fill the groove portion; and a step of etching the second polycrystalline silicon layer to form a second layer of polycrystalline silicon. a step of leaving the second polycrystalline silicon layer only in the groove, a step of leaving the first polycrystalline silicon layer on the surface of the substrate at least near the position of the groove, and a step of leaving the first polycrystalline silicon layer on the surface of the substrate at least near the position of the groove; The process consists of a step of oxidizing one layer of crystalline silicon.
（作用）
この発明の半導体装置の製造方法では、半導体基体に形
成した溝部の内周面及び基体の表面を連続して第１の絶
縁膜で被覆し、この上に溝部が埋まらない程度に第１の
多結晶シリコン層を堆積し、さらにこの上を第２の絶縁
膜で被覆し、次にこの上に溝部が埋まるように第２の多
結晶シリコン層をＪ［する。そして、上記第２の多結晶
シリコン層をエツチングしてこの第２の多結晶シリコン
層を上記溝部内にのみ残すようにしている。さらに第１
の多結晶シリコン層を少なくとも上記溝部の位置付近に
残した後にこの第１の多結晶シリコン層を酸化してフィ
ールド酸化膜を形成するようにしている。(Function) In the method for manufacturing a semiconductor device of the present invention, the inner circumferential surface of the groove formed in the semiconductor substrate and the surface of the substrate are continuously covered with the first insulating film, and the first insulating film is coated on the first insulating film to the extent that the groove is not buried. A first polycrystalline silicon layer is deposited, this is further covered with a second insulating film, and then a second polycrystalline silicon layer is deposited on top of this so as to fill the trench. Then, the second polycrystalline silicon layer is etched so that the second polycrystalline silicon layer remains only in the groove. Furthermore, the first
After leaving the first polycrystalline silicon layer at least near the position of the trench, the first polycrystalline silicon layer is oxidized to form a field oxide film.
これにより、この第２の多結晶シリコン層の堆積は最初
の溝部の幅よりも狭い幅を埋めることになるので短時間
で埋めることができ、かつエツチングに必要な時間も短
くすることができる。また、第２の多結晶シリコン層の
エツチングの際に、基体の平坦面上に位置している第２
の絶縁膜の表面が露出した時点でエツチングを止めれば
よいため、エツチングの制御性が容易である。As a result, the second polycrystalline silicon layer is deposited to fill a width narrower than the width of the first trench, so it can be filled in a short time, and the time required for etching can also be shortened. Also, when etching the second polycrystalline silicon layer, a second polycrystalline silicon layer located on the flat surface of the substrate is etched.
Etching can be easily controlled because it is sufficient to stop etching when the surface of the insulating film is exposed.
さらに、残された第１の多結晶シリコン層を酸化してフ
ィールド酸化膜を形成するようにしており、溝部付近の
基体を酸化することなしにフィールド酸化膜を形成する
ことができるため、結晶欠陥の発生が押さえられる。Furthermore, the remaining first polycrystalline silicon layer is oxidized to form a field oxide film, and since the field oxide film can be formed without oxidizing the substrate near the groove, crystal defects can be avoided. The occurrence of this can be suppressed.
（実施例） 以下、図面を参照してこの発明の一実施例を説明する。(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図はこの発明に係る半導体装置の製造方法の一実施
例による主要な製造工程を順次示す断面図である。FIG. 1 is a cross-sectional view sequentially showing the main manufacturing steps according to an embodiment of the method for manufacturing a semiconductor device according to the present invention.
まず、シリコン半導体基板１１の表面を熱酸化法、もし
くはＣＶＤ法によりシリコン酸化！１ｉ１２を形成し、
その上にシリコン窒化膜１３を減圧ＣＶＤ法などの方法
で堆積する。次に、上記シリコン窒化膜１３上に、基板
１１を選択エツチングする際のマスク材料となるシリコ
ン酸化１１４をＣＶＤ法により堆積する。さらに、この
シリコン酸化膜１４上にフォトレジスト膜１５を塗布形
成する。しかる後、フォトレジスト膜１５の露光及び現
象を行ない不要部分を除去してバターニングを行なう
（第１図（ａ））。First, the surface of the silicon semiconductor substrate 11 is oxidized to silicon by thermal oxidation method or CVD method! form 1i12,
A silicon nitride film 13 is deposited thereon by a method such as a low pressure CVD method. Next, silicon oxide 114 is deposited on the silicon nitride film 13 by the CVD method to serve as a mask material when selectively etching the substrate 11. Furthermore, a photoresist film 15 is coated and formed on this silicon oxide film 14. After that, the photoresist film 15 is exposed and developed to remove unnecessary parts and patterning is performed.
(Figure 1(a)).
続いて上記レジスト１１１５をエツチング用のマスクと
して、ＣＦ４などのガスを用いた異方性ドライエツチン
グ（例えばＲＩＥ、すなわち反応性イオンエツチング）
により上記シリコン酸化ｖＡ１４、シリコン窒化膜１３
及びシリコン酸化１１１２を順次、選択的にエツチング
し、その後、レジスト膜１５を酸素プラズマ中で燃焼す
るか、ｌｉＩ！酸系水溶液で処理することにより剥離す
る。次にシリコン酸化膜１４をエツチング用のマスクと
し、ＲＩＥ（反応性イオンエツチング）を用いた異方性
エツチング技術により基板１１を選択的にエツチングし
て溝１６を形成する。このとき、異方性エツチング技術
の持つ特性により、溝１６の両面が基板１１の平坦面に
対して垂直もしくは略垂直となるように形成される。Next, using the resist 1115 as an etching mask, anisotropic dry etching (for example, RIE, ie, reactive ion etching) is performed using a gas such as CF4.
The above silicon oxide vA14, silicon nitride film 13
and silicon oxide 1112 are sequentially selectively etched, and then the resist film 15 is burned in oxygen plasma or liI! Peel off by treatment with acidic aqueous solution. Next, using the silicon oxide film 14 as an etching mask, the substrate 11 is selectively etched by an anisotropic etching technique using RIE (reactive ion etching) to form grooves 16. At this time, due to the characteristics of the anisotropic etching technique, both surfaces of the groove 16 are formed perpendicularly or substantially perpendicularly to the flat surface of the substrate 11.
この後、マスクとして用いた上記シリコン酸化膜１４を
除去し、次いで満１６の内周面に熱酸化法によりシリコ
ン酸化Ｂ１１７を形成する。この後、上記シリコン窒化
ｗＡ１３及びシリコン酸化１１１１２を全面除去し、新
たに溝１６の内周面を含む全面にシリコン酸化１１１８
及びシリコン窒化膜１９を形成する。この後、多結晶シ
リコン層２０をＣＶＤ法により１０００人ないし５００
０人程度成長させる （第１図（ｂ））。Thereafter, the silicon oxide film 14 used as a mask is removed, and silicon oxide B 117 is then formed on the inner peripheral surface of the full 16 layers by thermal oxidation. After that, the silicon nitride wA13 and the silicon oxide 11112 are completely removed, and a new silicon oxide 1118 is added to the entire surface including the inner peripheral surface of the groove 16.
and a silicon nitride film 19 is formed. Thereafter, the polycrystalline silicon layer 20 is deposited by 1000 to 500 layers by CVD method.
0 people (Figure 1 (b)).
次に上記多結晶シリコン層２０の表面に約１０００成長
度のシリコン窒化ｐ１１２１をＣＶＤ法により形成し、
次に溝１６が埋まるように多結晶シリコン層２２を成長
させる。このときの多結晶シリコン層２２の膜厚は溝１
６の幅にもよるが、溝１６の当初の幅を１．５μｍとす
ると１μｍ程度の厚さにすると溝１６がほぼ埋め込まれ
る（第１図（Ｃ））。Next, silicon nitride p1121 with a growth degree of about 1000 is formed on the surface of the polycrystalline silicon layer 20 by the CVD method,
Next, a polycrystalline silicon layer 22 is grown so as to fill the groove 16. The film thickness of the polycrystalline silicon layer 22 at this time is
Although it depends on the width of the groove 16, if the original width of the groove 16 is 1.5 μm, the groove 16 is almost buried when the thickness is about 1 μm (FIG. 1(C)).
次に上記多結晶シリコン！２２を塩素系ガスプラズマを
用いた異方性ドライエツチング法によりエツチングして
いき、基板１１の平坦面上のシリコン窒化膜２１の表面
が露出した時点でエツチングを止める。これにより満１
６の内部にのみ、後からｍ積した第２層目の多結晶シリ
コン層２２を残す。さらに、表面に露出しているシリコ
ン窒化膜２１を等方性ドライエツチング法で除去した後
、溝１６の付近及び素子を形成しない基板表面上にのみ
多結晶シリコン層２０を選択的に残すようにバターニン
グする。（第１図（ｄ））。Next is the polycrystalline silicon mentioned above! 22 is etched by an anisotropic dry etching method using chlorine gas plasma, and the etching is stopped when the surface of the silicon nitride film 21 on the flat surface of the substrate 11 is exposed. As a result, 1
The second layer of polycrystalline silicon layer 22, which is later stacked by m, is left only in the interior of 6. Furthermore, after removing the silicon nitride film 21 exposed on the surface by an isotropic dry etching method, the polycrystalline silicon layer 20 is selectively left only in the vicinity of the groove 16 and on the substrate surface where no element will be formed. Buttering. (Figure 1(d)).
次に熱酸化法により、多結晶シリコン層２０及び溝１６
を埋めている多結晶シリコン層２２の表面を熱酸化して
厚い膜厚のフィールド酸化Ｉ！４２３を形成する（第１
図（ｅ））、この後は、上記溝１６の部分以外のところ
に素子を形成する。Next, by a thermal oxidation method, the polycrystalline silicon layer 20 and the groove 16 are
The surface of the polycrystalline silicon layer 22 filling the area is thermally oxidized to form a thick field oxidation I! 423 (first
(e), after this, elements are formed in areas other than the groove 16.
このような工程により、満１６で構成された分離領域が
形成される。ところで、上記のような方法によれば、多
結晶シリコン層２２の堆積は満１６の当初よりも狭い幅
を埋めることになるので短時間で埋めることができる。Through this process, 16 isolation regions are formed. By the way, according to the method described above, the polycrystalline silicon layer 22 is deposited to fill a narrower width than the original width of the 16th layer, so it can be filled in a short time.
例えば、従来の方法では溝の当初の幅を１．５μｍとす
ると、この溝を埋めるためには多結晶シリコン層を３μ
ｍ程度堆積しなければならないが、上記実施例の場合に
は１μｍでよい。また、上記実施例によればこの多結晶
シリコン層２２の膜厚が薄いため、この層２２のエツチ
ングに必要な時間を短くすることができる。For example, in the conventional method, if the initial width of the trench is 1.5 μm, a polycrystalline silicon layer of 3 μm is required to fill the trench.
The thickness must be approximately 1 .mu.m, but in the case of the above embodiment, 1 .mu.m is sufficient. Further, according to the above embodiment, since the polycrystalline silicon layer 22 is thin, the time required for etching this layer 22 can be shortened.
また、第２の多結晶シリコン層２２のエツチングの際に
、基体１１の平坦面上に位置しているシリコン窒化膜２
１の表面が露出した時点でエツチングを止めればよいた
め、エツチングの制御性が容易である。さらに、多結晶
シリコン層２２のエツチングを制陣性良く行なうことが
できるため、この後に形成されるフィールド酸化膜２３
の膜厚をＲ適値にすることができ、段差を発生が防止で
きて表面の平坦性を保つことができる。Also, when etching the second polycrystalline silicon layer 22, the silicon nitride film 2 located on the flat surface of the base 11 is etched.
Since it is sufficient to stop etching when the surface of 1 is exposed, the etching can be easily controlled. Furthermore, since the polycrystalline silicon layer 22 can be etched with good controllability, the field oxide film 22 formed subsequently can be etched with good controllability.
The film thickness can be set to an appropriate value R, and the generation of steps can be prevented and the surface flatness can be maintained.
また、残された第１層目の多結晶シリコン層２０を酸化
してフィールド酸化膜２３を形成するようにしているの
で、溝１６の位置で基体１１が酸化されることがなく、
従って基体１１の酸化による結晶欠陥の発生を押さえる
ことができる。Furthermore, since the remaining first polycrystalline silicon layer 20 is oxidized to form the field oxide film 23, the base 11 is not oxidized at the groove 16.
Therefore, generation of crystal defects due to oxidation of the substrate 11 can be suppressed.
第２図はこの発明をバイポーラトランジスタの製造に実
施した場合の製造工程を順次示す断面図である。FIG. 2 is a cross-sectional view sequentially showing manufacturing steps when the present invention is applied to manufacturing a bipolar transistor.
ここでは前記シリコン半導体基板１１として、Ｐ型シリ
コン基板１１Ａの表面にＮ１型の埋め込み層１１Ｂを堆
積し、さらにこの層１１Ｂ上にＮ型エピタキシャル層１
１Ｃを成長させたものを使用する。そしてまず、エピタ
キシャル１１１１Ｃの表面に熱酸化法もしくはＣＶＤ法
によりシリコン酸化膜１２を形成し、その上にシリコン
窒化ｌｌ１１３を減圧ＣＶＤ法などの方法で堆積する。Here, as the silicon semiconductor substrate 11, an N1 type buried layer 11B is deposited on the surface of a P type silicon substrate 11A, and an N type epitaxial layer 1 is further deposited on this layer 11B.
Use grown 1C. First, a silicon oxide film 12 is formed on the surface of the epitaxial film 1111C by a thermal oxidation method or a CVD method, and silicon nitride 113 is deposited thereon by a method such as a low pressure CVD method.
次に、上記シリコン窒化１９１３上に、基板１１を選択
エツチングする際のマスク材料となるシリコン酸化ｌ１
１４をＣＶＤ法により堆積する。さらに、このシリコン
酸化ｌｌ１１４上にフォトレジスト膜１５を塗布形成す
る。しかる後、フォトレジスト［１１５の露光及び現像
を行ない不要部分を除去してパターニングを行なう（第
２図（ａ））。Next, on the silicon nitride 1913, silicon oxide l1, which will be a mask material when selectively etching the substrate 11, is etched.
14 is deposited by CVD method. Further, a photoresist film 15 is coated and formed on this silicon oxide 114. Thereafter, the photoresist [115] is exposed and developed to remove unnecessary portions and patterned (FIG. 2(a)).
続いて上記レジスト膜１５をエツチング用のマスクとし
て、ＣＦ４などのガスを用いた異方性ドライエッチング
（例えばＲＩＥ、すなわち反応性イオンエツチング）に
より上２シリコン酸化ｇ１１４、シリコン窒化膜１３及
びシリコン酸化膜１２を順次、選択的にエツチングし、
その後、レジストｆｉ！１５をＩＩ！素プラズマ中で燃
焼するか、硫酸系水溶液で処理することにより剥離する
。次にシリコン酸化膜１４をエツチング用のマスクとし
、ＲＩＥ（反応性イオンエツチング）を用いた異方性エ
ツチング技術により基板１１を選択的にエツチングして
Ｐ型シリコン基板１１Ａに達する溝１６を形成する。こ
のとき、異方性エツチング技術の持つ特性により、溝１
Ｇの側面が基板１１の平坦面に対して垂直もしくは略垂
直となるように形成される。この侵、ボロンを基板１１
表面より垂直にイオン注入して、チャネルストッパー領
域４１を溝１６の底部に位置する基板１１Ａに形成する
（第２図（ｂ））。Next, using the resist film 15 as an etching mask, anisotropic dry etching (for example, RIE, ie, reactive ion etching) using a gas such as CF4 is performed to remove the upper silicon oxide film 114, the silicon nitride film 13, and the silicon oxide film. 12 sequentially and selectively etching,
After that, resist fi! 15 II! Peel off by burning in elementary plasma or treating with sulfuric acid-based aqueous solution. Next, using the silicon oxide film 14 as an etching mask, the substrate 11 is selectively etched by an anisotropic etching technique using RIE (reactive ion etching) to form a groove 16 that reaches the P-type silicon substrate 11A. . At this time, due to the characteristics of anisotropic etching technology, the groove 1
The side surface of G is formed to be perpendicular or substantially perpendicular to the flat surface of the substrate 11. During this attack, boron is transferred to the substrate 11.
Ions are implanted perpendicularly from the surface to form a channel stopper region 41 in the substrate 11A located at the bottom of the groove 16 (FIG. 2(b)).
この後、マスクとして用いた上記シリコン酸化膜１４を
除去し、次いで満１６の内周面に熱酸化法によりシリコ
ン酸化膜１７を形成する。この後、上記シリコン？化膜
１３及びシリコン酸化膜１２を全面除去し、新たに満１
６の内周面を含む全面にシリコン酸化膜１８及びシリコ
ン窒化膜１９を形成する。この後、多結晶シリコン層２
０をＣＶＤにより１０００人ないし５０００人程度成長
させる（第２図（Ｃ））。Thereafter, the silicon oxide film 14 used as a mask is removed, and then a silicon oxide film 17 is formed on the inner peripheral surface of the silicon oxide film 17 by thermal oxidation. After this, the silicon mentioned above? The silicon oxide film 13 and the silicon oxide film 12 are completely removed, and a new
A silicon oxide film 18 and a silicon nitride film 19 are formed on the entire surface including the inner circumferential surface of 6. After this, polycrystalline silicon layer 2
0 to about 1,000 to 5,000 people by CVD (Figure 2 (C)).
次に上記多結晶シリコン層２０の表面に杓１０００人程
成長シリコン窒化膜２１をＣＶＤ法により形成し、次に
満１６が埋まるように多結晶シリコン層２２を成長させ
る。このときの多結晶シリコン層２２の膜厚は溝１６の
幅にもよるが、満１６の当初の幅を１．５μｍとすると
１μｍ程度の厚さにすると満１６がほぼ埋め込まれる（
第２図（ｄ））。Next, on the surface of the polycrystalline silicon layer 20, a silicon nitride film 21 is grown in a thickness of about 1,000 ladle by CVD method, and then a polycrystalline silicon layer 22 is grown to fill the entire surface of the polycrystalline silicon layer 20. The thickness of the polycrystalline silicon layer 22 at this time depends on the width of the groove 16, but if the original width of the groove 16 is 1.5 μm, the thickness of the polycrystalline silicon layer 22 will be approximately 1 μm, and the groove 16 will be almost buried (
Figure 2(d)).
次に上記多結晶シリコン層２２を塩素系ガスプラズマを
用いた異方性ドライエツチング法によりエツチングして
いき、基板１１の平坦面上のシリコン窒化ｇｉ２１の表
面が露出した時点でエツチングを止める。これにより溝
１６の内部にのみ、後から堆積した第１！目の多結晶シ
リコン層２２をパす。さらに、表面に露出しているシリ
コン窒化膜２１を等方性ドライエツチング法で除去した
後、溝１６の付近及び素子を形成しない基板表面上にの
み多結晶シリコン層２０を選択的に残すようにバターニ
ングする。（第２図（ｅ））。Next, the polycrystalline silicon layer 22 is etched by an anisotropic dry etching method using chlorine-based gas plasma, and the etching is stopped when the surface of the silicon nitride gi 21 on the flat surface of the substrate 11 is exposed. As a result, the first ! The polycrystalline silicon layer 22 is removed. Furthermore, after removing the silicon nitride film 21 exposed on the surface by an isotropic dry etching method, the polycrystalline silicon layer 20 is selectively left only in the vicinity of the groove 16 and on the substrate surface where no element will be formed. Buttering. (Figure 2(e)).
次に熱酸化法により、多結晶シリコン層２０及び溝１６
を埋めている多結晶シリコン１２２の表面を熱酸化して
厚い膜厚のフィールド酸化！１１２３を形成する（第２
図（ｆ））。Next, by a thermal oxidation method, the polycrystalline silicon layer 20 and the groove 16 are
Thermal oxidation of the surface of the polycrystalline silicon 122 filling the area results in a thick field oxidation! 1123 (second
Figure (f)).
次に、全面にフォトレジスト２４を塗布した後、ＮＰＮ
トランジスタのコレクタ電極形成部分に対応した位置に
開口を有するようにバターニングし、このレジスト２４
及び上記フィールド酸化膜２３をマスクにしてリンをイ
オン注入することによりＮ＋型のコレクタ引き出し１ｉ
１２５をＮ型エピタキシャル層１１Ｇに形成する（第２
図（Ｑ））。Next, after coating the entire surface with photoresist 24, NPN
The resist 24 is patterned to have an opening at a position corresponding to the collector electrode forming portion of the transistor.
And by implanting phosphorus ions using the field oxide film 23 as a mask, an N+ type collector lead-out 1i is formed.
125 is formed in the N-type epitaxial layer 11G (second
Figure (Q)).
次に、再び全面にフォトレジスト２６を塗布した後、こ
のレジスト２６を上記コレクタ引き出し層２５を覆うよ
うな形状にバターニングした後、このレジスト２６及び
上記フィールド酸化１Ｉ２３をマスクにボロンをイオン
注入することによりＰ型のベース層２７をＮ型エピタキ
シャル層１１Ｇの表面に形成する（第２図（ｈ））。Next, after coating the entire surface with photoresist 26 again, this resist 26 is buttered into a shape that covers the collector extraction layer 25, and boron ions are implanted using this resist 26 and the field oxide 1I23 as a mask. As a result, a P type base layer 27 is formed on the surface of the N type epitaxial layer 11G (FIG. 2(h)).
次に、さらに再び全面にフォトレジスト２８を塗布し、
上記コレクタ引き出し層２５及びベース層２７それぞれ
に対応した位置に開口を有する形状にレジスト２８をバ
ターニングする。この後、このレジスト２８をマスクに
リンをイオン注入することにより上記ベース層２７の表
面にＮ型のエミツタ層２９を形成する（第２図（ｉ））
。Next, photoresist 28 is applied again to the entire surface,
The resist 28 is patterned into a shape having openings at positions corresponding to the collector extraction layer 25 and the base layer 27, respectively. Thereafter, an N-type emitter layer 29 is formed on the surface of the base layer 27 by ion-implanting phosphorus using the resist 28 as a mask (FIG. 2(i)).
.
この後は上記コレクタ引き出し層２５、ベース層２７及
びエミッタ！！２９それぞれの表面に通じるコンタクト
ホールを開口した後、全面に真空蒸着法によりアルミニ
ュームを被着させ、これをバターニングしてコレクタ電
極３０、ベースミル３１及びエミッタ電極３２それぞれ
を形成することによりＮＰＮトランジスタが完成する（
第２図（ｊ））。After this, the collector extraction layer 25, the base layer 27 and the emitter! ! 29 After opening contact holes leading to each surface, aluminum is deposited on the entire surface by vacuum evaporation method, and this is patterned to form a collector electrode 30, a base mill 31, and an emitter electrode 32, respectively, to form an NPN transistor. is completed (
Figure 2 (j)).
この実施例の方法でも第１図の場合と同様の理由により
、短時間で多結晶シリコン層の成長及びエツチングを行
なうことができ、かつ表面には段差が発生することがな
く、基板に対して結晶欠陥を発生させることがない。For the same reasons as in the case of FIG. 1, the method of this embodiment also allows the growth and etching of a polycrystalline silicon layer in a short time, and there is no difference in level on the surface, making it possible to grow and etch a polycrystalline silicon layer in a short time. Does not generate crystal defects.
なお、この発明は上記した実施例に限定されるものでは
なく種々の変形が可能であることはいうまでもない。例
えば、上記実施例では溝１６を形成した後に表面にシリ
コン酸化膜１８とシリコン窒化膜１９の二層膜を堆積す
る場合について説明したが、これはシリコン酸化膜のみ
を堆積するようにしてもよい。そして、このような場合
には、堆積された多結晶シリコン層２０の膜厚と、形成
すべきフィールド酸化膜２３の膜厚との関係に基づいて
基板表面が酸化される量をＩＩ ｎすることができる。It goes without saying that the present invention is not limited to the above-described embodiments, and that various modifications can be made. For example, in the above embodiment, a case has been described in which a two-layer film of a silicon oxide film 18 and a silicon nitride film 19 is deposited on the surface after forming the groove 16, but it is also possible to deposit only a silicon oxide film. . In such a case, the amount by which the substrate surface is oxidized is determined based on the relationship between the thickness of the deposited polycrystalline silicon layer 20 and the thickness of the field oxide film 23 to be formed. Can be done.
［発明の効果］
以上説明したようにこの発明によれば、多結晶シリコン
層の成長及びエツチングを短時間で行なうことができ、
また表面に段差が発生せず、かつ基板に結晶欠陥が発生
しない半導体装置の製造方法を提供することができる。[Effects of the Invention] As explained above, according to the present invention, a polycrystalline silicon layer can be grown and etched in a short time,
Further, it is possible to provide a method for manufacturing a semiconductor device in which no steps are generated on the surface and crystal defects are not generated in the substrate.
第１図（ａ）ないし第１図（ｅ）はこの発明の一実施例
による製造工程を示す断面図、第２図（ａ）ないし第２
図（ｊ）はこの発明の他の実施例による製造工程を示す
断面図、第３図（ａ）ないし第３図（ｄ）は従来方法に
よる製造工程を示す断面図である。
１１・・・シリコン半導体基板、１２・・・シリコン酸
化膜、１３・・・シリコン窒化膜、１４・・・シリコン
酸化膜、１５・・・フォトレジスト膜、１６・・・溝、
１７・・・シリコン酸化膜、１８・・・シリコン酸化膜
、１９・・・シリコン窒化膜、２０・・・多結晶シリコ
ン層、２１・・・シリコン窒化膜、２２・・・多結晶シ
リコン層、２３・・・フィールド酸化膜、２４．２６゜
２８・・・フォトレジスト、２５・・・コレクタ引き出
し層、２７・・・ベース層、２９・・・エミッタ、３０
・・・コレクタ電ｔｆＡ、３１・・・ベース電極、３２
・・・エミッタ電極。
出願人代理人 弁理士 鈴江武彦
第１図
第 １ 図
第２図
第３図FIGS. 1(a) to 1(e) are cross-sectional views showing the manufacturing process according to an embodiment of the present invention, and FIGS.
FIG. 3(j) is a sectional view showing the manufacturing process according to another embodiment of the present invention, and FIGS. 3(a) to 3(d) are sectional views showing the manufacturing process according to the conventional method. DESCRIPTION OF SYMBOLS 11... Silicon semiconductor substrate, 12... Silicon oxide film, 13... Silicon nitride film, 14... Silicon oxide film, 15... Photoresist film, 16... Groove,
17... Silicon oxide film, 18... Silicon oxide film, 19... Silicon nitride film, 20... Polycrystalline silicon layer, 21... Silicon nitride film, 22... Polycrystalline silicon layer, 23... Field oxide film, 24.26° 28... Photoresist, 25... Collector extraction layer, 27... Base layer, 29... Emitter, 30
...Collector electrode tfA, 31...Base electrode, 32
...Emitter electrode. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3
Claims (1)
周面及び上記基体の表面を連続して第１の絶縁膜で被覆
する工程と、上記溝部が埋まらない程度に上記第１の絶
縁膜上に第１の多結晶シリコン層を堆積する工程と、上
記第１の多結晶シリコン層を第２の絶縁膜で被覆する工
程と、上記溝部が埋まるように上記第２の絶縁膜上に第
２の多結晶シリコン層を堆積する工程と、上記第２の多
結晶シリコン層をエッチングしてこの第２の多結晶シリ
コン層を上記溝部内にのみ残す工程と、上記基体表面上
の第１の多結晶シリコン層を少なくとも上記溝部の位置
付近に残す工程と、上記工程で残された第１の多結晶シ
リコン層を酸化する工程とを具備したことを特徴とする
半導体装置の製造方法。 ２ 前記第１の絶縁膜が耐酸化性を有する膜を含んでい
る特許請求の範囲第１項に記載の半導体装置の製造方法
。 ３ 前記第２の多結晶シリコン層をエッチングしてこの
第２の多結晶シリコン層を上記溝部内にのみ残す工程の
後に、前記溝部以外の基体上の第２の絶縁膜を除去する
工程をさらに具備した特許請求の範囲第１項に記載の半
導体装置の製造方法。 ４ 前記溝部の側面が前記基体の平坦面に対して垂直も
しくは略垂直となるように形成される特許請求の範囲第
１項に記載の半導体装置の製造方法。 ５ 前記第１の多結晶シリコン層を酸化する際に同時に
前記溝部上の前記第２の多結晶シリコン層の表面も酸化
するようにした特許請求の範囲第１項に記載の半導体装
置の製造方法。[Scope of Claims] 1. A step of forming a groove in a semiconductor substrate, a step of continuously covering an inner circumferential surface of the groove and a surface of the substrate with a first insulating film, and a step of forming a groove to an extent that the groove is not filled. a step of depositing a first polycrystalline silicon layer on the first insulating film; a step of covering the first polycrystalline silicon layer with a second insulating film; a step of depositing a second polycrystalline silicon layer on the insulating film of the substrate; a step of etching the second polycrystalline silicon layer to leave the second polycrystalline silicon layer only in the groove; A semiconductor device comprising: a step of leaving a first polycrystalline silicon layer on the surface at least near the position of the groove; and a step of oxidizing the first polycrystalline silicon layer left in the above step. manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film includes a film having oxidation resistance. 3. After the step of etching the second polycrystalline silicon layer to leave the second polycrystalline silicon layer only in the groove, further step of removing the second insulating film on the substrate other than the groove. A method for manufacturing a semiconductor device according to claim 1. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the side surfaces of the groove are formed perpendicular or substantially perpendicular to the flat surface of the base. 5. The method of manufacturing a semiconductor device according to claim 1, wherein when oxidizing the first polycrystalline silicon layer, the surface of the second polycrystalline silicon layer on the groove portion is also oxidized at the same time. .
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169245A JPH07105436B2 (en) | 1986-07-18 | 1986-07-18 | Method for manufacturing semiconductor device |
| US07/072,446 US4810668A (en) | 1986-07-18 | 1987-07-13 | Semiconductor device element-isolation by oxidation of polysilicon in trench |
| KR1019870007715A KR900005121B1 (en) | 1986-07-18 | 1987-07-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61169245A JPH07105436B2 (en) | 1986-07-18 | 1986-07-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6325947A true JPS6325947A (en) | 1988-02-03 |
| JPH07105436B2 JPH07105436B2 (en) | 1995-11-13 |
Family
ID=15882931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61169245A Expired - Lifetime JPH07105436B2 (en) | 1986-07-18 | 1986-07-18 | Method for manufacturing semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4810668A (en) |
| JP (1) | JPH07105436B2 (en) |
| KR (1) | KR900005121B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02296352A (en) * | 1989-05-11 | 1990-12-06 | Nec Corp | Semiconductor device |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5457068A (en) * | 1992-11-30 | 1995-10-10 | Texas Instruments Incorporated | Monolithic integration of microwave silicon devices and low loss transmission lines |
| JPH07254640A (en) * | 1993-12-30 | 1995-10-03 | Texas Instr Inc <Ti> | Trench separation structure formation method in stack trench capacitor formation stage |
| US5405806A (en) * | 1994-03-29 | 1995-04-11 | Motorola Inc. | Method for forming a metal silicide interconnect in an integrated circuit |
| JP2861856B2 (en) | 1995-03-30 | 1999-02-24 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| US5724374A (en) * | 1996-08-19 | 1998-03-03 | Picolight Incorporated | Aperture comprising an oxidized region and a semiconductor material |
| JPH10303289A (en) * | 1997-04-30 | 1998-11-13 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| AU8369398A (en) * | 1997-07-11 | 1999-02-08 | Telefonaktiebolaget Lm Ericsson (Publ) | A process for manufacturing ic-components to be used at radio frequencies |
| US6136664A (en) * | 1997-08-07 | 2000-10-24 | International Business Machines Corporation | Filling of high aspect ratio trench isolation |
| US6020230A (en) * | 1998-04-22 | 2000-02-01 | Texas Instruments-Acer Incorporated | Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion |
| US7982284B2 (en) * | 2006-06-28 | 2011-07-19 | Infineon Technologies Ag | Semiconductor component including an isolation structure and a contact to the substrate |
| US7691734B2 (en) * | 2007-03-01 | 2010-04-06 | International Business Machines Corporation | Deep trench based far subcollector reachthrough |
| FR2990057A1 (en) * | 2012-04-26 | 2013-11-01 | St Microelectronics Crolles 2 | PROCESS FOR FORMING LOW TRENCHES |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5861641A (en) * | 1981-10-09 | 1983-04-12 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS6083346A (en) * | 1983-10-14 | 1985-05-11 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS61152062A (en) * | 1984-12-26 | 1986-07-10 | Hitachi Ltd | Manufacture of semiconductor device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5760851A (en) * | 1980-09-17 | 1982-04-13 | Hitachi Ltd | Dielectric isolation of semiconductor integrated circuit |
| US4356211A (en) * | 1980-12-19 | 1982-10-26 | International Business Machines Corporation | Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon |
| JPS6054453A (en) * | 1983-09-05 | 1985-03-28 | Oki Electric Ind Co Ltd | Manufacture of semiconductor integrated circuit device |
| US4528047A (en) * | 1984-06-25 | 1985-07-09 | International Business Machines Corporation | Method for forming a void free isolation structure utilizing etch and refill techniques |
| US4621414A (en) * | 1985-03-04 | 1986-11-11 | Advanced Micro Devices, Inc. | Method of making an isolation slot for integrated circuit structure |
-
1986
- 1986-07-18 JP JP61169245A patent/JPH07105436B2/en not_active Expired - Lifetime
-
1987
- 1987-07-13 US US07/072,446 patent/US4810668A/en not_active Expired - Lifetime
- 1987-07-16 KR KR1019870007715A patent/KR900005121B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5861641A (en) * | 1981-10-09 | 1983-04-12 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS6083346A (en) * | 1983-10-14 | 1985-05-11 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS61152062A (en) * | 1984-12-26 | 1986-07-10 | Hitachi Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02296352A (en) * | 1989-05-11 | 1990-12-06 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| US4810668A (en) | 1989-03-07 |
| KR900005121B1 (en) | 1990-07-19 |
| JPH07105436B2 (en) | 1995-11-13 |
| KR880002256A (en) | 1988-04-30 |
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