JPH0258778B2 - - Google Patents
Info
- Publication number
- JPH0258778B2 JPH0258778B2 JP56153242A JP15324281A JPH0258778B2 JP H0258778 B2 JPH0258778 B2 JP H0258778B2 JP 56153242 A JP56153242 A JP 56153242A JP 15324281 A JP15324281 A JP 15324281A JP H0258778 B2 JPH0258778 B2 JP H0258778B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- film
- forming
- nitride film
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 28
- 239000010703 silicon Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 26
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 230000003647 oxidation Effects 0.000 claims description 20
- 238000007254 oxidation reaction Methods 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 229910052814 silicon oxide Inorganic materials 0.000 description 20
- 238000005530 etching Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 13
- 238000002955 isolation Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り、特に素
子分離用の埋設シリコン酸化膜の形成方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a buried silicon oxide film for element isolation.
集積回路等の半導体装置の製造方法において、
集積度の向上、および製作工程の簡素化のために
埋設酸化膜による誘電体分離、さらには該埋設酸
化膜を用いた自己整合（Self―alignment）技術
による素子形成がさかんに行なわれている。この
埋設酸化膜を形成する方法としては、最も容易に
使用できる、シリコン窒化膜を耐酸化膜とした熱
酸化による選択酸化法が主に用いられている。 In a method for manufacturing semiconductor devices such as integrated circuits,
In order to improve the degree of integration and simplify the manufacturing process, dielectric isolation using a buried oxide film and furthermore self-alignment technology using the buried oxide film are frequently used to form elements. As a method for forming this buried oxide film, a selective oxidation method using thermal oxidation using a silicon nitride film as an oxidation-resistant film, which is the easiest to use, is mainly used.
従来の選択酸化法の１例を第１図〜第３図によ
り説明する。まず、ｎ型シリコン基板１１表面に
シリコン酸化膜１２及びシリコン窒化膜１３を、
順次、形成する（第１図）。次にフオトプロセス
法を用い、選択エツチングを行なつて、素子分離
領域上のシリコン窒化膜１３、シリコン酸化膜１
２を除去し、露出したシリコン基板表面をエツチ
ングして溝１４を形成する（第２図）。しかる後、
熱酸化法を用いて埋設シリコン酸化膜１５を形成
し、溝１４を埋める。 An example of a conventional selective oxidation method will be explained with reference to FIGS. 1 to 3. First, a silicon oxide film 12 and a silicon nitride film 13 are deposited on the surface of an n-type silicon substrate 11.
Form them sequentially (Fig. 1). Next, using a photo process method, selective etching is performed to remove the silicon nitride film 13 and silicon oxide film 1 on the element isolation region.
2 is removed and the exposed silicon substrate surface is etched to form a groove 14 (FIG. 2). After that,
A buried silicon oxide film 15 is formed using a thermal oxidation method to fill the trench 14.
こうして素子分離が行なわれ、それぞれ分離さ
れた島状領域に所望の素子を形成することにな
る。 Element isolation is thus performed, and desired elements are formed in each isolated island region.
しかし、この製造方法によると埋設シリコン酸
化膜を形成する時に、酸素（O2）が酸化膜中を、
シリコン窒化膜の下にも拡散して行く為、横方向
酸化が生じ、シリコン窒化膜下のシリコン基板も
少し酸化され、いわゆる“bird beak”が形成さ
れる。この為に、パターン幅の減少が生ずる。た
とえば、シリコン酸化膜約200Å、シリコン窒化
膜約1000Å、シリコンエツチング溝深さ約
0.6μm、埋設シリコン酸化膜膜厚約1.2μmとする
とパターン幅は約2μm減少することとなり、この
ような大きなパターン幅減少は、集積度を向上す
る上で大きな問題となる。その上、窒化膜下にシ
リコン酸化膜が部分的に形成されることにより、
シリコン基板内に大きな歪が加えられることとな
り、しいては結晶欠陥の発生となる等、素子形成
を行なう上での大きな欠点となつている。 However, according to this manufacturing method, when forming the buried silicon oxide film, oxygen (O 2 ) flows through the oxide film.
Since it also diffuses under the silicon nitride film, lateral oxidation occurs, and the silicon substrate under the silicon nitride film is also slightly oxidized, forming a so-called "bird beak." This results in a reduction in pattern width. For example, silicon oxide film is approximately 200 Å, silicon nitride film is approximately 1000 Å, silicon etching groove depth is approximately
If the thickness of the buried silicon oxide film is 0.6 μm and the thickness of the buried silicon oxide film is approximately 1.2 μm, the pattern width will be reduced by approximately 2 μm, and such a large pattern width reduction will be a major problem in improving the degree of integration. Moreover, by partially forming a silicon oxide film under the nitride film,
A large strain is applied to the silicon substrate, which in turn causes crystal defects, which is a major drawback in device formation.
本発明は上記の点に鑑み、埋設シリコン酸化膜
層を形成する際の横方向酸化を抑えて、基板内で
の歪発生を防止すると共に、素子分離領域の占有
面積を小さくして集積度向上を可能とした半導体
装置の製造方法を提供するものである。 In view of the above points, the present invention suppresses lateral oxidation when forming a buried silicon oxide film layer, prevents strain from occurring within the substrate, and improves the degree of integration by reducing the area occupied by the element isolation region. The present invention provides a method for manufacturing a semiconductor device that makes it possible to perform the following steps.
本発明の特徴は、シリコン基板上に選択的にシ
リコン窒化膜を形成する工程と、前記シリコン窒
化膜をマスクとして前記シリコン基板に溝を形成
する工程と、前記溝の底面および側面に露出せる
前記シリコン基板の部分に直接被着しかつ前記シ
リコン窒化膜を被覆せる多結晶シリコン膜を形成
する工程と、異方性プラズマエツチングをほどこ
すことにより前記シリコン窒化膜上の前記多結晶
シリコン膜を除去しかつ前記溝の底面に被着せる
前記多結晶シリコン膜を除去し、これにより前記
溝の側面の前記シリコン基板に前記多結晶シリコ
ン膜が直接被着した状態で前記溝の底面の前記シ
リコン基板を露呈せしめる工程と、しかる後に熱
酸化をほどこすことにより前記溝の側面に残余せ
る多結晶シリコン膜を酸化膜に交換する工程を有
する半導体装置の製造方法にある。このように本
発明では選択酸化時に溝の側面に多結晶シリコン
膜層を有しているからシリコン窒化膜下のシリコ
ン基板が酸化されることはない。又、シリコン窒
化膜下への入り込みには関係のない溝の底面は露
出して酸化するから溝の深さよりもより深い酸化
膜層が形全されより好ましい絶縁分離層となる。
さらにシリコン窒化膜は溝の形成としてのマスク
として用い、多結晶シリコン層の異方性エツチン
グの際のエツチングストツパーとして用い、選択
酸化の際のマスクとして用いる。すなわち一度形
状形成された上記シリコン窒化膜は三つの別の用
途に使用されるからそれだけ工程数が減少され製
造工程が簡素化される。又、異方性エツチングの
ときに多結晶シリコン層はまだ二酸化シリコン化
すなわち絶縁膜化していないから絶縁膜としての
シリコン窒化膜が有効なエツチングストツパーと
なり得る。又、側面はシリコンとシリコン酸化膜
が直接接する形となるからその密着性のよいもの
となる。 The features of the present invention include a step of selectively forming a silicon nitride film on a silicon substrate, a step of forming a groove in the silicon substrate using the silicon nitride film as a mask, and a step of forming a groove in the silicon substrate by using the silicon nitride film as a mask. forming a polycrystalline silicon film that is directly deposited on a portion of a silicon substrate and covering the silicon nitride film; and removing the polycrystalline silicon film on the silicon nitride film by performing anisotropic plasma etching. In addition, the polycrystalline silicon film deposited on the bottom surface of the trench is removed, so that the silicon substrate on the bottom surface of the trench is covered with the polycrystalline silicon film directly deposited on the silicon substrate on the side surface of the trench. The method of manufacturing a semiconductor device includes an exposing step and a subsequent step of replacing the polycrystalline silicon film remaining on the side surface of the trench with an oxide film by performing thermal oxidation. As described above, in the present invention, since the polycrystalline silicon film layer is provided on the side surface of the groove during selective oxidation, the silicon substrate under the silicon nitride film is not oxidized. Furthermore, since the bottom surface of the trench, which has no relation to the penetration under the silicon nitride film, is exposed and oxidized, an oxide film layer deeper than the depth of the trench is formed and becomes a more preferable insulating isolation layer.
Furthermore, the silicon nitride film is used as a mask for forming grooves, as an etching stopper during anisotropic etching of the polycrystalline silicon layer, and as a mask during selective oxidation. That is, the silicon nitride film once formed into a shape is used for three different purposes, which reduces the number of steps and simplifies the manufacturing process. Furthermore, since the polycrystalline silicon layer has not yet been converted into silicon dioxide, ie, an insulating film, during anisotropic etching, the silicon nitride film as an insulating film can serve as an effective etching stopper. In addition, since the silicon and silicon oxide films are in direct contact with each other on the side surfaces, their adhesion is good.
次に実施例に従がい本発明を詳細に説明する。
第４図〜第８図は、シリコン基板内に約1.1μmの
深さで埋設された埋設酸化膜の製造工程の主な断
面図である。 Next, the present invention will be explained in detail according to examples.
4 to 8 are main cross-sectional views of the manufacturing process of a buried oxide film buried in a silicon substrate to a depth of about 1.1 μm.
第４図は、ｎ型シリコン基板１１表面に、熱酸
化法により、シリコン酸化膜を約200Åの膜厚で
形成し、その上にシリコン窒化膜１３を、気相成
長（C.V.D.）法により、膜厚約1000Åで、被着
した所である。次にフオトプロセス法を用いて選
択的に、埋設酸化膜形成領域上のシリコン窒化膜
１３、シリコン酸化膜１２をエツチング除去し、
露出したシリコン基板表面を、CCl4ガス系によ
るプラズマエツチングを用いて食刻し、溝１４
を、0.6μmの深さで、形成する（第５図）。しか
る後に多結晶シリコン膜１６を気相成長法により
形成する（第６図）。この時の膜厚は、埋設シリ
コン酸化膜の所望の膜厚によつて変化し、埋設シ
リコン酸化膜の膜厚が約1.2μmであれば、多結晶
シリコン膜の膜厚は0.5μm程度が適当である。 FIG. 4 shows that a silicon oxide film with a thickness of about 200 Å is formed on the surface of an n-type silicon substrate 11 by thermal oxidation, and a silicon nitride film 13 is formed on top of the silicon oxide film 13 by vapor phase growth (CVD). The thickness is about 1000 Å, and this is where it was deposited. Next, the silicon nitride film 13 and silicon oxide film 12 on the buried oxide film forming region are selectively etched away using a photo process method,
The exposed silicon substrate surface is etched using plasma etching using a CCl 4 gas system to form grooves 14.
is formed at a depth of 0.6 μm (Fig. 5). Thereafter, a polycrystalline silicon film 16 is formed by vapor phase growth (FIG. 6). The film thickness at this time varies depending on the desired thickness of the buried silicon oxide film, and if the buried silicon oxide film has a thickness of about 1.2 μm, the appropriate thickness of the polycrystalline silicon film is about 0.5 μm. It is.
次に多結晶シリコン膜１６のエツチングを行な
う。このとき、エツチング方法としては、CCl4
系ガスによる異方性プラズマエツチングを用い、
基板表面全面をエツチングガスにさらす。する
と、エツチングに方向性があり、基板表面に垂直
な方向からしかエツチングされない為に、シリコ
ン・エツチング溝１４の側面以外の多結晶シリコ
ン膜を除去することとなる（第７図）。この時、
多結晶シリコン膜エツチング後、露出したシリコ
ン基板を再度エツチングしても良い。しかる後、
熱酸化法を用いて埋設シリコン酸化膜１５を形成
する（第８図）。すると、選択酸化時に、溝１４
の下面は従来通りに酸化されるが、側面は、多結
晶シリコン膜１６が酸化され、シリコン基板１１
自体は酸化されない。 Next, polycrystalline silicon film 16 is etched. At this time, the etching method is CCl 4
Using anisotropic plasma etching using a system gas,
The entire surface of the substrate is exposed to etching gas. Then, since the etching is directional and etching is performed only from the direction perpendicular to the substrate surface, the polycrystalline silicon film is removed from areas other than the side surfaces of the silicon etching groove 14 (FIG. 7). At this time,
After etching the polycrystalline silicon film, the exposed silicon substrate may be etched again. After that,
A buried silicon oxide film 15 is formed using a thermal oxidation method (FIG. 8). Then, during selective oxidation, the groove 14
The bottom surface of the silicon substrate 11 is oxidized as before, but the polycrystalline silicon film 16 is oxidized and the side surface of the silicon substrate 11 is oxidized.
itself is not oxidized.
従がつて、シリコン窒化膜１６の下に、選択酸
化時に、シリコン酸化膜が形成されることは無
い。その結果、選択酸化によるパターン幅の減少
や、結晶歪の発生を防止することが可能となる。 Therefore, no silicon oxide film is formed under the silicon nitride film 16 during selective oxidation. As a result, it is possible to prevent pattern width reduction and crystal distortion caused by selective oxidation.
以上、詳細に説明した様に、本発明によると、
選択酸化法により埋設シリコン酸化膜を形成する
時に、シリコン・エツチング溝形成後、溝の側面
のみに多結晶シリコン膜層を形成することによ
り、熱酸化時の横方向酸化を防止する。これによ
り、選択酸化時のパターン幅細化や結晶歪の発生
を防止することが可能となり、しいては集積度の
向上や、歩留向上が期待できる。 As explained above in detail, according to the present invention,
When forming a buried silicon oxide film by selective oxidation, after forming a silicon etching trench, a polycrystalline silicon film layer is formed only on the side surfaces of the trench to prevent lateral oxidation during thermal oxidation. This makes it possible to prevent thinning of the pattern width and generation of crystal distortion during selective oxidation, and is expected to improve the degree of integration and yield.
第１図〜第３図に従来の製造方法を工程順に示
した断面図であり、第４図〜第８図に本発明の実
施例の製造方法の主たる工程を示す断面図であ
る。尚、図中の記号は下記の事物と対応してい
る。
１１…シリコン半導体基板、１２，１５…シリ
コン酸化膜、１３…シリコン窒化膜、１４…シリ
コン・エツチング溝、１６…多結晶シリコン膜。
FIGS. 1 to 3 are cross-sectional views showing the conventional manufacturing method in the order of steps, and FIGS. 4 to 8 are cross-sectional views showing the main steps of the manufacturing method according to the embodiment of the present invention. The symbols in the figure correspond to the following items. 11... Silicon semiconductor substrate, 12, 15... Silicon oxide film, 13... Silicon nitride film, 14... Silicon etching groove, 16... Polycrystalline silicon film.
Claims (1)
形成する工程と、前記シリコン窒化膜をマスクと
して前記シリコン基板に溝を形成する工程と、前
記溝の底面および側面に露出せる前記シリコン基
板の部分に直接被着しかつ前記シリコン窒化膜を
被覆せる多結晶シリコン膜を形成する工程と、異
方性プラズマエツチングをほどこすことにより前
記シリコン窒化膜上の前記多結晶シリコン膜を除
去しかつ前記溝の底面に被着せる前記多結晶シリ
コン膜を除去し、これにより前記溝の側面の前記
シリコン基板に前記多結晶シリコン膜が直接被着
した状態で前記溝の底面の前記シリコン基板を露
呈せしめる工程と、しかる後に熱酸化をほどこす
ことにより前記溝の側面に残余せる多結晶シリコ
ン膜を酸化膜に交換する工程とを有することを特
徴とする半導体装置の製造方法。1. A step of selectively forming a silicon nitride film on a silicon substrate, a step of forming a groove in the silicon substrate using the silicon nitride film as a mask, and a step of forming a groove on the silicon substrate exposed at the bottom and side surfaces of the groove. forming a polycrystalline silicon film that is directly deposited and covering the silicon nitride film, and removing the polycrystalline silicon film on the silicon nitride film by performing anisotropic plasma etching and forming the grooves. removing the polycrystalline silicon film deposited on the bottom surface, thereby exposing the silicon substrate on the bottom surface of the trench with the polycrystalline silicon film directly deposited on the silicon substrate on the side surface of the trench; 1. A method of manufacturing a semiconductor device, comprising the step of subsequently performing thermal oxidation to replace the polycrystalline silicon film remaining on the side surfaces of the trench with an oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15324281A JPS5854651A (en) | 1981-09-28 | 1981-09-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15324281A JPS5854651A (en) | 1981-09-28 | 1981-09-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5854651A JPS5854651A (en) | 1983-03-31 |
| JPH0258778B2 true JPH0258778B2 (en) | 1990-12-10 |
Family
ID=15558160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15324281A Granted JPS5854651A (en) | 1981-09-28 | 1981-09-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5854651A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0620028A (en) * | 1992-06-29 | 1994-01-28 | Honda Motor Co Ltd | On-vehicle ecu device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59124141A (en) * | 1982-12-28 | 1984-07-18 | Toshiba Corp | Manufacture of semiconductor device |
| US5084413A (en) * | 1986-04-15 | 1992-01-28 | Matsushita Electric Industrial Co., Ltd. | Method for filling contact hole |
| US5472903A (en) * | 1994-05-24 | 1995-12-05 | United Microelectronics Corp. | Isolation technology for sub-micron devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54589A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Burying method of insulator |
-
1981
- 1981-09-28 JP JP15324281A patent/JPS5854651A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54589A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Burying method of insulator |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0620028A (en) * | 1992-06-29 | 1994-01-28 | Honda Motor Co Ltd | On-vehicle ecu device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5854651A (en) | 1983-03-31 |
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