JPS63240111A - Signal level adjusting circuit - Google Patents
Signal level adjusting circuitInfo
- Publication number
- JPS63240111A JPS63240111A JP7331787A JP7331787A JPS63240111A JP S63240111 A JPS63240111 A JP S63240111A JP 7331787 A JP7331787 A JP 7331787A JP 7331787 A JP7331787 A JP 7331787A JP S63240111 A JPS63240111 A JP S63240111A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- attenuation
- signal
- switching
- strobe signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000003111 delayed effect Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 101000863856 Homo sapiens Shiftless antiviral inhibitor of ribosomal frameshifting protein Proteins 0.000 description 1
- 241000219061 Rheum Species 0.000 description 1
- 102100029950 Shiftless antiviral inhibitor of ribosomal frameshifting protein Human genes 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000010902 straw Substances 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、たとえば音声増幅装置の音量調整用のがり，
ラム回路などに用いられるデジタル制御型の信号レベル
調整回路に係り、特にステ，ｆ当シの減衰量が異なる２
個以上のデジタル電子ボリュウム回路（以下、ゲリュウ
ム回路という）を備えた信号レベル調整回路に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a sound volume adjustment girder for, for example, an audio amplification device;
This is related to digitally controlled signal level adjustment circuits used in RAM circuits, etc., and in particular, the attenuation amount of the steering and f sections is different.
The present invention relates to a signal level adjustment circuit comprising more than one digital electronic volume circuit (hereinafter referred to as a Gerium circuit).
（従来の技術）
この種の従来の信号レベル調整回路を第４図に示す。即
ち、信号入力端子５１と信号出力端子５２との間に、ス
テップ当りの減衰量が大きく、たとえば１ ０ ｄＢ／
ステップを有する上位桁用の第１のゴリ，ウム回路５３
と、ステップ当りの減衰量が小さく、たとえば１ｄＢ／
ステツプを有する下位桁用の第２のポリ，ウム回路５４
とが直列に接続されている。５５はシフトレジスタ回路
であり、１個の制御データ入力端子５６から第５図に示
すようにシリアルに与えられる上位桁用の制御データＳ
Ａおよび下位桁用の制御データＳＢをクロック入力端子
５７からのクロ、り入力に同期して取シ込み、ノ！ラレ
ルの制御データＰＡおよびＰＲを各対応して第１のデー
タラッチ５８および第２のデータラ、チ５９に出力する
ものである。このデータラ、チ５Ｂ、５９は、データラ
、チ制御端子６０からのデータ書込み用のストローブ信
号入力を受けて前記制＃データＰＡ、ＰＢをラッチし、
ラッチした制御データを各対応して前記第１．第２の、
ｙリュウム回路５３．５４に減衰量指定入力として与え
るものである。(Prior Art) A conventional signal level adjustment circuit of this type is shown in FIG. That is, between the signal input terminal 51 and the signal output terminal 52, the amount of attenuation per step is large, for example, 10 dB/
First Gori, Um circuit 53 for upper digits with steps
, the attenuation per step is small, for example 1 dB/
Second poly,um circuit 54 for lower digits with steps
are connected in series. 55 is a shift register circuit, which receives control data S for upper digits serially applied from one control data input terminal 56 as shown in FIG.
The control data SB for A and the lower digits are taken in in synchronization with the clock input from the clock input terminal 57, and the control data SB for the lower digits are taken in, The parallel control data PA and PR are respectively outputted to the first data latch 58 and the second data latch 59. The data L/CH 5B, 59 receives a strobe signal input for data writing from the data L/CH control terminal 60, and latches the control # data PA, PB.
The latched control data is then transferred to the first . Second,
This is given to the Yium circuits 53 and 54 as an attenuation amount designation input.
上記信号レベル調整回路においては、減衰量が九とえば
９ ｄＢから１０ ｄＢに切り換わる桁上げ時とかたと
えば１０ ｄＢから９ ｄＢに切り換わる桁下げ時には
２個のボリュウム回路５１．５２が同時に動作するので
、切換雑音信号が発生する。特に、減衰量の大きな第１
のケリ、ラム回路５ノの切換雑音信号は大きく、この信
号レベル調整回路を使用した音声増幅装置などの品質を
低下させてしまうという問題があった。In the above signal level adjustment circuit, the two volume circuits 51 and 52 operate simultaneously when the attenuation is changed from 9 dB to 10 dB, for example, and when the attenuation is changed from 10 dB to 9 dB, for example, when the attenuation is carried. Therefore, a switching noise signal is generated. In particular, the first
However, the switching noise signal of the RAM circuit 5 is large, and there is a problem in that the quality of an audio amplification device using this signal level adjustment circuit is degraded.
（発８Ａが解決しようとする問題点）
本発明は、上記したよりに減衰量切換に際しての桁上げ
、桁下げ時に切換雑音信号が大きく発生するという問題
点を解決すべくなされたもので、上記切換雑音信号を低
減し得る信号レベル調整回路を提供することを目的とす
る。(Problem to be Solved by System 8A) The present invention has been made in order to solve the above-mentioned problem that a large switching noise signal is generated when carrying up or down when switching the attenuation amount. It is an object of the present invention to provide a signal level adjustment circuit that can reduce switching noise signals.
［発明の構成コ
（問題点を解決するための手段）
本発明の信号レベル調整回路は、信号入力端子と信号出
力端子との間にステップ当りの減衰量が異なる少なくと
も第１．第２のデジタル電子ボリュウム回路を直列に挿
入し、ステップ当りの減衰量が大きい方の第１のデジタ
ル電子ボリュウム回路の減衰ｔ’を切り換える際、この
切り換えの直前または直後にステップ当ジの減衰量が小
さい方の第２のデジタル電子ｙ リュウム回路の減衰量
を所定の範囲内の一端から他端へ切り換えるように制御
してなることを特徴とする。[Structure of the Invention (Means for Solving Problems)] The signal level adjustment circuit of the present invention includes at least first and second terminals having different attenuation amounts per step between a signal input terminal and a signal output terminal. When inserting a second digital electronic volume circuit in series and switching the attenuation t' of the first digital electronic volume circuit which has a larger attenuation amount per step, the attenuation amount per step is changed immediately before or after this switching. It is characterized in that the attenuation amount of the second digital electronic yium circuit, which has a smaller value, is controlled to be switched from one end to the other end within a predetermined range.
（作用）
減衰量切換に際しての第１のデジタル電子がリュウム回
路の減衰量切り換えによる桁上げ時、桁下げ時における
減衰量の変化量が小さくなるので、切換雑音信号が小さ
くなる。(Function) Since the amount of change in the attenuation amount when the first digital electron carries up or down due to the attenuation amount switching of the Rhium circuit during attenuation amount switching becomes smaller, the switching noise signal becomes smaller.
（実施例）
以下、図面を参照して本発明の一実施例を詳細に説明す
る。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図に示す信号レベル調整回路は、第４図に示した従
来の回路に比べて、第１のデータラ、チ８および第２の
データラ、チ９に与えるストローブ信号に時間差を持た
せるように遅延回路１１、インバータ１２．１３および
アンドゲート１４゜１５を付加した点が異なる。即ち、
信号入力端子１と信号出力端子２との間にたとえば１０
ｄＢ／ステ、プを有する上位桁用の第１のボリュウム
回路３と、たとえば１ ｄＢ／ステップを有する下位桁
用の第２のボリュウム回路４とが直列に挿入されている
。シフトレソスタ回路５は、制御データ入力端子６から
シリアルに与えられる上位桁用の制御データＳＡおよび
下位桁用の制御データＳＲをクロック入力端子７からの
クロ、り入力に同期して取シ込み、パラレルの制御デー
タＰＡおよびＰＢを各対応して上記第１のデータラ、チ
８および第２のデータラ、テ９に出力するものである。Compared to the conventional circuit shown in FIG. 4, the signal level adjustment circuit shown in FIG. The difference is that a delay circuit 11, inverters 12 and 13, and AND gates 14 and 15 are added. That is,
For example, 10
A first volume circuit 3 for the upper digits having dB/step and a second volume circuit 4 for the lower digits having, for example, 1 dB/step are inserted in series. The shift register circuit 5 takes in control data SA for upper digits and control data SR for lower digits, which are serially applied from a control data input terminal 6, in synchronization with the clock input from a clock input terminal 7, and inputs them in parallel. The control data PA and PB are outputted to the first data RA and TE 8 and the second data RA and TE 9 in correspondence with each other.
この第１．第２のデータラ、チ８，９は、各対応してデ
ータ書込み用の第１．第２のストローブ信号Ｓ１＋Ｓ鵞
を受けたときに制御データＰＡ、ＰＢをラッチし、ラッ
チ出力を第１．第２のボリュウム回路３，４に減衰量指
定入力として与えるものである。この場合、上記第１の
ストローブ信号Ｓ！は、データラッチ制御端子１０から
のストローブ信号入力が第１のインバータ１２によシ反
転され九反転ストローブ信号と、上記ストローブ信号入
力が遅延回路１１によシ所定時間遅延された遅延信号と
が、２人力の第１のアンドゲート１４によシアンド処理
された出力である。また、前記第２のストローブ信号Ｓ
！は、前記ストローブ信号入力が第２のインバータ１３
により反転された反転ストローブ信号と前記ストローブ
信号入力とが２人力の第２のアンドゲートＪ５によりア
ンド処理された出力である。This first. The second data rows 8 and 9 correspond to the first rows 8 and 9 for data writing. When the second strobe signal S1+S is received, the control data PA and PB are latched, and the latch output is sent to the first strobe signal. This is provided to the second volume circuits 3 and 4 as an attenuation amount designation input. In this case, the first strobe signal S! The strobe signal input from the data latch control terminal 10 is inverted by the first inverter 12, resulting in an inverted strobe signal, and the strobe signal input is delayed by a predetermined time by the delay circuit 11, resulting in a delayed signal. This is the output that has been cyan-processed by the first AND gate 14 operated by two people. Further, the second strobe signal S
! , the strobe signal input is connected to the second inverter 13
The inverted strobe signal inverted by the input strobe signal and the strobe signal input are AND-processed by the second AND gate J5, which is operated by two people.
次に、上記信号レベル調整回路の制御タイミングを第２
図に示すと共に減衰量切換動作について第３図（ａ）
、 （ｂ）を参照して説明する。シフトレソスタ回路５
に制御データＳＡ、ＳＢが格納された後、ストロ−７”
信号入力ｔ−ロウレベル→ハイレペ胎クロウレベル変化
させると、ストローブ信号入力と遅延回路１１の遅延出
力との時間差に対応するパルス幅を有し、上記ハイレベ
ル期間に見合う時間差ｔを有して第２．第１のストロー
ブ信号Ｓｘ＋８２が順に発生する。これによって、先ず
第２のストローブ信号Ｓ２により第２のデータラッチ９
で制御データＰＢがラッチされ、このラッチ出力により
第２のコリュウム回路４の減衰量が切換制御される。次
に、第１のストローブ信号ｓ１により第１のデータラッ
チ８で制御データＰＡがう。Next, the control timing of the signal level adjustment circuit is adjusted to a second level.
Figure 3 (a) shows the attenuation amount switching operation.
, (b). Shiftless star circuit 5
After the control data SA and SB are stored in the
When the signal input t is changed from low level to high repeat low level, it has a pulse width corresponding to the time difference between the strobe signal input and the delayed output of the delay circuit 11, and has a time difference t corresponding to the high level period, and the second ．． A first strobe signal Sx+82 is generated in turn. As a result, first, the second data latch 9 is activated by the second strobe signal S2.
The control data PB is latched, and the attenuation amount of the second corium circuit 4 is switched and controlled by this latch output. Next, the control data PA is loaded in the first data latch 8 by the first strobe signal s1.
チされ、このう、チ出力によｐ第１のボリュウム回路３
の減衰量が切換制御される。上記とは逆に、ストローブ
信号入力をハイレベル→ロウレベ紳ハイレベルと変化さ
せると、ストローブ信号入力と遅延回路１１の遅延出力
との時間差に一対応する・ヤルス幅を有し、上記ロウレ
ベル期間に見合う時間差ｔを有して第１．第２のストロ
ーブ信号Ｓ１ 。In this way, the first volume circuit 3 is
The amount of attenuation is controlled by switching. Contrary to the above, when the strobe signal input is changed from high level to low level to high level, it has a width corresponding to the time difference between the strobe signal input and the delayed output of the delay circuit 11, and during the low level period The first one with a corresponding time difference t. Second strobe signal S1.
Ｓ、が順に発生する。これによって、先ず第１の、ｙリ
ュウム回路３の減衰量が切換制御され、次に第２のｚｌ
Ｊニウム回路４の減衰量が切換制御される。S occurs in sequence. As a result, first, the attenuation amount of the first y-rium circuit 3 is switched and controlled, and then the amount of attenuation of the second z-lium circuit 3 is switched and controlled.
The amount of attenuation of the Jiumium circuit 4 is switched and controlled.
従って、レベル調整に際して下位桁用のポリ。Therefore, when adjusting the level, poly for the lower digits.
ラム回路４の切換制御のみで済む場合には、上記ス）ｏ
−プＭ号入力ｔハイレベル→ロウレベル→ハイレベルと
変化させても、あるいはロウレベル→ハイレベル→ロウ
レベルと変化させてもよい。If only the switching control of the ram circuit 4 is sufficient, the above step) o
-P No. M input t The signal may be changed from high level to low level to high level, or may be changed from low level to high level to low level.
しかし、減衰量の桁上げ、桁下げなど上位桁用の／リュ
ウム回路３の切換制御を伴う場合には、減衰量の減少（
ゴリーウム・アップ）または増大（ボリュウム・ダウン
）に応じて２個のボリュウム回路３．４の動作タイミン
グの順序を適切に選定する必要がある。即ち、ポリ、ラ
ム・アップ時ニハ、ストロ−！信号入力をロウレベル→
ハイレベル→ロウレベルと変化させて下位桁用ボリュウ
ム回路４、上位桁用ボリュウム回路３の順で動作させる
。この場合、下位桁用の制御データＳＢとして現在の減
衰′！ｋ（たとえば−６ｄＢ ）からたとえばＯｄＢま
で順に変化させたのち、たとえば−９ｄＢに設定し、さ
らに必要があれば所定値まで１ｄＢステ、ｆで変化させ
るものとし、上位桁用の制御データＳＡとしては下位桁
用データが上記ＯｄＢになったときに現在の減衰量（た
とえば−１０ｄＢ）から１０ ｄＢ減少したＯ ｄＢに
変化させる。これによって、本例では減衰量が−１６ｄ
Ｂから−１０ｄＢまでの範囲は１ ｄＢステ、ｆで下位
桁用ボリュウム回路４が切換制御され、次に下位桁用ボ
リュウム回路４が＝９ ｄＢになった直後（第１のスト
ローブ信号と第２のストローブ信号との時間差ｔだけ後
）に上位桁用、３ｆ リュウム回路３がＯｄＢになるよ
うに切換制御されることにより、減衰量が桁下げされて
一９ｄＢになる。従って、上位桁用メリュウム回路３の
切り換えにより減衰量が、−１０ｄＢから一９ｄＢにな
るので、切換雑音信号は従来のように一気に１０ｄＢの
切り換えを行う場合に比べて９ ｄＢ小さくなる（約１
／３になる）。However, when carrying up or down the attenuation amount involves switching control of the /rium circuit 3 for upper digits, the attenuation amount decreases (
It is necessary to appropriately select the order of the operation timings of the two volume circuits 3.4 depending on whether the volume is increased (volume up) or increased (volume down). In other words, poly, when ram up, niha, straw! Set signal input to low level →
The lower digit volume circuit 4 and the upper digit volume circuit 3 are operated in this order by changing from high level to low level. In this case, the control data SB for the lower digits is the current attenuation'! After changing in order from k (for example, -6 dB) to, for example, O dB, it is set to, for example, -9 dB, and if necessary, it is further changed in steps of 1 dB and f until it reaches a predetermined value, and the control data SA for the upper digits is When the data for the lower digit reaches the above O dB, the current attenuation amount (for example, -10 dB) is changed to O dB, which is decreased by 10 dB. As a result, in this example, the attenuation amount is -16d.
The range from B to -10 dB is 1 dB step, and f switches the lower digit volume circuit 4, and then immediately after the lower digit volume circuit 4 reaches =9 dB (the first strobe signal and the second strobe signal After the time difference t with the strobe signal), the 3f rhium circuit 3 for the upper digits is switched to O dB, and the attenuation is lowered to -9 dB. Therefore, the amount of attenuation changes from -10 dB to -9 dB by switching the Merium circuit 3 for upper digits, so the switching noise signal becomes 9 dB smaller (approximately 1
/3).
一方、ボリュウム・ダウン時には、上記とは逆にストロ
ーブ信号入力をハイレベル→ロウレベル→ハイレベルと
変化させて上位桁用ボリュウム回路３、下位桁用ボリー
ウム回路４の順で動作させる。この場合、下位桁用の制
御データＳＢとして現在の減衰量（たとえば−３ｄＢ）
からたとえば−９ｄＢまで順に変化させたのち、たとえ
ばＯｄＢに設定し、さらに必要があれば所定値まで１
ｄＢステ、！で変化させるものとし、上位桁用の制御デ
ータＳＡとしては下位桁用データがＯｄＢになったとき
に現在の減衰量（たとえば０ｄＢ）から１０ ｄＢ増大
した−１０ ｄＢに変化させる。これによって、本例で
は減衰量が−３ｄＢから−９ｄＢまでの範囲Ｆ１１ｄＢ
ステップで下位桁用メリュウム回路４が切換制御され、
次に下位桁用ボリュウム回路４がＯｄＢになる直前（第
２のストローブ信号と第１のストローブ信号との時間差
ｔだけ前）に上位桁用ｙＷ Ｉ）。On the other hand, when the volume is turned down, the strobe signal input is changed from high level to low level to high level, contrary to the above, and the volume circuit 3 for upper digits and the volume circuit 4 for lower digits are operated in that order. In this case, the current attenuation amount (for example -3 dB) is used as the control data SB for the lower digits.
After changing the value sequentially from -9dB to, for example, -9dB, set it to, for example, OdB, and if necessary, change it by 1 to a predetermined value.
dB Ste! The control data SA for the upper digits is changed from the current attenuation amount (for example, 0 dB) to -10 dB, which is increased by 10 dB, when the data for the lower digits becomes O dB. As a result, in this example, the attenuation amount is in the range F11 dB from -3 dB to -9 dB.
The mellium circuit 4 for lower digits is switched and controlled in the step.
Next, immediately before the lower digit volume circuit 4 becomes OdB (before the time difference t between the second strobe signal and the first strobe signal), the upper digit yW I).
ラム回路３が−１０ｄＢになるように切換制御されるこ
とにより、減衰量が桁上げされて一１０ｄＢになる。従
って、上位桁用ｚリーウム回路３の切り換えにより減衰
量が−９ｄＢから−１０ｄＢＫなるので、切換雑音信号
は従来のように一気に１０ｄＢの切夛換えを行う場合に
比べて９ ｄＢ小さくなる（約１／３になる）。By controlling the switching of the RAM circuit 3 to -10 dB, the attenuation amount is carried up to -10 dB. Therefore, since the attenuation amount changes from -9 dB to -10 dBK by switching the Z-reaum circuit 3 for upper digits, the switching noise signal becomes 9 dB smaller (about 1 /3).
また、ストローブ信号入力のパルス幅ｔを変えることに
よ＃）２つの〆す、ラム回路３，４の動作タイミング差
を任意に設定でき、切換雑音信号が最小になるように上
記時間ｔの最適化を図ることが可能である。In addition, by changing the pulse width t of the strobe signal input, the operating timing difference between the two closing and RAM circuits 3 and 4 can be set arbitrarily, and the above time t is optimized so that the switching noise signal is minimized. It is possible to achieve this goal.
なお、本発明は上記実施例に限られるものではなく、シ
リアルな制御データをシフトレジスタ回路に格納するこ
とに代えてパラレルな制御データを扱うようにしてもよ
い。また、信号入力端子１と信号出力端子２との間にス
テ、ｆ当夛の減衰量が異なる３個以上のがリュウム回路
を直列に挿入した場合にも、減衰量の桁上げ、桁下げ時
に上記実施例と同様に制御することによシ上記実施例と
同様な効果が得られる。Note that the present invention is not limited to the above-described embodiment, and instead of storing serial control data in the shift register circuit, parallel control data may be handled. Also, if three or more rheum circuits with different attenuation amounts for step and f are inserted in series between signal input terminal 1 and signal output terminal 2, when the attenuation amount is carried up or down, By controlling in the same manner as in the above embodiment, the same effects as in the above embodiment can be obtained.
［発明の効果］
上述したように本発明の信号レベル調整回路によれば、
減衰量の切り換えに際しての桁上げ時とか桁下げ時にお
ける切換雑音信号の発生を抑制することができる。従っ
て、本回路を音声増幅装置の音量ｖ４整用＆リュウムな
どに使用した場合、使用装置の品質を向上させることが
できる。[Effects of the Invention] As described above, according to the signal level adjustment circuit of the present invention,
It is possible to suppress the generation of a switching noise signal when carrying up or down when switching the attenuation amount. Therefore, when this circuit is used for volume adjustment and volume control of an audio amplification device, the quality of the device used can be improved.
第１図は本発明の信号レベル調整回路の一実施例を示す
プロ、り図、第２図は第１図の回路の制御タイミングの
一例を示すタイミング図、第３図（ａ） 、 （ｂ）は
第１図の回路のコリュウム・アップ時、〆リーウム・ダ
ウン時の減衰量切換動作の一例を示す特性図、第４図は
従来の信号レベル調整回路を示すプロ、り図、第５図は
第４図の回路の制御タイミングを示すタイミング図であ
る。
１・・・信号入力端子、２・・・信号出力端子、３，４
・・・デジタル電子ゴリーウム回路、８，９・・・デー
クラッチ。FIG. 1 is a schematic diagram showing an embodiment of the signal level adjustment circuit of the present invention, FIG. 2 is a timing diagram showing an example of the control timing of the circuit in FIG. 1, and FIGS. 3(a) and (b). ) is a characteristic diagram showing an example of the attenuation amount switching operation when columium is up and columium is down in the circuit of Fig. 1, Fig. 4 is a diagram showing a conventional signal level adjustment circuit, and Fig. 5 5 is a timing diagram showing the control timing of the circuit of FIG. 4. FIG. 1... Signal input terminal, 2... Signal output terminal, 3, 4
...Digital electronic golium circuit, 8,9...day clutch.
Claims (2)
りの減衰量が異なる少なくとも第１、第２のデジタル電
子ボリュウム回路を直列に接続し、ステップ当りの減衰
量が大きい方の第１のデジタル電子ボリュウム回路の減
衰量を切り換える際、この切り換えの直前または直後に
ステップ当りの減衰量が小さい方の第２のデジタル電子
ボリュウム回路の減衰量を所定の範囲内の一端から他端
へ切り換えるように制御してなることを特徴とする信号
レベル制御回路。(1) At least first and second digital electronic volume circuits having different amounts of attenuation per step are connected in series between the signal input terminal and the signal output terminal, and the first digital volume circuit having the larger amount of attenuation per step is connected in series between the signal input terminal and the signal output terminal. When switching the attenuation of the digital electronic volume circuit, the attenuation of the second digital electronic volume circuit with the smaller attenuation per step is switched from one end to the other within a predetermined range immediately before or after this switching. A signal level control circuit characterized in that it controls.
ム回路の減衰量の可変範囲であることを特徴とする前記
特許請求の範囲第１項記載の信号レベル調整回路。(2) The signal level adjustment circuit according to claim 1, wherein the predetermined range is a variable range of the amount of attenuation of the second digital electronic volume circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62073317A JP2656251B2 (en) | 1987-03-27 | 1987-03-27 | Signal level adjusting circuit and signal level adjusting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62073317A JP2656251B2 (en) | 1987-03-27 | 1987-03-27 | Signal level adjusting circuit and signal level adjusting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63240111A true JPS63240111A (en) | 1988-10-05 |
| JP2656251B2 JP2656251B2 (en) | 1997-09-24 |
Family
ID=13514674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62073317A Expired - Lifetime JP2656251B2 (en) | 1987-03-27 | 1987-03-27 | Signal level adjusting circuit and signal level adjusting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2656251B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06180595A (en) * | 1992-10-07 | 1994-06-28 | Hudson Soft Co Ltd | Sound and image processor |
| JPH09297998A (en) * | 1996-05-01 | 1997-11-18 | Nec Corp | Bi-directional shift register and digital control attenuator using the same |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54122341U (en) * | 1978-02-16 | 1979-08-27 | ||
| JPS54144854A (en) * | 1978-05-04 | 1979-11-12 | Matsushita Electric Ind Co Ltd | Controller for signal amount |
| JPS57124934A (en) * | 1981-01-26 | 1982-08-04 | Mitsubishi Electric Corp | Signal switching device |
| JPS58178724U (en) * | 1982-05-25 | 1983-11-30 | 株式会社ケンウッド | Gain switching circuit in amplifier |
| JPS5931050U (en) * | 1982-08-20 | 1984-02-27 | 株式会社島津製作所 | pin type grip |
| JPS6111007A (en) * | 1984-06-26 | 1986-01-18 | 住友ベークライト株式会社 | Attachment of water tank |
-
1987
- 1987-03-27 JP JP62073317A patent/JP2656251B2/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54122341U (en) * | 1978-02-16 | 1979-08-27 | ||
| JPS54144854A (en) * | 1978-05-04 | 1979-11-12 | Matsushita Electric Ind Co Ltd | Controller for signal amount |
| JPS57124934A (en) * | 1981-01-26 | 1982-08-04 | Mitsubishi Electric Corp | Signal switching device |
| JPS58178724U (en) * | 1982-05-25 | 1983-11-30 | 株式会社ケンウッド | Gain switching circuit in amplifier |
| JPS5931050U (en) * | 1982-08-20 | 1984-02-27 | 株式会社島津製作所 | pin type grip |
| JPS6111007A (en) * | 1984-06-26 | 1986-01-18 | 住友ベークライト株式会社 | Attachment of water tank |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06180595A (en) * | 1992-10-07 | 1994-06-28 | Hudson Soft Co Ltd | Sound and image processor |
| JPH09297998A (en) * | 1996-05-01 | 1997-11-18 | Nec Corp | Bi-directional shift register and digital control attenuator using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2656251B2 (en) | 1997-09-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |