JPH0349417A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0349417A JPH0349417A JP1186714A JP18671489A JPH0349417A JP H0349417 A JPH0349417 A JP H0349417A JP 1186714 A JP1186714 A JP 1186714A JP 18671489 A JP18671489 A JP 18671489A JP H0349417 A JPH0349417 A JP H0349417A
- Authority
- JP
- Japan
- Prior art keywords
- delay time
- circuit
- output
- semiconductor integrated
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000007613 environmental effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000003111 delayed effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に出力信号の遅延時
間かつ一定になるように設計される半導体集積回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit designed so that the delay time of an output signal is constant.
従来、この種の半導体集積回路は、第３図に示すように
、インバータＩ３１．Ｉ３２を備えた出力バッファ回路
３Ａを有し、入力信号ＩＮは、インバータＩ３１．Ｉ３
２によって所定の遅延時間を与えられて半導体集積回路
の外部へ出力信号ＯＵＴとして出力される構成となって
いた。Conventionally, this type of semiconductor integrated circuit includes inverters I31 . It has an output buffer circuit 3A with inverters I32, and input signals IN are connected to inverters I31. I3
2, the signal is given a predetermined delay time and is output as an output signal OUT to the outside of the semiconductor integrated circuit.
上述した従来の半導体集積回路は、出力バッファ回路３
Ａを構成するインバータＩ３１．Ｉ３２によって遅延時
間を設定する構成とな−）でいるので、出力に付加され
る負荷回路の容量や周囲温度１電源電圧等の環境条件に
より、遅延時間が著しく変化するため、遅延時間の規格
、特に遅延時間の最小規格と最大規格を同時に満足する
ような出力バッファ回路の設計が困難であり、しかも最
小規格と最大規格の幅が広くなるため半導体集積回路の
外部にこの幅を調整する別の回路を設けなければならな
いという欠点がある。The conventional semiconductor integrated circuit described above has an output buffer circuit 3.
Inverter I31. Since the delay time is set by I32, the delay time changes significantly depending on the capacity of the load circuit added to the output and environmental conditions such as ambient temperature and power supply voltage. In particular, it is difficult to design an output buffer circuit that satisfies the minimum and maximum delay time specifications at the same time.Moreover, since the width of the minimum and maximum specifications becomes wide, a separate circuit is required outside the semiconductor integrated circuit to adjust this width. The disadvantage is that a circuit must be provided.
本発明の目的は、外部に調整用の回路を設ける必要がな
く、しかも出力に付加される負荷回路の容量や周囲温度
、電源電圧等に影響されることなく常に所定の遅延時間
を与えることができる半導体集積回路を提供することに
ある。The purpose of the present invention is to eliminate the need for an external adjustment circuit and to always provide a predetermined delay time without being affected by the capacity of the load circuit added to the output, ambient temperature, power supply voltage, etc. Our goal is to provide semiconductor integrated circuits that can.
本発明の半導体集積回路は、入力信号に対し所定の遅延
時間を与え出力する基準遅延時間設定回路と、前記入力
信号に対してそれぞれ異なる遅延時間をもつ複数の信号
を生成し切換信号によりこれら信号の１つを選択して出
力する遅延時間切換回路と、この遅延時間切換回路の出
力信号を外部へ伝達する出力バッファ回路と、前記入力
信号に対するこの出力バッファ回路の出力信号と前記基
準遅延時間設定回路の出力信号との時間差を検出して前
記切換信号を出力する遅延時間切換制御回路とを有して
いる。The semiconductor integrated circuit of the present invention includes a reference delay time setting circuit that gives an input signal a predetermined delay time and outputs it, and generates a plurality of signals each having a different delay time with respect to the input signal, and switches these signals by a switching signal. a delay time switching circuit that selects and outputs one of the delay time switching circuits, an output buffer circuit that transmits the output signal of the delay time switching circuit to the outside, and an output signal of the output buffer circuit for the input signal and the reference delay time setting. and a delay time switching control circuit that detects a time difference with the output signal of the circuit and outputs the switching signal.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.
この実施例は、インバータ■ｔ、ｒ２を備え入力信号Ｉ
Ｎに対し所定の遅延時間を与え出力する基準遅延時間設
定回路１と、インバータ■３■４及びトランスファゲー
トＴ、、Ｔ２を備え入力信号ＩＮに対してそれぞれ異な
る遅延時間をもつ複数（この実施例では２つ）の信号を
生成し切換信号（Ｄ、Ｆ）によりこれら信号の１つを選
択して出力する遅延時間切換回路２と、インバータＩ５
．Ｉ６を備えこの遅延時間切換回路２の出力信号を外部
へ出力信号ＯＵＴとして伝達する出力バッファ回路３と
、ゲート回路Ｇ１〜Ｇ４及びインバータＩ、、Ｉ、を備
え入力信号ＩＮに対するこの出力バッファ回ｉ１３の出
力信号ＯＵＴと基準遅延時間設定回路１の出力信号（Ｂ
）との時間差を検出して切換信号（Ｄ、Ｆ）を出力する
遅延時間切換制御回路４とを有する構成となっている。This embodiment includes inverters t and r2, and an input signal I
A reference delay time setting circuit 1 for giving and outputting a predetermined delay time to N, a plurality of inverters 3 and 4 and transfer gates T, T2 each having a different delay time for the input signal IN (this embodiment The delay time switching circuit 2 generates two signals (D, F) and selects and outputs one of these signals using the switching signal (D, F), and the inverter I5.
．． An output buffer circuit 3 comprising I6 and transmitting the output signal of the delay time switching circuit 2 to the outside as an output signal OUT, and an output buffer circuit i13 comprising gate circuits G1 to G4 and inverters I, , I for input signal IN. The output signal OUT of the reference delay time setting circuit 1 and the output signal (B
) and a delay time switching control circuit 4 that detects the time difference between the delay time switching signal (D, F) and outputs a switching signal (D, F).
次に、この実施例の動作について説明する。Next, the operation of this embodiment will be explained.
第２図はこの実施例の動作を説明するための各部信号の
タイミング図である。FIG. 2 is a timing chart of signals of various parts for explaining the operation of this embodiment.
信号入力ＩＮは、遅延時間切換回路２を通って出力バッ
ファ回路３に入力され、半導体集積回路の出力信号ＯＵ
Ｔとして外部へ伝達される。同時に信号入力ＩＮは基準
遅延時間設定回路１に入力され、一定時間遅延された信
号が出力ラインＢに出力される。The signal input IN is inputted to the output buffer circuit 3 through the delay time switching circuit 2, and the output signal OU of the semiconductor integrated circuit is inputted to the output buffer circuit 3.
It is transmitted to the outside as T. At the same time, the signal input IN is input to the reference delay time setting circuit 1, and a signal delayed by a certain period of time is output to the output line B.
出力信号ＯＵＴが基準遅延時間設定回路１の出力信号（
Ｂ）より早く伝達される場合には（第２図ｔ１の期間）
、遅延時間切換制御回路４の出力信号（Ｄ）がＬ １１
レベル、出力信号（Ｆ）が“Ｈ′″レベルとなり、遅延
時間切換回路２のトランスファーゲートＴ、はオフ、ト
ランスフアゲ−） Ｔ ２はオンとなり、入力信号ＩＮ
はインバータＩ、、Ｉ４によって遅延された信号が出力
バッファ回路３に入力され、出力信号ＯＵ、Ｔは遅延さ
れる。The output signal OUT is the output signal of the reference delay time setting circuit 1 (
B) If it is transmitted earlier (period t1 in Figure 2)
, the output signal (D) of the delay time switching control circuit 4 is L 11
level, the output signal (F) becomes "H'" level, the transfer gate T of the delay time switching circuit 2 turns off, and the transfer gate T2 turns on, and the input signal IN
The signals delayed by inverters I, I4 are input to the output buffer circuit 3, and the output signals OU and T are delayed.
又、出力信号ＯＵＴが基準遅延時間設定回路１の出力信
号（Ｂ）より遅く伝達される場合には（第２図ｔ２の期
間）、遅延時間切換制御回路４の出力信号（Ｄ）が”Ｈ
１１レベル、出力信号（Ｆ）が“′Ｌ′°レベルとなり
、遅延時間切換回路２のトランスファーゲートＴ１はオ
ン、トランスファゲートＴ２はオフとなり、出力信号Ｏ
ＵＴは早くなる。Further, when the output signal OUT is transmitted later than the output signal (B) of the reference delay time setting circuit 1 (period t2 in FIG. 2), the output signal (D) of the delay time switching control circuit 4 becomes "H".
11 level, the output signal (F) becomes the "'L'° level, the transfer gate T1 of the delay time switching circuit 2 is turned on, the transfer gate T2 is turned off, and the output signal (F) is turned on.
UT will be faster.
この実施例では本発明を出力回路へ適用したときの例を
示したが、半導体集積回路の他の回路へも応用すること
ができる。Although this embodiment shows an example in which the present invention is applied to an output circuit, it can also be applied to other circuits of semiconductor integrated circuits.
以上説明したように本発明は、入力信号に対する、基準
遅延時間を設定する回路と複数の遅延時間を切換える回
路とを設け、この基準遅延時間を設定する回路の出力信
号と半導体集積回路の出力信号との時間差に応じて複数
の遅延時間のうちの１つを選択する構成とすることによ
り、出力に付加される負荷回路の容量、周囲温度、電源
電圧等の環境条件が変化しても常に一定の遅延時間にな
るようにすることができるので、半導体集積回路の外部
に遅延時間を調整する別の回路を取り付ける必要がなく
、同時に出力遅延時間の最小規格。As explained above, the present invention provides a circuit for setting a reference delay time and a circuit for switching a plurality of delay times for an input signal, and provides an output signal of the circuit for setting the reference delay time and an output signal of a semiconductor integrated circuit. By selecting one of multiple delay times according to the time difference between the This eliminates the need to install a separate circuit outside the semiconductor integrated circuit to adjust the delay time, and at the same time meets the minimum output delay time standard.
最大規格の幅が広くてもこれらを設定することができる
効果がある。This has the advantage that even if the maximum standard range is wide, it can be set.
第１図は本発明の一実施例を示す回路図、第２図は第１
図に示された実施例の動作を説明するための各部信号の
タイミング図、第３図は従来の半導体集積回路の一例を
示す回路図である。
１・・・基準遅延時間設定回路、２・・・遅延時間切換
回路、３，３Ａ・・・出力バッファ回路、４・・・遅延
時間切換制御回路、０１〜Ｇ４・・・ゲート回路、Ｉ。
〜’Ｂ 、Ｉ３１＋ １３２・・・インバータ、Ｔ、
、Ｔ２・・・トランスファゲート。Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a timing diagram of signals of various parts for explaining the operation of the embodiment shown in the figure. FIG. 3 is a circuit diagram showing an example of a conventional semiconductor integrated circuit. DESCRIPTION OF SYMBOLS 1... Reference delay time setting circuit, 2... Delay time switching circuit, 3, 3A... Output buffer circuit, 4... Delay time switching control circuit, 01-G4... Gate circuit, I. ~'B, I31+ 132...Inverter, T,
, T2...transfer gate.
Claims (1)
延時間設定回路と、前記入力信号に対してそれぞれ異な
る遅延時間をもつ複数の信号を生成し切換信号によりこ
れら信号の１つを選択して出力する遅延時間切換回路と
、この遅延時間切換回路の出力信号を外部へ伝達する出
力バッファ回路と、前記入力信号に対するこの出力バッ
ファ回路の出力信号と前記基準遅延時間設定回路の出力
信号との時間差を検出して前記切換信号を出力する遅延
時間切換制御回路とを有することを特徴とする半導体集
積回路。A reference delay time setting circuit that gives and outputs a predetermined delay time to an input signal, generates a plurality of signals each having a different delay time for the input signal, selects one of these signals by a switching signal, and outputs it. an output buffer circuit that transmits an output signal of the delay time switching circuit to the outside; and a time difference between the output signal of the output buffer circuit and the output signal of the reference delay time setting circuit in response to the input signal. A semiconductor integrated circuit comprising: a delay time switching control circuit that detects and outputs the switching signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1186714A JPH0349417A (en) | 1989-07-18 | 1989-07-18 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1186714A JPH0349417A (en) | 1989-07-18 | 1989-07-18 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0349417A true JPH0349417A (en) | 1991-03-04 |
Family
ID=16193355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1186714A Pending JPH0349417A (en) | 1989-07-18 | 1989-07-18 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0349417A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0579855A1 (en) * | 1992-07-23 | 1994-01-26 | Siemens Aktiengesellschaft | Propagation time compensation circuit |
| US5900761A (en) * | 1995-01-24 | 1999-05-04 | Advantest Corporation | Timing generating circuit and method |
| KR20170015372A (en) | 2014-07-02 | 2017-02-08 | 닛본 세이고 가부시끼가이샤 | Crown cage and angular contact ball bearing |
-
1989
- 1989-07-18 JP JP1186714A patent/JPH0349417A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0579855A1 (en) * | 1992-07-23 | 1994-01-26 | Siemens Aktiengesellschaft | Propagation time compensation circuit |
| US5900761A (en) * | 1995-01-24 | 1999-05-04 | Advantest Corporation | Timing generating circuit and method |
| WO2004100372A1 (en) * | 1995-01-24 | 2004-11-18 | Seiji Hideno | Circuit and method for generating timing |
| KR20170015372A (en) | 2014-07-02 | 2017-02-08 | 닛본 세이고 가부시끼가이샤 | Crown cage and angular contact ball bearing |
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