JPS63224375A - Superconducting transistor - Google Patents
Superconducting transistorInfo
- Publication number
- JPS63224375A JPS63224375A JP62058101A JP5810187A JPS63224375A JP S63224375 A JPS63224375 A JP S63224375A JP 62058101 A JP62058101 A JP 62058101A JP 5810187 A JP5810187 A JP 5810187A JP S63224375 A JPS63224375 A JP S63224375A
- Authority
- JP
- Japan
- Prior art keywords
- source
- drain electrodes
- superconducting
- semiconductor layer
- superconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002887 superconductor Substances 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000009826 distribution Methods 0.000 claims abstract description 4
- 238000004544 sputter deposition Methods 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 4
- 229910052727 yttrium Inorganic materials 0.000 claims description 2
- 229910002480 Cu-O Inorganic materials 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 8
- 239000007788 liquid Substances 0.000 abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 230000001747 exhibiting effect Effects 0.000 abstract description 2
- 229910000765 intermetallic Inorganic materials 0.000 abstract description 2
- 230000032683 aging Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001422 barium ion Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/437—Superconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/128—Junction-based devices having three or more electrodes, e.g. transistor-like structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Materials Engineering (AREA)
- Computer Hardware Design (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、ソース、ドレイン部に超伝導体を用いた超伝
導トランジスタに関する。Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a superconducting transistor using a superconductor in the source and drain portions.
（従来の技術）
現在まで、超高密度電子素子や超高速電子素子の開発は
、シリコン及び化合物半導体を中心として進められてき
た。従来の半導体素子の高密度化、高速化は、高度の微
細加工技術、均質で完全性の高い結晶作製技術及びシミ
ュレーションを利用した素子設計技術によりなし遂げら
れてきた。(Prior Art) Until now, the development of ultra-high-density electronic devices and ultra-high-speed electronic devices has focused on silicon and compound semiconductors. High density and high speed conventional semiconductor devices have been achieved through advanced microfabrication technology, homogeneous and highly perfect crystal manufacturing technology, and device design technology using simulation.
半導体素子の更なる高密度化、高速化を図る上で今後ま
すます重要になる問題は、発熱である。これは、結晶の
完全性や微細加工技術とは別に、半導体素子の高密度化
や高速化の限界を与える太きい要因になると考えられて
いる。Heat generation is an issue that will become increasingly important in the future as the density and speed of semiconductor devices are further increased. This is considered to be a major factor that limits the ability to increase the density and speed of semiconductor devices, in addition to crystal perfection and microfabrication technology.
電子素子の発熱の点で、半導体素子に比べて優れている
のは、ジョセフソン接合素子に代表される超伝導素子で
ある。しかし、超伝導素子はこれまでのところ、本格的
な実用化の目途は立っていない。その理由は、超伝導現
象が液体ヘリウム温度という超低温でないと得られない
こと、超伝導材料として金属あるいは金属間化合物を用
いるため酸化され易いこと、ジョセフソン接合素子の場
合にはその絶縁膜として用いる金属酸化物の時間的安定
性、空間的一様性が得られず、また本質的に二端子素子
であるため使い難いこと、等である。Superconducting devices, such as Josephson junction devices, are superior to semiconductor devices in terms of heat generation. However, to date, there is no prospect of full-scale practical use of superconducting devices. The reasons for this are that superconductivity can only be achieved at extremely low temperatures, such as the temperature of liquid helium, that metals or intermetallic compounds are used as superconducting materials and are easily oxidized, and that they are used as insulating films in Josephson junction devices. The temporal stability and spatial uniformity of metal oxides cannot be obtained, and since they are essentially two-terminal devices, they are difficult to use.
近年、ジョセフソン接合素子の二端子素子という欠点を
解消するものとして、超伝導体と半導体を結合した超伝
導トランジスタが試作されている。In recent years, superconducting transistors combining superconductors and semiconductors have been prototyped to overcome the shortcomings of Josephson junction devices, which are two-terminal devices.
これは、半導体層の一方の面に微少間隔をもって対向す
る一対の超伝導体電極（ソース、ドレイン電極）を設け
、他方の而に半導体層内のキャリア濃度分布を制御する
電極（ゲート電極）を設けた構造を有する。ゲート電極
により、ソース、ドレイン近傍のキャリア濃度が減少す
る方向のバイアスを与えるとソース、ドレイン電極間に
はジョセフソン接合が形成されず、ソース、ドレイン電
極間に超伝導電流は流れない。これがトランジスタのオ
フ状態である。一方、ゲート電極によりソース、ドレス
イン近傍のキャリア濃度を増大させるバイアスを与える
と、ある一定電圧以上でソース。In this method, a pair of superconductor electrodes (source and drain electrodes) are provided on one surface of the semiconductor layer, facing each other with a small distance, and an electrode (gate electrode) that controls the carrier concentration distribution within the semiconductor layer is provided on the other side. It has a built-in structure. If a bias is applied by the gate electrode in a direction that decreases the carrier concentration near the source and drain, a Josephson junction will not be formed between the source and drain electrodes, and no superconducting current will flow between the source and drain electrodes. This is the off state of the transistor. On the other hand, if a bias is applied to increase the carrier concentration near the source and dress-in by the gate electrode, the source will be drained at a certain voltage or higher.
ドレイン電極間にジョセフソン接合（超伝導接合）が形
成され、トランジスタはオン状態になる。これは、従来
厚み方向に対向させていたジョセフソン素子の一対の超
伝導電極を平面上に展開した形とし、その超伝導電極間
のキャリア濃度の制御により超伝導接合を形成するか否
かを制御するようにしたものと言うことができる。超伝
導接合には電圧零で電流が流れるから、この超伝導トラ
ンジスタは理論的に発熱がない。A Josephson junction (superconducting junction) is formed between the drain electrodes, and the transistor is turned on. In this method, a pair of superconducting electrodes of a Josephson element, which were conventionally opposed in the thickness direction, are expanded on a plane, and it is possible to form a superconducting junction by controlling the carrier concentration between the superconducting electrodes. It can be said that it is controlled. Since current flows through the superconducting junction with zero voltage, this superconducting transistor theoretically does not generate heat.
この超伝導トランジスタは、三端子素子である点で従来
のジョセフソン素子に比べて使い易いという利点を有す
るが、動作温度が液体ヘリウムあるいはその近傍という
超低温であり、また超伝導電極が材料的に空気中で不安
定である、という超伝導体素子の難点が解決されなけれ
ば、実用化は難しい。This superconducting transistor has the advantage of being easier to use than conventional Josephson devices in that it is a three-terminal element, but its operating temperature is extremely low, at or near liquid helium, and the superconducting electrode is Unless the drawback of superconductor devices, which is their instability in air, is resolved, it will be difficult to put them into practical use.
（発明が解決しようとする問題点）
以上のように超伝導素子は、発熱がない点で従来の半導
体素子の高密度化や高速化の限界を超え得るものとして
注目されるが、主として材料特性による制約から実用化
には至っていない。(Problems to be Solved by the Invention) As described above, superconducting devices are attracting attention as they do not generate heat and can exceed the limits of high density and high speed of conventional semiconductor devices, but mainly due to their material properties. It has not been put into practical use due to restrictions.
本発明はこの様な点に鑑み、液体窒素温反以上の温度で
動作可能で、空気中での安定性も優れた超伝導トランジ
スタを提供することを目的とする。In view of these points, it is an object of the present invention to provide a superconducting transistor that can operate at a temperature higher than that of liquid nitrogen and has excellent stability in air.
［発明の構成］
（問題点を解決するための手段）
本発明は、半導体層の一方の面に所定間隔をもって超伝
導体からなるソース、ドレイン電極を形成し、他方の面
に半導体層内のキャリア濃度分布を制御するためのゲー
ト電極を形成した構造の超伝導トランジスタにおいて、
ソース、ドレイン電極として、酸化物超伝導体を用いた
ことを特徴とする。[Structure of the Invention] (Means for Solving the Problem) The present invention forms source and drain electrodes made of a superconductor at predetermined intervals on one surface of a semiconductor layer, and forms superconductor electrodes in the semiconductor layer on the other surface. In a superconducting transistor with a structure in which a gate electrode is formed to control carrier concentration distribution,
It is characterized by using an oxide superconductor for the source and drain electrodes.
本発明において用いる酸化物超伝導体は例えば、Ｌ−Ｍ
−Ｃｕ−０で示される材料である。ここで、Ｌは、Ｌａ
、Ｓｃ、Ｙのうち少なくとも一種、Ｍは、Ｂａ、Ｓｒ、
Ｃａ、 のうち少なくとも一種からなる。この材料の化
学量論的組成からの僅かのずれは許容される。ゲート電
極部は例えばＭＯ３構造とし、電界効果によってソース
、ドレイン電極近傍の半導体層内のキャリア濃度制御を
行なうように構成すればよい。The oxide superconductor used in the present invention is, for example, L-M
-Cu-0 is the material. Here, L is La
, Sc, and Y; M is Ba, Sr,
It consists of at least one of Ca. Small deviations from the stoichiometric composition of this material are tolerated. The gate electrode portion may have an MO3 structure, for example, and may be configured to control the carrier concentration in the semiconductor layer near the source and drain electrodes by a field effect.
（作用）
上述した酸化物超伝導体は、超伝導を示す臨界混成Ｔｃ
が３０に以上と非常に高く、液体窒素温度で超伝導を示
す。材料作製技術の進歩により、更に臨界温度が高いも
のが得られる可能性が大きい。またこれらの酸化物超伝
導体は、従来の金属あるいは金属間化合物超伝導体に比
べて大気中での安定性が優れている。またシリコンなど
の半導体との界面特性も優れている。(Function) The above-mentioned oxide superconductor is a critical hybrid Tc exhibiting superconductivity.
is extremely high, over 30, and exhibits superconductivity at liquid nitrogen temperatures. With advances in material production technology, there is a strong possibility that materials with even higher critical temperatures will be obtained. These oxide superconductors also have superior stability in the atmosphere compared to conventional metal or intermetallic superconductors. It also has excellent interfacial properties with semiconductors such as silicon.
従って本発明によれば、簡便な冷凍機で得られる温度で
動作可能で、経時変化の少ない安定した素子特性が得ら
れる。そして三端子素子であるため使い易く、かつ発熱
がないことから、従来の半導体材料のみを用いた素子で
は得られない超高密度集積回路や超高速素子の実現・も
可能である。Therefore, according to the present invention, it is possible to operate at a temperature obtained by a simple refrigerator, and stable element characteristics with little change over time can be obtained. Since it is a three-terminal device, it is easy to use and does not generate heat, making it possible to realize ultra-high-density integrated circuits and ultra-high-speed devices that cannot be obtained with devices using only conventional semiconductor materials.
（実施例） 以下、本発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.
第１図は一実施例の超伝導トランジスタを示す。ホウ素
を１０１９／ｃ１１３ ドープしたｐ型Ｓｔ基板１を用
い、そのチャネル部を約０．５μｍの厚みに加工して、
裏面には１００人のシリコン酸化膜２を介してゲート電
極３を形成している。ゲート電極３はこの実施例ではＡ
ｕ電極である。基板１の表面には１００人のシリコン酸
化膜４がチャネル部に開口をもって形成され、この上に
酸化物超伝導体からなるソース、ドレイン電極５．６が
形成されている。具体的にこの実施例では、ソース、ド
レイン電極５．６の超伝導材料として、（Ｌａ Ｓ
ｒ ） ２ Ｃｕ Ｏを５００人の０．８５ ０
．１５ ３．９厚さにスパッタにより波管し、
これをパターン形成している。ソース、ドレイン電極５
．６間の距離は０．３μｍである。このソース、ドレイ
ン電極５．６−ＬにはＡｕ膜による端子電極７，８が形
成されている。FIG. 1 shows one embodiment of a superconducting transistor. Using a p-type St substrate 1 doped with 1019/c113 boron, the channel part was processed to a thickness of about 0.5 μm,
A gate electrode 3 is formed on the back surface with a silicon oxide film 2 of 100 layers interposed therebetween. The gate electrode 3 is A in this embodiment.
It is a u electrode. A 100-layer silicon oxide film 4 is formed on the surface of the substrate 1 with an opening in the channel portion, and source and drain electrodes 5.6 made of an oxide superconductor are formed thereon. Specifically, in this example, the superconducting material of the source and drain electrodes 5.6 is (LaS
r) 2 CuO to 500 people 0.85 0
．． 15 Corrugated tube by sputtering to 3.9 thickness,
This is used to form a pattern. Source, drain electrode 5
．． The distance between 6 is 0.3 μm. Terminal electrodes 7 and 8 made of Au films are formed on the source and drain electrodes 5.6-L.
この様な構成とし、ゲート電極３に零電圧またはソース
、ドレイン電極５，６近傍のキャリア密度（この実施例
の場合、正孔密度）が減少する正極性のバイアス電圧が
印加された場合、ソース。With this configuration, when zero voltage or a positive bias voltage that reduces the carrier density (hole density in this embodiment) near the source and drain electrodes 5 and 6 is applied to the gate electrode 3, the source .
ドレイン電極５，６間にはジョセフソン接合は形成され
ず、トランジスタはオフ状態に保たれる。No Josephson junction is formed between the drain electrodes 5 and 6, and the transistor is kept in an off state.
ゲート電極３を上記と逆に負にバイアスすると、ソース
、ドレイン電極５．６近傍の正孔密度が増大し、ある一
定ゲート電圧以上でソース、ドレイン電極５．６間にジ
ョセフソン接合が形成される。When the gate electrode 3 is negatively biased, contrary to the above, the hole density near the source and drain electrodes 5.6 increases, and a Josephson junction is formed between the source and drain electrodes 5.6 above a certain gate voltage. Ru.
これがトランジスタのオン状態である。This is the on state of the transistor.
第２図は、この超伝導トランジスタのソース・ドレイン
間の超伝導臨界電流のゲート電圧依存性を示す。ゲート
電圧的−６００ｍＶで急激な超伝導臨界電流の上昇が観
測される。測定温度は２０にである。FIG. 2 shows the gate voltage dependence of the superconducting critical current between the source and drain of this superconducting transistor. A rapid increase in superconducting critical current is observed at a gate voltage of -600 mV. The measurement temperature is 20°C.
この実施例の素子を１か月の間、常温の大気中に放置後
、同様の超伝導臨界電流の測定を行なったが、特性の変
動は認められなかった。After the device of this example was left in the atmosphere at room temperature for one month, the superconducting critical current was measured in the same manner, but no change in characteristics was observed.
次に、ソース、ドレイン電極１ご用いる酸化物超伝導体
として、ＹＢａ Ｃｕ Ｏ系を使用した実施例を説明す
る。この酸化物超伝導体は、臨界温度が９０〜１００に
と高く、また空気中での安定性も優れている。素子構造
は基本的に第１図の実施例と同じである。具体的な製造
条件を説明すれば、ｐ型Ｓｔ基板１はチャネル部分の厚
みを１００ｎａとし、その裏面にはゲート電極３として
シリコン酸化膜を介してＡノ膜を蒸着した。表面の酸化
物超伝導体からなるソース、ドレイン電極５，６は、ス
パッタによるＹＢａ Ｃｕ Ｏ薄膜である。Next, an example will be described in which YBa Cu O type is used as the oxide superconductor for the source and drain electrodes 1. This oxide superconductor has a high critical temperature of 90 to 100°C and also has excellent stability in air. The element structure is basically the same as the embodiment shown in FIG. To explain the specific manufacturing conditions, the p-type St substrate 1 had a channel portion having a thickness of 100 na, and an A film was deposited on the back surface of the p-type St substrate 1 as a gate electrode 3 via a silicon oxide film. The source and drain electrodes 5 and 6 made of an oxide superconductor on the surface are YBa Cu O thin films formed by sputtering.
スパッタ・ターゲットには、Ｙ２０３ 、Ｂａ Ｏ。Sputter target: Y203, BaO.
ＣｕＯの３種を第３図のように一つの円板状に組合わせ
た、厚さ５ ａｍ、直ｉ４８０ｍｔｘＯものを用いた。Three types of CuO were combined into one disk shape as shown in Fig. 3, and a thickness of 5 am and a diameter of 480mtxO was used.
Ｙ２Ｏ３とＢａＯとＣｕＯのターゲットでの面積比は１
：１：２である。この様なターゲットを基板と共に高周
波スパッタ装置のチ・ヤンバ内に取付け、１０− ’
ｔｏｒｒまで排気した後、Ａｒ−５０％０２ガスを５Ｘ
１０−２ｔｏｒｒの圧になるまで導入し、放電時の高
周波パワー２００Ｗでスパッタを行なった。これにより
厚さ１５０ｎｍのＹＢａ Ｃｕ Ｏ膜が形成される。こ
の薄膜は、ＰＭＭＡを用いた電子線描画とＡ「イオンエ
ツチングを用いて０．２μｍ間隔のソース、ドレイン電
極に分離した。The area ratio of Y2O3, BaO and CuO in the target is 1
:1:2. Install such a target together with the substrate in the chamber of the high frequency sputtering equipment, and
After exhausting to torr, Ar-50%02 gas was pumped 5X.
The pressure was introduced until the pressure reached 10<-2 >torr, and sputtering was performed with a high frequency power of 200 W during discharge. As a result, a YBa Cu O film with a thickness of 150 nm is formed. This thin film was separated into source and drain electrodes with an interval of 0.2 μm using electron beam lithography using PMMA and A-ion etching.
このようにして形成された素子はセラミック製パッケー
ジに固定し、各電極をＡノワイヤを用いてボンディング
接続した。そしてこれを液体窒素中に浸漬し、ゲート電
極に印加する電圧を変化させてソース、ドレイン電極間
の電流−電圧特性を測定した。The element thus formed was fixed in a ceramic package, and each electrode was connected by bonding using an A wire. Then, this was immersed in liquid nitrogen, and the voltage applied to the gate electrode was varied to measure the current-voltage characteristics between the source and drain electrodes.
第３図はその電流−電圧特性である。ゲート電圧がＯの
時はソ・−ス・ドレイン間には殆ど電流は流れず、ゲー
ト電圧を一１５０ｍＶとすると約１００μＡの超伝導電
流が観測された。FIG. 3 shows its current-voltage characteristics. When the gate voltage was O, almost no current flowed between the source and drain, and when the gate voltage was -150 mV, a superconducting current of about 100 μA was observed.
第５図のＡは、この実施例の超伝導トランジスタのゲー
ト電圧と超伝導電流の関係を測定した結果である。ゲー
ト電圧が０〜−８０ｍＶまでは超伝導電流は観ｐ１され
ないが、それ以上の負電圧で超伝導電流が観＃ｊされて
いる。A in FIG. 5 shows the result of measuring the relationship between the gate voltage and superconducting current of the superconducting transistor of this example. No superconducting current p1 is observed when the gate voltage is 0 to -80 mV, but superconducting current #j is observed at more negative voltages.
この実施例の超伝導トランジスタは、空気中に室温で２
週間放置した後も特性に変化は認められず、安定性に優
れていることも確認された。The superconducting transistor of this example can be immersed in air at room temperature.
No change in properties was observed even after leaving it for a week, confirming that it had excellent stability.
酸化物超伝導体として、Ｓｃ Ｂａ Ｃｕ Ｏ系薄膜を
用いた他、上記実施例と同様の超伝導トランジスタを作
った。酸化物超伝導薄膜用のターゲットは、Ｓｃ ２０
３ 、Ｂａ Ｏ，Ｃｕ Ｏを１枚の円板状に成型した複
合ターゲット（面積比は５ｃ２０３：ＢａＯ：ＣｕＯ−
１：１：２）を用いた。A superconducting transistor similar to the above example was fabricated except that a Sc Ba Cu O thin film was used as the oxide superconductor. The target for oxide superconducting thin film is Sc20
3. A composite target made of BaO and CuO molded into a disk shape (area ratio is 5c203:BaO:CuO-
1:1:2) was used.
この実施例の超伝導トランジスタの特性は第５図のＢの
ようになった。The characteristics of the superconducting transistor of this example were as shown in FIG. 5B.
以上では半導体層として単結晶Ｓｔを用いたが、酸化物
半導体を用いることも可能である。その様な実施例を第
６図に示す。この実施例では、ｐ型Ｓｉ基板１１を用い
、この上に酸化物半導体層としてＹ−Ｃｕ−０層１２を
スパッタ法により例えば１００ｎｉ形成し、このＹ−Ｃ
ｕ−０層１２に選択的にＢａをドープすることにより、
Ｙ−Ｂａ−Ｃｕ−０からなる酸化物超伝導体ソース、ド
レイン電極１３．１４を形成している。Ｙ−Ｃｕ−０層
１２は、Ｙ２Ｏ３とＣｕＯをターゲットとし、Ａｒ−５
０％０２ガス中で、５Ｘ１０−２ｔｏｒｒのガス圧で高
周波スパッタして得られる。またソース。Although single crystal St was used as the semiconductor layer in the above, it is also possible to use an oxide semiconductor. Such an embodiment is shown in FIG. In this example, a p-type Si substrate 11 is used, and a Y-Cu-0 layer 12 of, for example, 100 ni is formed thereon as an oxide semiconductor layer by sputtering.
By selectively doping Ba into the u-0 layer 12,
Oxide superconductor source and drain electrodes 13 and 14 made of Y-Ba-Cu-0 are formed. Y-Cu-0 layer 12 targets Y2O3 and CuO, and Ar-5
It is obtained by high frequency sputtering in 0% 02 gas at a gas pressure of 5×10 −2 torr. Also the sauce.
ドレイン電極１３．１４は、８５０℃に加熱された溶融
Ｂａを含み、Ｂａ蒸気が充満した拡散炉中に試料を投入
して、厚さ３００ ｎｍ程度に形成される。但し、ソー
ス、ドレイン電極１３．１４が０．２μｍの間隔をもっ
て分離されるように拡散炉投入前に分離部に酸化膜マス
クを形成しておく。The drain electrodes 13 and 14 contain molten Ba heated to 850° C. and are formed to have a thickness of about 300 nm by placing a sample into a diffusion furnace filled with Ba vapor. However, an oxide film mask is formed on the separated portion before charging into the diffusion furnace so that the source and drain electrodes 13 and 14 are separated by an interval of 0.2 μm.
最後に、ＡＩ！膜によりソース、ドレインの端子電極１
５．１６が形成され、基板１１裏面には予め形成されて
いたシリコン酸化膜１７を介してやはりＡ、ｆｆ膜によ
りゲート電極１８が形成される。Finally, AI! The source and drain terminal electrodes 1 are formed by the film.
5.16 is formed, and a gate electrode 18 is also formed of the A, ff film on the back surface of the substrate 11 via a silicon oxide film 17 formed in advance.
第７図はこの実施例による超伝導トランジスタのゲート
電圧と超伝導電流の関係を示す。この実施例によっても
先の各実施例と同様に超伝導電流をゲート電圧で制御す
ることができる。FIG. 7 shows the relationship between the gate voltage and superconducting current of the superconducting transistor according to this embodiment. In this embodiment as well, the superconducting current can be controlled by the gate voltage as in the previous embodiments.
本発明は上記実施例に限られるものではない。The present invention is not limited to the above embodiments.
例えば上記各実施例ではゲート電極として金属電極を用
いたが、ソース、ドレイン電極と同じように酸化物超伝
導体を用いることもできる。このようにすれば、本発明
の素子を具体回路に組込んだ時にゲート電極配線が長く
なってここで発熱が生じるのを防止することができ、実
用上有利である。For example, in each of the above embodiments, a metal electrode is used as the gate electrode, but an oxide superconductor can also be used in the same way as the source and drain electrodes. In this way, when the element of the present invention is incorporated into a concrete circuit, it is possible to prevent the gate electrode wiring from becoming long and generating heat there, which is advantageous in practice.
また酸化物超伝導体薄膜をスパッタ法で得るためのター
ゲットは例えば、Ｙ単体、ＢａＯ及びＣｕＯの組合せ、
Ｙ２Ｏ３，ＢａＯ及びＣｕの組合せ、Ｙ２Ｏ３，Ｂａ単
体及びＣｕＯの組合わせ等の各種ターゲットを用いるこ
とができる。また第６図の構造のソース、ドレイン電極
を形成する方法として、拡散法の他、Ｂａのイオン注入
法を利用することができる。更にまた、Ｙ−Ｃｕ−０層
全面にＢａの拡散を行い、その後例えばイオンスパッタ
法等によりソース、ドレイン電極を分離する溝を形成す
ることにより、同様の超伝導トランジスタを得ることが
できる。その池水発明で用いられる酸化物超伝導体材料
は、一般に、Ｌ−Ｍ−Ｃｕ −０（Ｌは、Ｌａ、Ｓｅ、
Ｙのうち少なくとも一種であり、Ｍは、Ｂａ、Ｓｒ、Ｃ
ａのうち少なくとも一種）で示されるものであればよい
。Further, targets for obtaining an oxide superconductor thin film by sputtering include, for example, Y alone, a combination of BaO and CuO,
Various targets can be used, such as a combination of Y2O3, BaO and Cu, a combination of Y2O3, Ba alone, and CuO. In addition to the diffusion method, a Ba ion implantation method can be used as a method for forming the source and drain electrodes of the structure shown in FIG. Furthermore, a similar superconducting transistor can be obtained by diffusing Ba over the entire surface of the Y-Cu-0 layer and then forming grooves separating the source and drain electrodes by, for example, ion sputtering. The oxide superconductor material used in the Ikemi invention is generally LM-Cu-0 (L is La, Se,
At least one type of Y, M is Ba, Sr, C
At least one of a) may be used.
その池水発明はその趣旨を逸脱しない範囲で種々変形し
て実施することができる。The pond water invention can be implemented with various modifications without departing from the spirit thereof.
［発明の効果］
以上述べたように本発明によれば、ソース、ドレイン電
極に酸化物超伝導体を用いることにより、液体温度以−
Ｌで動作させることができ、しかも安定な特性を示す超
伝導トランジスタを得ることができる。[Effects of the Invention] As described above, according to the present invention, by using an oxide superconductor for the source and drain electrodes, the temperature is lower than the liquid temperature.
A superconducting transistor that can be operated at L and exhibits stable characteristics can be obtained.
第１図は本発明の一実施例の超伝導トランジスタを示す
図、第２図はそのゲート電圧と超伝導電流の関係を示す
図、第３図は他の実施例に用いた酸化物超伝導体薄膜を
得るためのターゲット構成を示す図、第４図は他の実施
例による超伝導トランジスタのドレイン・ソース間電圧
と電流の関係を示す図、第５図は同じくゲート電圧と超
伝導電流の関係を示す図、第６図は史に他の実施例の超
伝導トランジスタを示す図、第７図はそのゲート電圧と
超伝導電流の関係を示す図である。
１・・・ｐ型Ｓｉ基板、２・・・シリコン酸化膜、３・
・・ゲート電極、４・・・シリコン酸化膜、５・・・ソ
ース電極（酸化物超伝導体）、６・・・ドレイン電極（
酸化物超伝導体）、７．８・・・端子電極、１１・・・
ｐ型Ｓｉ基板、１２・・・Ｙ−Ｃｕ−０層（酸化物半導
体層）、１３．１４・・・ソース、ドレイン電極（Ｙ−
Ｂａ−Ｃｕ −０酸化物超伝導体） 、１５．１６・・
・端子電極、１７・・・シリコン酸化膜、１８・・・ゲ
ート電極。
出願人代理人 弁理士 鈴江武彦
第３図
？
第４図
ｔ１４ｑ＄ ｒ！、ｔ−Ｉｃ （ｐＡ ＞第６図
イード電、丘、ＶＧ（ｍＶ）Figure 1 shows a superconducting transistor according to one embodiment of the present invention, Figure 2 shows the relationship between its gate voltage and superconducting current, and Figure 3 shows an oxide superconductor used in another embodiment. Figure 4 is a diagram showing the relationship between the drain-source voltage and current of a superconducting transistor according to another embodiment, and Figure 5 is a diagram showing the relationship between the gate voltage and superconducting current. FIG. 6 is a diagram showing the superconducting transistor of another embodiment, and FIG. 7 is a diagram showing the relationship between the gate voltage and superconducting current. 1...p-type Si substrate, 2...silicon oxide film, 3...
...Gate electrode, 4...Silicon oxide film, 5...Source electrode (oxide superconductor), 6...Drain electrode (
oxide superconductor), 7.8...terminal electrode, 11...
p-type Si substrate, 12...Y-Cu-0 layer (oxide semiconductor layer), 13.14... source, drain electrode (Y-
Ba-Cu-0 oxide superconductor), 15.16...
- Terminal electrode, 17... silicon oxide film, 18... gate electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 3? Figure 4 t14q$r! , t-Ic (pA > Figure 6 Eid electric current, hill, VG (mV)
Claims (4)
をもって配置されたソース、ドレイン電極と、前記半導
体層の他方の面に半導体層のキャリア濃度分布の制御を
行なうゲート電極とを備え、前記ソース、ドレイン電極
を酸化物超伝導体により構成したことを特徴とする超伝
導トランジスタ。(1) A semiconductor layer, source and drain electrodes arranged at a predetermined interval on one surface of the semiconductor layer, and a gate electrode for controlling the carrier concentration distribution of the semiconductor layer on the other surface of the semiconductor layer. A superconducting transistor, wherein the source and drain electrodes are made of an oxide superconductor.
導体は、Ｌ−Ｍ−Ｃｕ−Ｏ系（Ｌは、Ｌａ、Ｓｃ、Ｙの
うちの少なくとも一種、Ｍは、Ｂａ、Ｓｒ、Ｃａのうち
少なくとも一種）である特許請求の範囲第１項記載の超
伝導トランジスタ。(2) The oxide superconductor constituting the source and drain electrodes is based on the LM-Cu-O system (L is at least one of La, Sc, and Y, and M is one of Ba, Sr, and Ca). The superconducting transistor according to claim 1, which is at least one of the following.
、ドレイン電極を構成する酸化物超伝導体は、スパッタ
法により形成された膜である特許請求の範囲第１項記載
の超伝導トランジスタ。(3) The superconducting transistor according to claim 1, wherein the semiconductor layer is a single crystal semiconductor, and the oxide superconductor forming the source and drain electrodes is a film formed by sputtering.
、ドレイン電極は前記酸化物半導体に所定の元素を導入
して形成した酸化物超伝導体である特許請求の範囲第１
項記載の超伝導トランジスタ。(4) The semiconductor layer is an oxide semiconductor, and the source and drain electrodes are oxide superconductors formed by introducing a predetermined element into the oxide semiconductor.
Superconducting transistor described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62058101A JPS63224375A (en) | 1987-03-13 | 1987-03-13 | Superconducting transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62058101A JPS63224375A (en) | 1987-03-13 | 1987-03-13 | Superconducting transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63224375A true JPS63224375A (en) | 1988-09-19 |
Family
ID=13074567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62058101A Pending JPS63224375A (en) | 1987-03-13 | 1987-03-13 | Superconducting transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63224375A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6463223A (en) * | 1987-03-18 | 1989-03-09 | Sumitomo Electric Industries | Manufacture of superconductive thin film |
| JPS6463224A (en) * | 1987-03-18 | 1989-03-09 | Sumitomo Electric Industries | Manufacture of superconductive thin film |
| JPS6463222A (en) * | 1987-03-18 | 1989-03-09 | Sumitomo Electric Industries | Manufacture of superconductive thin film |
| JPS6463221A (en) * | 1987-03-18 | 1989-03-09 | Sumitomo Electric Industries | Manufacture of superconductive thin film |
| JPS6463220A (en) * | 1987-03-16 | 1989-03-09 | Sumitomo Electric Industries | Manufacture of superconductive thin film |
| US5441926A (en) * | 1992-12-29 | 1995-08-15 | Fuji Electric Co., Ltd. | Superconducting device structure with Pr-Ba-Cu-O barrier layer |
-
1987
- 1987-03-13 JP JP62058101A patent/JPS63224375A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6463220A (en) * | 1987-03-16 | 1989-03-09 | Sumitomo Electric Industries | Manufacture of superconductive thin film |
| JPS6463223A (en) * | 1987-03-18 | 1989-03-09 | Sumitomo Electric Industries | Manufacture of superconductive thin film |
| JPS6463224A (en) * | 1987-03-18 | 1989-03-09 | Sumitomo Electric Industries | Manufacture of superconductive thin film |
| JPS6463222A (en) * | 1987-03-18 | 1989-03-09 | Sumitomo Electric Industries | Manufacture of superconductive thin film |
| JPS6463221A (en) * | 1987-03-18 | 1989-03-09 | Sumitomo Electric Industries | Manufacture of superconductive thin film |
| US5441926A (en) * | 1992-12-29 | 1995-08-15 | Fuji Electric Co., Ltd. | Superconducting device structure with Pr-Ba-Cu-O barrier layer |
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