GB2151078A - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
- Publication number
- GB2151078A GB2151078A GB08430033A GB8430033A GB2151078A GB 2151078 A GB2151078 A GB 2151078A GB 08430033 A GB08430033 A GB 08430033A GB 8430033 A GB8430033 A GB 8430033A GB 2151078 A GB2151078 A GB 2151078A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 131
- 239000000969 carrier Substances 0.000 claims abstract description 21
- 238000002347 injection Methods 0.000 claims abstract description 16
- 239000007924 injection Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 description 30
- 238000009792 diffusion process Methods 0.000 description 13
- 239000012535 impurity Substances 0.000 description 13
- 239000000758 substrate Substances 0.000 description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 9
- 150000001875 compounds Chemical class 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 9
- 230000003321 amplification Effects 0.000 description 7
- 238000003199 nucleic acid amplification method Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005275 alloying Methods 0.000 description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000001629 suppression Effects 0.000 description 4
- 238000005036 potential barrier Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- -1 boron ions Chemical class 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 238000002050 diffraction method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
- H01L29/1008—Base region of bipolar transistors of lateral transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
A semiconductor device comprises a first emitter region 11 and a second collector region 12, both of the first conductivity type and formed on a semi-insulating semiconductor 10, and a third region 13 of opposite conductivity type also formed on the semiconductor 10 between these first and second regions 11 and 12. A forward bias voltage is applied between the third and first regions 13 and 11 so as to inject majority carriers from the third region 13 into a semi-insulating semiconductor region 17 beneath the third region 13 so that a virtual base region 18 is formed beneath the third region 13 and so that the semiconductor device can be operated as a bipolar transistor. A region may be formed on the surface of the semi-insulating semiconductor between the third and first regions for suppressing the injection of carriers. The third region may be made from an epitaxial layer of opposite conductivity type formed on the semiconductor. <IMAGE>
Description
SPECIFICATION
Semiconductor devices
This invention relates to semiconductor devices. Embodiments of the invention may form bipolar transistors in integrated circuits.
To simplify the manufacturing and wiring pattern of a bipolar transistor forming a circuit element of a semiconductor integrated circuit, it is desired that the bipolar transistor be of a so-called lateral structure in which respective regions such as an emitter, a base and a collector are located on the same surface. A bipolar transistor of lateral structure, however, genrally has a small current amplification fac tors.
Moreover, since a semiconductor device made of a compound semiconductor such as
GaAs is superior in high-speed operation, a semiconductor integrated circuit made of compound semiconductor is now often preferred.
In a compound semiconductor integrated circuit of this kind, as, for example, shown in
Fig. 1 of the accompanying drawings, there is formed on a semi-insulating compound semiconductor 1 a channel region 2 of, for example, n-type on which a gate region 3 of, for example, p-type is formed by a selective diffusion technique thereby to form a gate junction JG therebetween. A source region 4 of, for example, n-type, and a drain region 5 of n-type are formed selectively on the compound semiconductor 1 at respective sides of the n-type channel region 2. Thus a junctiontype field effect transistor J-FET is formed as a circuit element. However, this circuit element has the disadvantage that its threshold voltage is difficult to control, because the threshold voltage depends on the diffusion depth of the gate region 3.
According to the present invention there is provided a semiconductor device comprising:
a semi-insulating semiconductor;
a first region of a first conductivity type which becomes an emitter region;
a second region of the first conductivity type which becomes a collector region, said first and second regions being formed on said semi-insulating semiconductor with a predetermined distance therebetween; and
a third region of a second conductivity type formed on said semiconductor between said first and second regions;
wherein a forward bias voltage is applied between said third and first regions so as to form a virtual base region in a portion of said semi-insulating semiconductor beneath said third region by injected majority carriers from said third region, so that said semiconductor device can be operated as a bipolar transistor.
According to the present invention there is also provided a semi-conductor device comprising:
a semi-insulating semiconductor;
a first region of a first conductivity type which becomes an emitter region;
a second region of the first conductivity type which becomes a collector region, said first and second regions being formed on said semi-insulating semiconductor with a predetermined distance therebetween; and
a third region made of an epitaxial layer of a second conductivity type selectively formed on said semiconductor between said first and secind regions;
wherein a forward bias voltage is applied between said third and first regions so as to form a virtual base region in a portion of said semi-insulating semiconductor beneath said third region by injected majority carriers from said third region, so that said semiconductor device can be operated as a bipolar transistor.
In an embodiment of the invention, a first region of a first conductivity type which will become an emitter region and a second region of the same conductivity type which will become a collector region are formed on a semiinsulating semiconductor with a predetermined distance therebetween, and a third region of another conductivity type is formed on the semiconductor between the first and second regions. Then a forward bias voltage is applied between the third and first regions whereby majority carriers are injected from the third region into the semi-insulating semiconductor region beneath the third region, thereby to form a virtual base region beneath the third region, so that the semiconductor device can be operated as a bipolar transistor.
Additionally, a region for suppressing carrier injection may be formed on the surface of the semi-insulating semiconductor between the third and first regions and between the third and second regions thereby to avoid a null base current, so that the semiconductor device is of lateral structure but can carry out the operation of a bipolar transistor efficiently.
The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which:
Figure I is a cross-sectional view of a prior art semiconductor device;
Figures 2 to 4 are respective cross-sectional views of embodiments of semiconductor device according to this invention;
Figures 5 to 7 are respective cross-sectional views of embodiments of semiconductor device according to this invention in which there is provided a region for preventing a reactive base current; and
Figures 8 to 11 are respective cross-sectional views illustrating an example of a manufacturing method for producing an embodiment of semiconductor device according to this invention.
A first embodiment of semiconductor device according to the present invention will now be described with reference to Fig. 2. The device comprises a Ill-V compound semi-insulating semiconductor (for example, GaAs) layer or substrate 10, that is, having a low current carrier concentration and a high resistance (106 ohm. cm). In one major surface 10a of the semiconductor layer 10 there are formed first and second regions 11 and 12 of, for example, n-type, and having a high impurity concentration which will respectively become emitter and collector regions, at a predetermined spacing and with a predetermined depth from the major surface 1 ova. The first and second regions 11 and 12 are formed, for example, by an ion implantation technique.Between the first and second regions 11 and 12, there is formed a third region 13 of, for example, p-type having a high impurity concentration and a spacing of, for example, 1 micron, by an ion implantation technique or a diffusion technique. The third region 13 is formed such that it faces to the major surface 1 ova, to which the the first and second regions 11 and 12 are faced, and is disposed parallel to them. The depth of the third region 13 is selected to be smaller than that of the first and second regions 11 and 12, for example, about 1000 angstroms. Then, for example,
Ni/Au followed by Ge/Au is vaporised onto the first and second regions 11 and 12 thereby to form ohmic contacts which become emitter and collector electrodes 14 and 15. Ti is followed by Pt is followed by Au is vaporised on the third region 13 to form a base electrode 16.References E, C and B respectively designate terminals for the emitter, collector and base.
Then, a forward bias voltage is applied between the first and third regions 11 and 13, while a reverse bias voltage is applied between the third and second regions 13 and 12. Then, holes as the majority carrier are injected from the third region 13 into a high resistance region 17 defined in the semiinsulating semiconductor layer 10 between the first and second regions 11 and 12 and beneath the third region 13, so that a virtual base region 18 is established therein. Thus, the injection of electrons as the majority carrier into the first region 11 is promoted and they are fed through the virtual base region 18 to the the third region 13. Therefore, this semiconductor device is operated as a bipolar transistor of n-p-n type having a lateral structure.
The virtual base region 18 is mainly generated in the portion in which the carriers from the first and second regions 11 and 12 are injected into the region 17 efficiently, namely, the portion beneath the third region 13.
In the example shown in Fig. 2, the regions 11 to 13 are respectively located separately with a predetermined distance therebetween.
It is possible that as shown in Fig. 3, the third region 13 is formed to bridge the first and second regions 11 and 12. In this case, there is then an advantage that the distance between the first and second regions 11 and 12, namely, the base width Wb can be reduced. In Fig. 3, like parts corresponding to those in Fig. 2 are marked with the same references and will not be further described.
While in the above embodiments the first to third regions 11 to 13 are formed by an ion implantation technique or a diffusion technique, they can be formed by an alloying technique as shown in Fig, 4. Alternatively, in order that the depth of the first and second regions 11 and 12 becomes deeper than that of the third region 13, it is possible that as shown in Fig. 4, concave portions 19 and 20 are respectively formed on the surface 1 0a of the semiconductor layer 10 at the positions where the first and second regions 11 and 12 are to be formed, and then the first and second regions 11 and 12 are formed within these concave portions 19 and 20 by an alloying technique, a diffusion technique, or an ion implantation technique.
With the embodiments of semiconductor device described above, since the semiconductor devices are formed as a lateral structure, it is easy to form their electrodes and to carry out the wiring thereof, which is advantageous for constructing an integrated circuit.
Moreover, since the respective regions 11, 12 and 13 can be formed by the same process as that for forming the respective regions 4, 5 and 3 in the J-FET described in connection with, for example, Fig. 1, it is possible to manufacture the semiconductor without special working processes. This is very advantageous when applied to an integrated circuit.
Although the semiconductor device is formed as a lateral structure, there is the advantage that its current amplification factor can be increased. To be more specific, since the substantial base region, namely, the current path formed by the carrier injection is formed within the semi-insulating region, except for the third region 13 having high impurity concentration, namely, within the region 17 having low impurity concetration, the diffusion length of the injected carriers is extremely long. Also the injected carriers are little affected by the portion of the semiconductor surface having a large recombination rate. Moreover, the injected carriers do not flow through the third region 13, but flow through the portion of the semi-insulating region 17 whose potential barrier is low and flat, and is little influenced by the collector voltage. Thus the semiconductor device can be operated as a bipolar transistor having a high current amplification factor.
Particularly when the semiconductor device is formed of a compound semiconductor, it is possible to obtain a semiconductor device which is superior in high-speed operation.
Since the substantial base region is formed within the semi-insulating semiconductor, the above characteristic is little affected by the depth of the third region 13, or by scatter.
Thus, it is easy to manufacture a semiconductor device whose characteristics are stable and uniform.
Since the first and second regions 11 and 12 are symmetrical with respect to the third region it is possible to make a transistor whose emitter and collector have symmetry.
Reffering to Fig. 5, another embodiment of this invention will be described in which regions for suppressing the injection of carriers are formed on the surface of a semi-insulating semicondictor substrate between the third and first regions and between the third and second regions.
In Fig. 5, on the major surface 1 0a of the semi-insulating semi-conductor substrate or layer 10 at positions between the third region 13 and the first region 11 and between the third region 13 and the second region 12, there is formed a region 19, which suppresses the injection of carriers from each region, and has a smaller depth than those of the first and second regions 11 and 12.
On the major surface 1 0a of the semiconductor substrate or layer 10, these regions 19 are extendedly formed so as to lie across the portions which are opposed to each other, namely, confronting each other between the region 13 and the region 11 and between the region 13 and the region 12. As, for example, shown in Fig. 5, the regions 19 are formed such that the portions in contact with the respective regions 11 and 13, and 13 and 12 are selectively ion-implanted with boron ions B or protons H + . The regions 19 are then insulated, or portions are removed by selective etching, or concave portions are formed by a selective etching technique.Buried Al GaAs semiconductor, for example, which has a large energy gap as compared with the GaAs semiconductor layer 10 may be provided by a selective epitaxial growth technique.
In the semiconductor device with such a structure, if a forward bias voltage is applied between the first and third regions 11 and 13 and a reverse bias voltage is applied between the third and second regions 13 and 12, holes forming the majority carriers from the third region 13 are injected into the high resistance region 17 made of the semi-insulating semiconductor layer 10 between the first and second regions 11 and 12 and beneath the third region 13 at which the virtual base region 18 is generated. Thus, the injection of electrons as the majority carriers from the first region 11 thereto is promoted and the electrons then reach through the virtual base region 18 to the third region 13. Thus the semiconductor device of this embodiment can be operated as a bipolar transistor of n-p-n type having a lateral structure.
In this case, since at the surface side of the region 17 are formed the insilation layers of the regions 19 having the large gap as compared with the region 17, and into which the injection of carriers is not made or is difficult, the virtual base region 18 is not formed on this surface side but is formed in the portion beneath the third region 13 through which the first and second regions 11 and 12 are opposed to each other.
While in the embodiment shown in Fig. 5 the first to third regions 1 1 to 1 3 are selec- tively formed on the surface of the GaAs semiinsulating semiconductor layer or semiconductor substrate 10, namely, on one major surface 1 ova, and the injection suppression region 19 is provided, the following version is also possible. As shown in Fig. 6, an AlGaAs semiconductor layer 20 of, for example, ptype which will form the third region 13 is epitaxially grown on the GaAs semiconductor substrate or layer 10. Then, the first and second regions 11 and 12 are selectively formed such that they extend in the thickness direction of the layer 20 and have a depth ranging from the surface of the layer 20 to the semi-insulating semiconductor substrate or layer 10 by an ion implantation technique or a diffusion technique.Also surrounding the peripheral edges of the surfaces of the regions 11 and 12, insulatiopn layers are formed with a depth crossing the layer 20, by the implantation of boron ions B+ or protons H + to form the injection suppression region 19.
Alternatively, as shown in Fig. 7 on the semi-insulating semi-conductor substrate or layer 10 is grown a like AlGaAs layer 21 with semi-insulation properties whose energy gap is larger than that of the layer 10. Then, the first to third regions 11 to 13 are selectively formed and the injection suppression regions 19 can be made of the AlGaAs layer 21. In this case, since the boundary surface or junction between the GaAs semiconductor layer or substrate 10 and the Al GaAs epitaxial semiconductor layer 21 is formed as a continuous and clean surface in view of crystallography, it is possible to avoid the recombination of carriers on the boundary surface from being increased.
In Figs. 6 and 7, like parts corresponding to those of Fig. 5 are marked with the same references and will not be further described.
While in the above examples of Figs. 5 to 7, the first to third regions 11 to 13 are formed by an ion implantation technique or a diffusion technique, they can be formed by an alloying technique. Alternatively, in order that the depth of the first and second regions 11 and 12 becomes deeper than that of the third region 13, the concave portions are respectively formed at the portions of the layer 10 where the first and second regions 11 and 12 are to be formed, and the first and second regions 11 and 12 are respectively formed in these concave portions by an alloying technique, a diffusion technique or an ion implan tation technique.
Since the semiconductor device is formed with a lateral structure, it is easy to form the electrodes and to carry out the wiring thereof, which is advantageous for constructing an integrated circuit. Moreover, since the respective regions 11, 12 and 13 can be formed by the same process as that for forming the respective regions 4, 5 and 3 in the J-FET described in connection with, for example,
Fig. 1, it is possible to manufacture the semiconductor device without special working processes. This is very advantageous for making an integrated circuit.
Although a semiconductor device is formed with a lateral structure, there is an advantage that its current amplification factoe ss can be increased. To be more specific, since the base region, namely, the current path formed by carrier injection is formed within the semiinsulating region except the third region 13 having a high impurity concentration, namely, the region 17 having a low impurity concentration, the diffusion length of the injected carriers is extremely long. Moreover, in the embodiments shown in Figs. 5 to 7, the injection suppression region 19 is provided on the surface of the semiconductor so as to form the virtual base region 18 at the position remote from the surface, so that it is possible to avoid the collector current which will flow through the third region 13.Also this semiconductor device is little affected by the portion of the semiconductor surface having a large recombination rate. Moreover, the collector current does not flow through the third region 13 but flows through the portion of the semi-insulating region 17 whose potential barrier is low and flat, and which substantially unaffected by the collector voltage. Thus the semiconductor device can be operated as a bipolar transistor having a high current amplification factor.
Particularly when the semiconductor device is formed of a compound semiconductor, it is possible to obtain a semiconductor device which is superior in high-speed operation.
Since the substantial base region is formed within the semi-insulating semiconductor the above characteristic is little affected by the depth of the third region 13 and scatter.
Thus, it is easy to produce a semiconductor device whose characteristics are stable and uniform.
Since the first and second regions 11 and 12 are symmetrical with respect to the third region 13, it is possible to made a transistor whose emitter and collector have symmetry.
Referring to Figs. 8 to 11, to facilitate the understanding of the semiconductor device according to this invention, a further embodiment of this invention will be described together with an example of its manufacture.
As shown in Fig. 8, there is provided, for example, a GaAs Ill-V compound semiconductor substrate or semi-insulating semiconductor layer 110 which is not substantially doped with impurity and hence which presents high resistance. Formed in one major surface 1 1 ova of the semiconductor layer 110 is a semiconductor layer 111 made of, for example, AlGaAs in which P-type impurity is doped with high concentration by, for example, metal organic chemical vapour deposition. Selectively deposited on this semiconductor layer 111 in ohmic contact therewith is a base electrode 11 2 made of a metal layer with heat-resisting properties which has a predetermined width W.
Then, while the electrode 112, for example, is used as the etching resist, the semiconductor layer 111 is etched to remove the portions of the semiconductor layer 111 at both sides of the electrode 112 which are then exposed as shown in Fig. 9.
Subsequently, as shown in Fig. 10, while at least the electrode 112 is used as the mask, impurity of different conductivity type from that of the semicondictor layer 111, for example, N-type is introduced into the semiconductor substrate 110 from the side of its major surface 1 1 ova by an ion implantation technique or a diffusion technique to form first and second regions 11 3 and 114 in which at least the positions of the edge portions thereof facing to each other are matched to have a predetermined positional relative to the edge portions of the electrode 112 and the semiconductor layer 111 therebeneath.
Namely, these edge portions are coincident with one another or the regions 11 3 and 114 are restricted such that they enter into the underside of the semiconductor layer 111 with a predetermined width. In this case, in order that the positions of these regions 11 3 and 114 which are opposed to each other are automatically matched, or so-called selfaligned, to have the predetermined positional relation with the electrode 112 and the semiconductor layer 111 formed therebeneath, the electrode 112 which is used as the mask upon selective etching process of the semiconductor layer 111 is also employed as the mask.
Then, emitter and collector electrodes 115 and 116 are deposited on the first and second regions 1 13 and 1 14 in ohmic contact therewith, as shown in Fig. 11.
The semiconductor device thus made has a structure in which the third region formed of the semiconductor layer 111 made of, for example, P-type having high impurity concentration is formed on the semiconductor substrate 110 between the first and second regions 11 3 and 114 of high impurity concentration which will become emitter and collector regions respectively. In Fig. 11, references
E, C and B respectively designate terminals for the emitter, collector and base.
In the semiconductor device with such a structure, a forward bias voltage is applied between the first and third regions 113 and
111 and a reverse bias voltage is applied between the third and second regions 111 and 114, the holes as the majority carriers from the third region 111 are then injected into the high resistance region 117 made of the semi-insulating semiconductor 100 at the position between the first and second regions 11 3 and 114 and beneath the third region
111 (Fig. 11) at which the virtual base region is generated. Thus, the injection of the electrons as the majority carriers from the first region 113 is promoted and the majority carriers reach through the virtual base region to the second region 114. Thus the semiconductor device can be operated as a bipolar transistor of N-P-N type.
While in the above embodiment the first and second regions 11 3 and 114 are respectively formed by an ion implantation technique or a diffusion technique, these regions 11 3 and 114 can be formed by an alloying technique.
The semiconductor device is formed as a lateral structure in which the respective regions 111, 113 and 114 are disposed sepa- rately. As a result, it is easy to form the electrodes thereof and to carry out the wiring thereof, which fact is advantageous for constructing an integrated circuit.
Although the semiconductor device is formed as a lateral structure, there is the advantage that its current amplification factor can be increased. To be more specific, since the substantial base region, namely, the current path formed by the carrier injection is formed within the semi-insulating region, except for the third region 111 having the high impurity concentration, namely, within the region 117 having low impurity concentration, the diffusion length of the injected carrier is extremely long.
Moreover, the current flows through the portion of the semi-insulating region 11 7 whose potential barrier is low and flat and is little affected by the collector voltage, and so this semiconductor device can be operated as a bipolar transistor having a high current amplification factor and a high speed of operation. Since the substantial base region is formed within the semi-insulating semiconductor, the above characteristic is little affected by the depth of the third region 111 and scatter of characteristics. Thus, it is easy to produce a semiconductor device whose characteristics are stable and uniform.
Since the first and second regions 113 and 11 4 are symmetrical with respect to the third region 111, it is possible to make a transistor whose emitter and collector have symmetry.
Since this semiconductor device is constructed as the semi-insulating semiconductor device, when applied to an integrated circuit, it is possible to simplify the isolation between the elements thereof.
Claims (10)
1. A semiconductor device comprising:
a semi-insulating semiconductor;
a first region of a first conductivity type which becomes an emitter region;
a second region of the first conductivity type which becomes a collector region, said first and second regions being formed on said semi-insulating semiconductor with a predetermined distance therebetween; and
a third region of a second conductivity type formed on said semiconductor between said first and second regions;
wherein a forward bias voltage is applied between said third and first regions so as to form a virtual base region in a portion of said semi-insulating semiconductor beneath said third region by injected majority carriers from said third region, so that said semiconductor device can be operated as a bipolar transistor.
2. A semiconductor device according to claim 1 further comprising a region formed on the surface of said semi-insulating semiconductor between said third and first regions for suppressing the injection of said carriers.
3. A semiconductor device comprising:
a semi-insulating semiconductor;
a first region of a first conductivity type which becomes an emitter region;
a second region of the first conductivity type which becomes a collector region, said first and second regions being formed on said semi-insulating semiconductor with a predetermined distance therebetween; and
a third region made of an epitaxial layer of a second conductivity type selectively formed on said semiconductor between said first and second regions;
wherein a forward bias voltage is applied between said third and first regions so as to form a virtual base region in a portion of said semi-insulating semiconductor beneath said third region by injected majority cariers from said third region, so that said semiconductor device can be operated as a bipolar transistor.
4. A semiconductor device substantially as hereinbefore described with reference to Fig.
2 of the accompanying drawings.
5. A semiconductor devoce substantially as hereinbefore described with reference to
Fig. 3 of the accompanying drawings.
6. A semiconductor device substantially as hereinbefore described with reference to Fig.
4 of the accompanying drawings.
7. A semiconductor device substantially as hereinbefore described with reference to Fig.
5 of the accompanying drawings.
8. A semiconductor device substantially as hereinbefore described with reference to Fig.
6 of the accompanying drawings.
9. A semiconductor device substantially as hereinbefore described with reference to Fig.
70f the accompanying drawings.
10. A semiconductor device substantially as hereinbefore described with reference to
Figs. 8 to 11 of the accompanying drawings.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22484183A JPS60116170A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
| JP22484283A JPS60116171A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
| JP22484383A JPS60116172A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8430033D0 GB8430033D0 (en) | 1985-01-09 |
| GB2151078A true GB2151078A (en) | 1985-07-10 |
| GB2151078B GB2151078B (en) | 1987-09-23 |
Family
ID=27330963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08430033A Expired GB2151078B (en) | 1983-11-29 | 1984-11-28 | Semiconductor devices |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE3443407A1 (en) |
| FR (1) | FR2555814B1 (en) |
| GB (1) | GB2151078B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112014004818B4 (en) * | 2013-10-21 | 2020-02-13 | Toyota Jidosha Kabushiki Kaisha | Bipolar transistor |
| DE112014004821B4 (en) * | 2013-10-21 | 2020-02-13 | Toyota Jidosha Kabushiki Kaisha | Bipolar transistor |
| EP2954557B1 (en) * | 2013-02-07 | 2021-03-31 | John Wood | A bipolar junction transistor structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6174369A (en) * | 1984-09-20 | 1986-04-16 | Sony Corp | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BE792639A (en) * | 1971-12-17 | 1973-03-30 | Ibm | LIMITED SPACE LOAD TRANSISTOR |
-
1984
- 1984-11-28 GB GB08430033A patent/GB2151078B/en not_active Expired
- 1984-11-28 DE DE19843443407 patent/DE3443407A1/en not_active Withdrawn
- 1984-11-29 FR FR8418222A patent/FR2555814B1/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2954557B1 (en) * | 2013-02-07 | 2021-03-31 | John Wood | A bipolar junction transistor structure |
| DE112014004818B4 (en) * | 2013-10-21 | 2020-02-13 | Toyota Jidosha Kabushiki Kaisha | Bipolar transistor |
| DE112014004821B4 (en) * | 2013-10-21 | 2020-02-13 | Toyota Jidosha Kabushiki Kaisha | Bipolar transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3443407A1 (en) | 1985-06-27 |
| GB2151078B (en) | 1987-09-23 |
| GB8430033D0 (en) | 1985-01-09 |
| FR2555814A1 (en) | 1985-05-31 |
| FR2555814B1 (en) | 1987-08-28 |
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| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19961128 |