JPS6318337B2 - - Google Patents
Info
- Publication number
- JPS6318337B2 JPS6318337B2 JP52146268A JP14626877A JPS6318337B2 JP S6318337 B2 JPS6318337 B2 JP S6318337B2 JP 52146268 A JP52146268 A JP 52146268A JP 14626877 A JP14626877 A JP 14626877A JP S6318337 B2 JPS6318337 B2 JP S6318337B2
- Authority
- JP
- Japan
- Prior art keywords
- input protection
- diffusion layer
- input
- semiconductor substrate
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009792 diffusion process Methods 0.000 claims description 35
- 239000004065 semiconductor Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 18
- 230000000295 complement effect Effects 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000012535 impurity Substances 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Amplifiers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、相補型半導体装置の入力保護装置に
関し、特に外部入力から半導体基板に対して順方
向電圧が加わつた場合、ラツチアツプに対して強
い保護能力を有する相補型半導体装置の入力保護
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input protection device for a complementary semiconductor device, and in particular, the present invention relates to an input protection device for a complementary semiconductor device that has a strong protection ability against latch-up when a forward voltage is applied from an external input to a semiconductor substrate. This invention relates to an input protection device for a device.
一般に、相補型電界効果半導体装置（以下Ｃ−
MOSTと略記する。）の入力保護装置は、第１図
の如く構成される。第１図はＮ型半導体基板を用
いた時の図である。この入力保護装置は、外部入
力からＮ型半導体基板電圧に対して負電圧が入力
電極６に加わつた場合、P+不純物拡散層２とＮ
型半導体基板１の接合における逆耐圧でブレーク
ダウンを起こさせたり、又、拡散層を長くして、
次段のゲートに対して抵抗を有する様にして、時
定数を大きくし、次段のゲート破壊に対して保護
の役割をしている。ただし、６′は次段のゲート
に接続されている。又、逆に外部入力から正電圧
が加わつた場合、P+不純物拡散層２とＮ型半導
体基板１の順方向特性で、電流をＮ型半導体基板
１に流して、次段のゲート破壊を保護している。
がしかし、正電圧が加わつた場合、Ｃ−MOST
構造の為にP+不純物拡散層２、Ｎ型半導体基板
１とP-ウエル拡散層４で横型P+NP-トランジス
タが構成される。この横型トランジスタが構成さ
れる為、入力から加わつた順方向電流のα倍が
P-ウエル拡散層４へ流れ込む。αは横型トラン
ジスタの電流増率である。このP-ウエル拡散層
４へ流れ出す電流がトリガーとなつてＣ−
MOST特有のラツチアツプが発生し、入力及び
電源から過大電流が流れ、Ｃ−MOSTが破壊さ
れるなどの欠点があつた。又、αはP+不純物拡
散層２からP-ウエル拡散層４までの距離を長く
すれば、ラツチアツプは発生しにくくなるが、こ
れはチツプ面積の増加を招くなどの欠点があつ
た。 Generally, complementary field effect semiconductor devices (hereinafter referred to as C-
Abbreviated as MOST. ) is constructed as shown in FIG. FIG. 1 is a diagram when an N-type semiconductor substrate is used. In this input protection device, when a negative voltage with respect to the N-type semiconductor substrate voltage is applied to the input electrode 6 from an external input, the P + impurity diffusion layer 2
By causing breakdown due to the reverse breakdown voltage at the junction of the type semiconductor substrate 1, or by lengthening the diffusion layer,
It has resistance to the gate of the next stage, increases the time constant, and serves to protect the gate of the next stage from destruction. However, 6' is connected to the gate of the next stage. Conversely, when a positive voltage is applied from an external input, the forward characteristics of the P + impurity diffusion layer 2 and the N-type semiconductor substrate 1 allow current to flow through the N-type semiconductor substrate 1 to protect the gate from destruction in the next stage. are doing.
However, if a positive voltage is applied, C-MOST
Due to its structure, a lateral P + NP -transistor is composed of a P + impurity diffusion layer 2, an N type semiconductor substrate 1 and a P - well diffusion layer 4. Since this horizontal transistor is configured, α times the forward current applied from the input is
Flows into the P - well diffusion layer 4. α is the current increase rate of the lateral transistor. This current flowing into the P - well diffusion layer 4 acts as a trigger for C-
There were drawbacks such as a latch-up peculiar to MOSTs, excessive current flowing from the input and power supply, and destruction of the C-MOST. Furthermore, if α increases the distance from the P + impurity diffusion layer 2 to the P - well diffusion layer 4, latch-up will be less likely to occur, but this has the disadvantage of increasing the chip area.
本発明は、上記諸欠点を除き、入力から順方向
電圧が加わつても、容易にラツチアツプが発生せ
ず、Ｃ−MOSTが破壊されない相補型半導体装
置の入力保護装置を提供するものである。 The present invention provides an input protection device for a complementary semiconductor device which eliminates the above-mentioned drawbacks and which does not easily latch up or destroy the C-MOST even if a forward voltage is applied from the input.
本発明の相補型半導体装置の入力保護装置は、
第１導電型半導体基板に、第２導電型の入力保護
の拡散層を設け、該拡散層の周囲を、第２導電型
で該拡散層よりも深い拡散属領域で囲み、深い拡
散層と第１導電型半導体基板を電気的に接続する
事を特徴とする。 The input protection device for a complementary semiconductor device of the present invention includes:
A first conductivity type semiconductor substrate is provided with a second conductivity type input protection diffusion layer, the diffusion layer is surrounded by a second conductivity type diffusion region deeper than the diffusion layer, and the deep diffusion layer and the second conductivity type input protection diffusion layer are provided. It is characterized by electrically connecting two conductive type semiconductor substrates.
次に本発明の１実施例を図面を用いて詳細に説
明する。 Next, one embodiment of the present invention will be described in detail using the drawings.
第２図に示すように通常のＣ−MOSTの製造
に用いられる写真蝕刻および熱拡散又はイオン注
入技術に基づき、Ｎ型半導体基板１にＮチヤンネ
ルMOSトランジスタを形成する為のP-−ウエル
拡散層４ａと本発明入力保護装置に特長的なP-
−ウエル拡散層４ｂを同時に形成する。同時に形
成するのは、写真蝕刻の回数を増やすことなく
P+不純物拡散層２よりも深い拡散層４ｂが得ら
れるからであり、拡散層４ｂは別工程で形成して
もよい。次にＮ型半導体基板表面の寄生MOSト
ランジスタを無くし、ＮチヤンネルMOSトラン
ジスタのソースおよびドレインを形成する目的で
N+不純物拡散層３を設け、次に入力保護ダイオ
ード又は抵抗としての入力保護拡散層２を形成す
るとともに、P-−ウエル表面の寄生MOSトラン
ジスタを無くし、ＰチヤンネルMOSトランジス
タのソース及びドレインを形成する目的でP+不
純物拡散層２′を設ける。その後Ｐチヤンネルお
よびＮチヤンネルMOSトランジスタの必要な領
域にゲート酸化膜を設け、さらにコンタクト５を
設け、アルミ蒸着後、写真蝕刻を用いてパターン
ニングしてアルミニウム電極６，６′および６″を
設け本発明の相補型半導体入力保護装置ができ
る。ただし、６は入力電極、６′は次段のゲート
に接続される電極、６″は接地用金属電極である。 As shown in FIG. 2, a P -- well diffusion layer is used to form an N-channel MOS transistor in an N-type semiconductor substrate 1 based on photolithography and thermal diffusion or ion implantation techniques used in the production of ordinary C-MOSTs. 4a and the P- characteristic of the input protection device of the present invention.
- Form the well diffusion layer 4b at the same time. At the same time, it is possible to form without increasing the number of photo engravings.
This is because a diffusion layer 4b deeper than the P + impurity diffusion layer 2 can be obtained, and the diffusion layer 4b may be formed in a separate process. Next, for the purpose of eliminating the parasitic MOS transistor on the surface of the N-type semiconductor substrate and forming the source and drain of the N-channel MOS transistor.
An N + impurity diffusion layer 3 is provided, and then an input protection diffusion layer 2 as an input protection diode or resistor is formed, and the parasitic MOS transistor on the P - - well surface is eliminated, and the source and drain of the P channel MOS transistor are formed. For this purpose, a P + impurity diffusion layer 2' is provided. After that, a gate oxide film is formed in the necessary areas of the P-channel and N-channel MOS transistors, and contacts 5 are formed. After aluminum evaporation, patterning is performed using photolithography to form aluminum electrodes 6, 6', and 6''. A complementary semiconductor input protection device of the invention is obtained.However, 6 is an input electrode, 6' is an electrode connected to the gate of the next stage, and 6'' is a grounding metal electrode.
本発明の相補型半導体装置の入力保護装置を用
いると、第２図に示す様にP+不純物拡散層２又
は２′よりも深く拡散されたP-−ウエル拡散層４
ｂが入力保護拡散層２とP-−ウエル拡散層４ａ
の間に形成してある為、入力保護拡散層２からの
順方向電流は、Ｎ型半導体基板１、P-−ウエル
拡散層４ｂに殆んど流れて、P-−ウエル拡散層
４ａには流れなくなる。この様に従来の構造では
入力保護装置の横型PNPトランジスタのαが大
きかつたが、本発明の構造ではαが小さくなり、
ラツチアツプに対するトリガーが発生せずラツチ
アツプが起こりにくくなる効果がある。又、この
P-−ウエル４ｂは、入力保護拡散層５とP-−ウ
エル４ｂは、入力保護拡散層２とP-−ウエル拡
散層４ａの間に設けるだけでも効果はあるが、入
力保護拡散層２の全周囲を囲む様にすれば、さら
に効果は大きくなる。 When the input protection device of the complementary semiconductor device of the present invention is used, as shown in FIG.
b is the input protection diffusion layer 2 and the P - -well diffusion layer 4a
Since the input protection diffusion layer 2 is formed between It stops flowing. In this way, in the conventional structure, α of the lateral PNP transistor of the input protection device was large, but in the structure of the present invention, α is small,
This has the effect of making it less likely that a latch-up will occur because a trigger for the latch-up will not occur. Also, this
Although it is effective to provide the input protection diffusion layer 5 and the P - -well 4b between the input protection diffusion layer 2 and the P - -well diffusion layer 4a, If you surround it all around, the effect will be even greater.
上記実施例はＮ型半導体基板を使つて説明した
が、Ｐ型半導体基板を使つても、同様に実施でき
ることは勿論である。 Although the above embodiment has been explained using an N-type semiconductor substrate, it goes without saying that it can be similarly implemented using a P-type semiconductor substrate.
以上詳細に説明した様に、本発明によれば、入
力から順方向電流が流れても、容易にラツチアツ
プを起こさないＣ−MOSTが得られる。 As described in detail above, according to the present invention, a C-MOST that does not easily latch up even if a forward current flows from the input can be obtained.
第１図ａおよびｂは従来の相補型半導体装置の
入力保護装置のそれぞれ平面図およびＡ−A′方
向の断面図。第２図ａおよびｂは、本発明の相補
型半導体装置の入力保護装置の一実施例のそれぞ
れ平面図およびＢ−B′方向の断面図である。
１……Ｎ型半導体基板、２……入力保護P+不
純物拡散層、２′……P+不純物拡散層、３……
N+型不純物拡散層、４ａ，４ｂ……P-−ウエル
拡散層、５……コンタクト、６，６′……アルミ
ニウム電極、６″……接地用金属電極。
FIGS. 1a and 1b are a plan view and a sectional view taken along the line A-A', respectively, of a conventional input protection device for a complementary semiconductor device. FIGS. 2a and 2b are a plan view and a sectional view taken along the line B-B', respectively, of an embodiment of the input protection device for a complementary semiconductor device according to the present invention. 1... N-type semiconductor substrate, 2... Input protection P + impurity diffusion layer, 2'... P + impurity diffusion layer, 3...
N + type impurity diffusion layer, 4a, 4b...P -- well diffusion layer, 5...Contact, 6, 6'...Aluminum electrode, 6''...Grounding metal electrode.
Claims (1)
に形成された第２導電型のウエル領域にそれぞれ
異なる導電型の電界効果トランジスタを有し、入
力電極と前記電界効果トランジスタのそれぞれの
ゲート電極との間の前記半導体基板に設けられ、
一端に前記入力電極が他端に前記ゲート電極が
夫々接続された前記第２導電型の入力保護層を有
する相補型半導体装置の入力保護装置において、
前記入力保護層の全周を取り囲む前記第１導電型
の高濃度拡散層を貫通し、かつ前記入力保護層の
全周を囲んで前記入力保護層より深く前記ウエル
領域と同じ深さに形成された前記第２導電型の環
状領域を有し、該環状領域は前記半導体基板と電
気的に接続されていることを特徴とする相補型半
導体装置の入力保護装置。1 Field effect transistors of different conductivity types are provided in a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed in the semiconductor substrate, and an input electrode and a gate electrode of each of the field effect transistors are connected to each other. provided on the semiconductor substrate between;
In an input protection device for a complementary semiconductor device, the input protection layer has the second conductivity type input protection layer connected to the input electrode at one end and the gate electrode at the other end,
penetrating the first conductivity type high concentration diffusion layer surrounding the entire periphery of the input protection layer, and surrounding the entire periphery of the input protection layer to be deeper than the input protection layer and at the same depth as the well region. An input protection device for a complementary semiconductor device, comprising: an annular region of the second conductivity type, the annular region being electrically connected to the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14626877A JPS5478674A (en) | 1977-12-05 | 1977-12-05 | Input protective device for complementary semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14626877A JPS5478674A (en) | 1977-12-05 | 1977-12-05 | Input protective device for complementary semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5478674A JPS5478674A (en) | 1979-06-22 |
| JPS6318337B2 true JPS6318337B2 (en) | 1988-04-18 |
Family
ID=15403886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14626877A Granted JPS5478674A (en) | 1977-12-05 | 1977-12-05 | Input protective device for complementary semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5478674A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56120165A (en) * | 1980-02-28 | 1981-09-21 | Nec Corp | Protecting device for input of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5098791A (en) * | 1973-12-27 | 1975-08-06 | ||
| JPS5238890A (en) * | 1975-09-23 | 1977-03-25 | Mitsubishi Electric Corp | Semiconductor device |
-
1977
- 1977-12-05 JP JP14626877A patent/JPS5478674A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5098791A (en) * | 1973-12-27 | 1975-08-06 | ||
| JPS5238890A (en) * | 1975-09-23 | 1977-03-25 | Mitsubishi Electric Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5478674A (en) | 1979-06-22 |
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