JPS63181436A - Circuit device - Google Patents

Circuit device

Info

Publication number
JPS63181436A
JPS63181436A JP62014709A JP1470987A JPS63181436A JP S63181436 A JPS63181436 A JP S63181436A JP 62014709 A JP62014709 A JP 62014709A JP 1470987 A JP1470987 A JP 1470987A JP S63181436 A JPS63181436 A JP S63181436A
Authority
JP
Japan
Prior art keywords
copper foil
copper
areas
chip
foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62014709A
Other languages
Japanese (ja)
Inventor
Norio Koutou
杭東　詔夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP62014709A priority Critical patent/JPS63181436A/en
Publication of JPS63181436A publication Critical patent/JPS63181436A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Abstract

PURPOSE:To make copper hard to deform due to thermal expansion and contraction and to reduce the thermal deformation of a chip by a method wherein a metal electrode on a substrate is divided into two or more regions and the single chip is placed on two or more divided fine regions. CONSTITUTION:In order to glue an LSI silicon chip 3 of, e.g., 8 mm X 8 mm onto a copper-foil laminated plate which is formed by bonding a sheet of copper foil 2 to a glass-epoxy laminated plate 1, each area of the copper foil on the plate is decided to be 2 mm X 2 mm and the space between the areas composed of the copper foil is decided to be, e.g., 1 mm; electrodes are formed in such a way that the areas of the copper foil 2 are formed in a matrix form composed of three lines in the vertical direction and three rows in the transverse direction. A silver paste 4 is dropped onto the areas of the copper foil 2 by using a dispenser. For this process, the tip of the dispenser is to be equipped with nine nozzles so that an appropriate amount of paste can be dropped onto nine areas of the copper foil 2. After that, a silicon chip 3 is held by means of a collet and is glued after an appropriate pressure has been applied. After that, the silver paste 4 is hardened at 150 deg.C for 1 hr.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、プリント基板上に電気回路を構成する単体部
品（以下、チップと呼ぶ）を載置する回路装置に関する
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a circuit device in which a single component (hereinafter referred to as a chip) constituting an electric circuit is mounted on a printed circuit board.

従来の技術 従来、樹脂を基板としだ銅張積層板のプリント基板では
、銅箔をエツチングして必要パターンのみ残して電極お
よび回路配線構成を行なっている。ＩＣ等の半導体チッ
プを接着する時、樹脂基板上の銅の電極部に、銀ペース
トの接着剤あるいは、鉛、錫系のはんだで接着していた
。2. Description of the Related Art Conventionally, in printed circuit boards made of copper-clad laminates using resin as substrates, electrodes and circuit wiring are constructed by etching the copper foil to leave only the necessary patterns. When bonding semiconductor chips such as ICs, they are bonded to copper electrodes on resin substrates using silver paste adhesive or lead or tin-based solder.

発明が解決しようとする問題点 たとえば、プリント基板上にシリコンチップを接着した
状態では、シリコン、銅電極および樹脂基板の３層構造
になり、３者それぞれ熱膨張係数が異なり、中でも銅が
最も熱膨張係数が大きい。Problems to be Solved by the Invention For example, when a silicon chip is bonded to a printed circuit board, it has a three-layer structure of silicon, copper electrodes, and a resin substrate, and each of the three has a different coefficient of thermal expansion, with copper having the highest thermal expansion coefficient. Large expansion coefficient.

シリコンチップ裏面全面に銅の電極が存在すると、シリ
コンチップ接着後にシリコンにそりが生じ、特性面、信
頼性面に問題が生じる。If a copper electrode is present on the entire back surface of the silicon chip, warpage will occur in the silicon after the silicon chip is bonded, causing problems in terms of characteristics and reliability.

また、銅の電極を小さくして、シリコンチップの真中部
分のみ接着しようとすると、熱放散が悪くなると同時・
に、シリコンチップが傾いて接着されたりして、安定し
た接着が得られなかった。Also, if you try to make the copper electrode smaller and only bond it to the middle part of the silicon chip, heat dissipation will deteriorate and at the same time,
Also, the silicon chip was sometimes glued at an angle, making it impossible to obtain stable adhesion.

問題点を解決するための手段 本発明は、基板上の金属電極を複数領域に分割し、その
分割された微小な複数領域にまたがって、単一体のチッ
プを載置できるようにしたものである。Means for Solving the Problems In the present invention, a metal electrode on a substrate is divided into a plurality of regions, and a single chip can be placed across the plurality of divided micro regions. .

作用 金属電極がチップの一面に存在すると、その電極の熱膨
張、収縮の影響がチップ全面に及ぶが、本発明によると
、電極を小さく分割されたことにより、熱膨張、収縮の
影響はチップ面に対して局部的に起り、電極のない部分
は、その影響を受けないため、チップ全面にうける熱膨
張、収縮は少本発明を、第１図の電極パターン平面図、
第２図の断面図を参照して、実施例により説明する。When a working metal electrode exists on one surface of a chip, the influence of thermal expansion and contraction of the electrode affects the entire surface of the chip. However, according to the present invention, since the electrode is divided into small pieces, the influence of thermal expansion and contraction is limited to the entire surface of the chip. The thermal expansion and contraction that occur over the entire surface of the chip are small because the areas without electrodes are not affected by the thermal expansion and contraction.
An example will be described with reference to the sectional view of FIG.

１　、６　＋ｎ＋ｎ　ｔのガラスエポキシ積層板１に３
５μ−の銅箔２を張った鋼張積層板に、８　ｍ　Ｘ　８
　ｗａのＬＳＩのシリコンチップ３を接着するため、基
板の鋼箔の面積を２　ｍ　Ｘ　２　ｍとし、鋼箔と鋼箔
間距離をＩＩｓとして縦３列、横３列のマトリックス状
に８箔２を残して電極とした。この電極の鋼箔２上に、
銀ペースト４をディスペンサーによって、滴下した。こ
の時のディスペンサーの先端のノズルは９点式とし、銅
箔２の上に９か所適量滴下するようにした。その後シリ
コンチップ３をコレットでつかみ、適当量加在して接着
した。しかる後、１５０℃１時間銀ペースト４を硬化し
た。1, 6 +n+nt glass epoxy laminate 1 to 3
8 m x 8 on a steel clad laminate covered with 5μ copper foil 2
In order to bond the silicon chip 3 of the wa LSI, the area of the steel foil on the board was 2 m x 2 m, and the distance between the steel foils was IIs, and 8 foils 2 were placed in a matrix of 3 vertical rows and 3 horizontal rows. This was left behind to serve as an electrode. On the steel foil 2 of this electrode,
Silver paste 4 was dropped by a dispenser. At this time, the nozzle at the tip of the dispenser was a 9-point type, and an appropriate amount was dropped onto the copper foil 2 at 9 locations. Thereafter, the silicon chip 3 was grasped with a collet, and an appropriate amount was added and bonded. Thereafter, silver paste 4 was cured at 150° C. for 1 hour.

発明の効果 本発明によれば、チップ面が、銅電極を分割することに
よって、鋼の熱膨張、収縮による歪がうけにくくなり、
したがってチップの熱歪が小さくなる。Effects of the Invention According to the present invention, by dividing the copper electrode, the chip surface becomes less susceptible to distortion due to thermal expansion and contraction of steel.
Therefore, the thermal distortion of the chip is reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明実施例の平面図、第２図は同実施例の断
面図である。 １・・・・・・ガラスエポキシ積層板、２・・・・・・
銅箔電極、３・・・・・・チップ、４・・・・・・銀ペ
ースト。FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view of the same embodiment. 1...Glass epoxy laminate, 2...
Copper foil electrode, 3...chip, 4...silver paste.

Claims (1)

【特許請求の範囲】[Claims] プリント基板表面のチップ接着用金属電極を複数領域に
分割したことを特徴とする回路装置。A circuit device characterized in that a metal electrode for chip adhesion on the surface of a printed circuit board is divided into multiple regions.
JP62014709A 1987-01-23 1987-01-23 Circuit device Pending JPS63181436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62014709A JPS63181436A (en) 1987-01-23 1987-01-23 Circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62014709A JPS63181436A (en) 1987-01-23 1987-01-23 Circuit device

Publications (1)

Publication Number Publication Date
JPS63181436A true JPS63181436A (en) 1988-07-26

Family

ID=11868689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62014709A Pending JPS63181436A (en) 1987-01-23 1987-01-23 Circuit device

Country Status (1)

Country Link
JP (1) JPS63181436A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04297101A (en) * 1991-03-13 1992-10-21 Mitsubishi Electric Corp Semiconductor package
JP2007208276A (en) * 2007-03-08 2007-08-16 Texas Instr Japan Ltd Semiconductor device and its manufacturing method
JP2013065891A (en) * 2007-09-06 2013-04-11 Nichia Chem Ind Ltd Semiconductor device
JP2014045156A (en) * 2012-08-29 2014-03-13 Hitachi Automotive Systems Ltd Electronic control device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04297101A (en) * 1991-03-13 1992-10-21 Mitsubishi Electric Corp Semiconductor package
JP2007208276A (en) * 2007-03-08 2007-08-16 Texas Instr Japan Ltd Semiconductor device and its manufacturing method
JP4484891B2 (en) * 2007-03-08 2010-06-16 日本テキサス・インスツルメンツ株式会社 Semiconductor device and manufacturing method thereof
JP2013065891A (en) * 2007-09-06 2013-04-11 Nichia Chem Ind Ltd Semiconductor device
JP2014045156A (en) * 2012-08-29 2014-03-13 Hitachi Automotive Systems Ltd Electronic control device

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