JPH04297101A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH04297101A
JPH04297101A JP3048105A JP4810591A JPH04297101A JP H04297101 A JPH04297101 A JP H04297101A JP 3048105 A JP3048105 A JP 3048105A JP 4810591 A JP4810591 A JP 4810591A JP H04297101 A JPH04297101 A JP H04297101A
Authority
JP
Japan
Prior art keywords
die pad
chip
package
semiconductor device
pad part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3048105A
Other languages
Japanese (ja)
Inventor
Toshiichi Ogata
敏一 尾形
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3048105A priority Critical patent/JPH04297101A/en
Publication of JPH04297101A publication Critical patent/JPH04297101A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Waveguide Connection Structure (AREA)

Abstract

PURPOSE:To improve high frequency characteristics while reducing stray capacity regardless of the size of a chip to be incorporated in a die pad part. CONSTITUTION:A die pad part 1a is divided by an insulated stripe 1b. The small chips are incorporated on one die pad part 1a, and large chips are incorporated using a plurality of die pad part 1a to make the area of the die pad part 1a minimum capable of incorporating the chip. The stray capacity of the package is held according to a chip 5 to be incorporated.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は、浮遊容量を減少させた
半導体装置用パッケ−ジに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package with reduced stray capacitance.

【０００２】0002

【従来の技術】図４は従来の半導体装置用パッケ−ジを
示す斜視図である。この図において、１はベ−スセラミ
ックス、１ａはこのベ−スセラミックス１上にメタライ
ズされたダイパッド部、２は前記ベ−スセラミックス１
上に装着されたフレ−ムセラミックス、３はこのフレ−
ムセラミックス２にろう付けされた外部リ−ド端子、４
は放熱フィンである。2. Description of the Related Art FIG. 4 is a perspective view showing a conventional package for a semiconductor device. In this figure, 1 is a base ceramic, 1a is a die pad portion metallized on this base ceramic 1, and 2 is a base ceramic 1.
Frame ceramics mounted on top, 3 indicates this frame.
External lead terminal brazed to ceramics 2, 4
is a heat dissipation fin.

【０００３】次に、動作について説明する。ベ−スセラ
ミックス１上にメタライジングされたダイパッド部１ａ
の寸法は、その上にボンディングするトランジスタ等の
チップ寸法をあらかじめ想定し、十分搭載できるように
大きく決められる。また、チップの設計変更や、多種チ
ップの使用等で搭載するチップ寸法がダイパッド部１ａ
の寸法に比べ極端に小さくなる。Next, the operation will be explained. Die pad portion 1a metallized on base ceramics 1
The size of the chip is determined in advance so that the size of the chip such as a transistor to be bonded thereon can be assumed, and the size of the chip can be sufficiently mounted. In addition, due to changes in chip design or the use of various types of chips, the dimensions of the chip mounted on the die pad portion 1a may change.
extremely small compared to the dimensions of

【０００４】一般に高周波特性を向上させるための一手
段としてパッケ−ジの浮遊容量を下げる、すなわちダイ
パッド部１ａの面積をチップが搭載可能な最小面積とす
るのが一般的なアプロ−チ方法である。Generally, as a means of improving high frequency characteristics, a common approach is to reduce the stray capacitance of the package, that is, to make the area of the die pad portion 1a the minimum area on which a chip can be mounted. .

【０００５】[0005]

【発明が解決しようとする課題】従来の半導体装置用パ
ッケ−ジは、以上のように高周波特性を向上させるため
、使用チップ寸法に合せ浮遊容量を減らそうとすれば、
パッケ−ジのメタライジングパタ−ンの変更から行うこ
とが必要で、パッケ−ジコストの上昇，パッケ−ジ納期
の長期化等の問題点があった。[Problems to be Solved by the Invention] In order to improve the high frequency characteristics of conventional semiconductor device packages as described above, it is necessary to reduce stray capacitance in accordance with the chip size used.
It is necessary to change the metallizing pattern of the package, which causes problems such as an increase in package cost and a long package delivery time.

【０００６】本発明は、上記のような問題点を解消する
ためになされたもので、いかなるチップ寸法のものを搭
載する際にもパッケ−ジ浮遊容量を小さくすることがで
きる半導体装置用パッケ−ジを得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and provides a package for semiconductor devices that can reduce the stray capacitance of the package when mounting chips of any size. The purpose is to obtain

【０００７】[0007]

【課題を解決するための手段】本発明に係る半導体装置
用パッケ−ジは、ダイパッド部のメタライズ部分に絶縁
のためのストライプを設け、ダイパッド部を複数に分割
したものである。SUMMARY OF THE INVENTION A package for a semiconductor device according to the present invention has stripes for insulation provided on the metallized portion of the die pad portion, and the die pad portion is divided into a plurality of parts.

【０００８】[0008]

【作用】本発明における半導体装置用パッケ−ジのダイ
パッド部は、複数の絶縁ストライプで分割したことから
、最小面積のダイパッド部に、チップを搭載することが
でき、浮遊容量を減少させることができる。[Function] Since the die pad portion of the semiconductor device package according to the present invention is divided by a plurality of insulating stripes, a chip can be mounted on the die pad portion with the minimum area, and stray capacitance can be reduced. .

【０００９】[0009]

【実施例】以下、本発明の一実施例を図について説明す
る。図１は本発明の一実施例を示す半導体装置用パッケ
−ジの斜視図である。この図において、図４と同一符号
を付してある部分は同一構成部分を示し、１ｂは絶縁ス
トライプで、これによりメタライズ部を複数に分割し、
複数のダイパッド部１ａが形成される。２はフレ−ムセ
ラミックス、３はこのフレ−ムセラミックス２にろう付
けされた外部リ−ド端子、４は放熱フィンである。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view of a package for a semiconductor device showing an embodiment of the present invention. In this figure, parts with the same reference numerals as those in FIG.
A plurality of die pad portions 1a are formed. 2 is a frame ceramic, 3 is an external lead terminal brazed to the frame ceramic 2, and 4 is a heat radiation fin.

【００１０】図２は比較的小さなチップ５を、分割した
ダイパッド部１ａの１つのセグメント上に搭載し、その
セグメントから出力細線６等を配線した半導体装置であ
り、パッケ−ジの浮遊容量として他セグメントの分は軽
減される効果がある。FIG. 2 shows a semiconductor device in which a relatively small chip 5 is mounted on one segment of a divided die pad portion 1a, and output thin wires 6, etc. are routed from that segment. This has the effect of reducing the amount of segment.

【００１１】図３は比較的大きなチップ５を、分割した
ダイパッド部１ａの複数のセグメントを使用して搭載可
能となることを示したもので、各セグメントから出力細
線６等を配線した図である。FIG. 3 shows that a relatively large chip 5 can be mounted using a plurality of segments of the divided die pad portion 1a, and is a diagram in which thin output wires 6, etc. are wired from each segment. .

【００１２】0012

【発明の効果】以上説明したように、本発明は、メタラ
イズ部を分割して複数のダイパッド部を形成し、搭載す
るチップの大きさに対応した１つのセグメントまたは複
数のセグメント上にチップを搭載するようにしたので、
１種類の半導体装置用パッケ−ジで多種類のチップが搭
載でき、高周波特性の向上につながるパッケ−ジの浮遊
容量を搭載するチップに合せて小さく抑え、かつ小さな
チップから大きなチップまで使用セグメント数を増すこ
とで搭載できる半導体装置用パッケ−ジが得られる効果
がある。As explained above, the present invention divides a metallized portion to form a plurality of die pad portions, and mounts the chip on one segment or multiple segments corresponding to the size of the chip to be mounted. I decided to do this, so
Many types of chips can be mounted in one type of semiconductor device package, and the stray capacitance of the package, which improves high frequency characteristics, can be kept small according to the chip being mounted, and the number of segments used can be reduced from small chips to large chips. There is an effect that a package for a semiconductor device that can be mounted can be obtained by increasing the number of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】本発明の一実施例による半導体装置用パッケ−
ジを示す斜視図である。FIG. 1: A package for a semiconductor device according to an embodiment of the present invention.
FIG.

【図２】図１の半導体装置用パッケ−ジに小さなチップ
を搭載した状態を示す斜視図である。FIG. 2 is a perspective view showing a state in which a small chip is mounted on the semiconductor device package of FIG. 1;

【図３】同じく大きなチップを搭載した状態を示す斜視
図である。FIG. 3 is a perspective view showing a state in which a similarly large chip is mounted.

【図４】従来の半導体装置用パッケ−ジを示す斜視図で
ある。FIG. 4 is a perspective view showing a conventional package for a semiconductor device.

【符号の説明】[Explanation of symbols]

１　　　　ベ−スセラミックス １ａ　　ダイパッド部 １ｂ　　絶縁ストライプ ２　　　　フレ−ムセラミックス ３　　　　外部リ−ド端子 ４　　　　放熱フィン ５　　　　チップ ６　　　　出力細線 1. Base ceramics 1a Die pad part 1b Insulation stripe 2 Frame ceramics 3 External lead terminal 4 Heat radiation fins 5 Chip 6 Output thin line

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】ベ−スセラミックス上にメタライズされた
ダイパッド部にチップを搭載して構成された半導体装置
用パッケ−ジにおいて、前記メタライズ部を絶縁のため
のストライプにより分割し、複数のダイパッド部を形成
したことを特徴とする半導体装置用パッケ−ジ。1. A semiconductor device package configured by mounting a chip on a metallized die pad portion on a base ceramic, wherein the metallized portion is divided by stripes for insulation, and a plurality of die pad portions are formed. 1. A package for a semiconductor device, characterized in that a package for a semiconductor device is formed.
JP3048105A 1991-03-13 1991-03-13 Semiconductor package Pending JPH04297101A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3048105A JPH04297101A (en) 1991-03-13 1991-03-13 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3048105A JPH04297101A (en) 1991-03-13 1991-03-13 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH04297101A true JPH04297101A (en) 1992-10-21

Family

ID=12794039

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3048105A Pending JPH04297101A (en) 1991-03-13 1991-03-13 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH04297101A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63181436A (en) * 1987-01-23 1988-07-26 Matsushita Electronics Corp Circuit device
JPS6489548A (en) * 1987-09-30 1989-04-04 Mitsubishi Electric Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63181436A (en) * 1987-01-23 1988-07-26 Matsushita Electronics Corp Circuit device
JPS6489548A (en) * 1987-09-30 1989-04-04 Mitsubishi Electric Corp Semiconductor device

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