JPS63177451A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63177451A JPS63177451A JP62008755A JP875587A JPS63177451A JP S63177451 A JPS63177451 A JP S63177451A JP 62008755 A JP62008755 A JP 62008755A JP 875587 A JP875587 A JP 875587A JP S63177451 A JPS63177451 A JP S63177451A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor
- semiconductor substrate
- layer
- recessed part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 118
- 238000000034 method Methods 0.000 abstract description 5
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
Ａ、産業上の利用分野
本発明は上下２層に半導体基板を配置した半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a semiconductor device in which semiconductor substrates are arranged in two layers, upper and lower.
Ｂ、従来の技術
２種類の半導体チップを電極部分で接合させて形成した
半導体装置が例えばＩＥＥＥ ＩＥＤＭ１９８４年第
８１６頁〜第８１９頁に開示されている。第１０図に示
すとおり、この従来の半導体装置は、・半導体素子５３
が設けられた下層基板５１と半導体基板５４が設けられ
た上層基板５２とが互いに接合されて構成されている。B. Prior Art A semiconductor device formed by joining two types of semiconductor chips at electrode portions is disclosed, for example, in IEEE IEDM, 1984, pages 816 to 819. As shown in FIG. 10, this conventional semiconductor device includes: a semiconductor element 53;
A lower substrate 51 provided with a semiconductor substrate 54 and an upper substrate 52 provided with a semiconductor substrate 54 are bonded to each other.
下層基板５１の酸化シリコン層（Ｓｉｎ、）５５には半
導体素子５３の一部を形成するポリシリコンゲート５６
と、ＡＱ電極５７と、Ａｕ電極５８と、ポリイミド層５
９とが形成され、同様に上層基板５２の酸化シリコン層
６０には半導体素子５４の一部を形成するポリシリコン
ゲート６１と、Ａｕ電極６２と、Ａｕ電極６３と、ポリ
イミド層６４とが形成されている。そして、下層基板５
１と上層基板５２とはＡｕ電極５８とＡｕ電極６３とに
よって電気的接続がなされ、また基板表面のポリイミド
層５９．６４は平坦化されている。A polysilicon gate 56 forming a part of the semiconductor element 53 is formed on the silicon oxide layer (Sin) 55 of the lower substrate 51.
, AQ electrode 57 , Au electrode 58 , and polyimide layer 5
Similarly, a polysilicon gate 61 forming a part of the semiconductor element 54, an Au electrode 62, an Au electrode 63, and a polyimide layer 64 are formed on the silicon oxide layer 60 of the upper substrate 52. ing. And the lower substrate 5
1 and the upper substrate 52 are electrically connected by Au electrodes 58 and 63, and polyimide layers 59 and 64 on the substrate surface are planarized.
このような構成によれば半導体素子を三次元的配置する
ことができ集積度が向上する。また互いに接する面に酸
化シリコン層５５．６０を形成し、さらにこれらの表面
にポリイミド層５９．６４を形成しているので、上層基
板Ｓ２と下層基板５１とが完全に絶縁され、ＣＭＯＳト
ランジスタなどに用いた場合にラッチアップを有効に防
止できる。According to such a configuration, semiconductor elements can be arranged three-dimensionally, and the degree of integration is improved. Furthermore, since silicon oxide layers 55 and 60 are formed on the surfaces in contact with each other, and polyimide layers 59 and 64 are further formed on these surfaces, the upper layer substrate S2 and the lower layer substrate 51 are completely insulated, making it suitable for CMOS transistors and the like. When used, latch-up can be effectively prevented.
Ｃ９発明が解決しようとする問題点
しかしながら、上述のような従来の半導体装置では、２
つの半導体基板５１．５２の全表面を精度よく平坦化し
なくてはならず、コストがかかり、また電気的接続の信
頼性に問題があった。C9 Problems to be Solved by the Invention However, in the conventional semiconductor device as described above, 2
The entire surface of each semiconductor substrate 51, 52 must be planarized with high precision, which increases cost and poses problems in the reliability of electrical connections.
本発明は、上下２層の半導体基板同士の電気的接触が良
好でありかつ低コストの半導体装置を提供することを目
的としている。An object of the present invention is to provide a low-cost semiconductor device that has good electrical contact between upper and lower semiconductor substrate layers.
Ｄ２問題点を解決するための手段
本発明に係る半導体装置は、一実施例を示す第１図に示
すとおり、基板のほぼ中央部に半導体素子３−１．３−
２が形成されるとともに該半導体素子３−１．３−２の
周囲に配線用電極８が設けられた第１の半導体基板１と
、表面に半導体素子４−１．４−２が形成されると共に
裏面に凹部５が形成された第２の半導体基板２とを備え
、凹部５が第１の半導体基板１上の半導体素子３−１゜
３−２を囲繞し配線用電極８を囲繞しないように、当該
凹部５を画成する第２の半導体基板の凸部１７を第１の
半導体基板１に接合して両基板を一体化したものである
。Means for Solving Problem D2 As shown in FIG. 1 showing one embodiment, the semiconductor device according to the present invention has a semiconductor element 3-1.3- located approximately in the center of the substrate.
A first semiconductor substrate 1 on which a wiring electrode 8 is provided around the semiconductor element 3-1.3-2, and a semiconductor element 4-1.4-2 is formed on the surface thereof. and a second semiconductor substrate 2 having a recess 5 formed on its back surface, so that the recess 5 surrounds the semiconductor elements 3-1 and 3-2 on the first semiconductor substrate 1 and does not surround the wiring electrode 8. Then, the convex portion 17 of the second semiconductor substrate defining the recess 5 is bonded to the first semiconductor substrate 1 to integrate both substrates.
Ｅ０作用
第２の半導体基板２は、その凸部１７を第１の半導体基
板１に接合して第１の半導体基板１上に積層され、これ
により第１の半導体基板１と第２の半導体基板２との接
着面積が小さくなる。このため、両基板の接触面が従来
よりも狭くなり、平滑化に要するコストが低減される。E0 action The second semiconductor substrate 2 is stacked on the first semiconductor substrate 1 with its convex portion 17 bonded to the first semiconductor substrate 1, and thereby the first semiconductor substrate 1 and the second semiconductor substrate 1 are bonded to each other. The adhesion area with 2 becomes smaller. Therefore, the contact surface between both substrates becomes narrower than before, and the cost required for smoothing is reduced.
また第１の半導体基板１の配線用電極８は、例えばＡＱ
ワイヤあるいはＡｕワイヤ１０．１１などを用いたワイ
ヤボンディングなどによって第２の半導体基板２の電極
９と直接接続されるので信頼性が向上する。Further, the wiring electrode 8 of the first semiconductor substrate 1 is, for example, an AQ
Since it is directly connected to the electrode 9 of the second semiconductor substrate 2 by wire bonding using a wire or Au wire 10, 11, etc., reliability is improved.
Ｆ、実施例
本発明の一実施例を第１図および第２図に基づいて説明
する。F. Embodiment An embodiment of the present invention will be described based on FIGS. 1 and 2.
第１図は本発明の半導体装置の構成図であり、半導体素
子３−１．３−２が形成された下層基板１と半導体素子
４−１．４−２が形成された上層基板２とが凸部１７を
介して接合されている。下層基板１と接する上層基板２
の下面には凹部５が形成され、下層基板１の半導体素子
３−１゜３−２はこの凹部５に収容されている。半導体
素子３−１．３−２は、ポリシリコンからなるゲート電
極１３−１．１３−２をそれぞれ有し、また半導体素子
４−１．４−２はポリシリコンからなるゲート電極１４
−１．１４−２をそれぞれ有する。なお、これらの半導
体素子３−１．３−２および４−１．４−２上には表面
保護膜１５゜１６がそれぞれ設けられている。また半導
体素子３−２および４−２の下側にはウェル４１および
４２がそれぞれ形成されている。FIG. 1 is a block diagram of a semiconductor device of the present invention, in which a lower substrate 1 on which a semiconductor element 3-1.3-2 is formed and an upper substrate 2 on which a semiconductor element 4-1.4-2 is formed. They are joined via the protrusion 17. Upper layer substrate 2 in contact with lower layer substrate 1
A recess 5 is formed in the lower surface of the substrate 1, and the semiconductor elements 3-1 and 3-2 of the lower substrate 1 are housed in the recess 5. The semiconductor elements 3-1.3-2 each have a gate electrode 13-1.13-2 made of polysilicon, and the semiconductor element 4-1.4-2 has a gate electrode 14 made of polysilicon.
-1.14-2 respectively. Incidentally, surface protective films 15 and 16 are provided on these semiconductor elements 3-1, 3-2 and 4-1, 4-2, respectively. Further, wells 41 and 42 are formed under the semiconductor elements 3-2 and 4-2, respectively.
下層基板１と上層基板２とは酸化膜６を介して接着され
、酸化膜６に接する下層基板１の表面には拡散層配線７
など凹凸の少ない素子が形成されている。また上層基板
２が当接しない下層基板１の縁部表面にはＬＯＧＯ８酸
化膜（局所酸化膜）１２が設けられ、そのほぼ真上に外
部電極取り出し用のＡΩパッド８が形成されている。こ
のＡＱバッド８と上層基板２のＡＱパッド９とはＡｕワ
イヤ１０（あるいはＡｆｉワイヤ）で直接接続されてい
る。リードフレーム（図示せず）を介して両者を接続し
てもよい。The lower substrate 1 and the upper substrate 2 are bonded together via an oxide film 6, and a diffusion layer wiring 7 is provided on the surface of the lower substrate 1 in contact with the oxide film 6.
An element with few irregularities is formed. Further, a LOGO8 oxide film (local oxide film) 12 is provided on the edge surface of the lower substrate 1 which the upper substrate 2 does not contact, and an AΩ pad 8 for taking out external electrodes is formed almost directly above the LOGO8 oxide film (local oxide film) 12. This AQ pad 8 and the AQ pad 9 of the upper layer substrate 2 are directly connected by an Au wire 10 (or an Afi wire). The two may be connected via a lead frame (not shown).
第２図（ａ）〜（ｇ）は第１図に示す半導体装置の製造
プロセスを示したものである。FIGS. 2(a) to 2(g) show the manufacturing process of the semiconductor device shown in FIG. 1.
第２図（ａ）に示すように、先ず下層基板１および上層
基板２に半導体素子３−１．３−２および半導体素子４
−１．４−２をそれぞれ形成するとともに、ＡＱパッド
８，９を設ける。このとき下層基板１の半導体素子３−
１．３−２とＡＱパッド８との間にはある程度の距離を
もたせて表面が平坦となる拡散層配線７（第１図参照）
で接続し、更にその上に積層された酸化膜６（第１図参
照）を平坦化する。これにより、両者間に広がる基板表
面の凹凸を小さくする。As shown in FIG. 2(a), first, semiconductor elements 3-1, 3-2 and semiconductor elements 4 are placed on a lower substrate 1 and an upper substrate 2.
-1, 4-2 are respectively formed, and AQ pads 8 and 9 are provided. At this time, the semiconductor element 3- of the lower substrate 1
1. Diffusion layer wiring 7 with a flat surface with a certain distance between 3-2 and AQ pad 8 (see Figure 1)
The oxide film 6 (see FIG. 1) layered thereon is then flattened. This reduces the unevenness on the substrate surface that spreads between the two.
次に第２図（ｂ）に示すように、上層基板２の底面のう
ち、半導体素子３−１．３−２およびＡＱパッド８に対
向する部分にエツチング等により凹部５を形成する。こ
のときに凸部１７が同時に形成される。Next, as shown in FIG. 2(b), a recess 5 is formed by etching or the like in a portion of the bottom surface of the upper layer substrate 2 facing the semiconductor element 3-1, 3-2 and the AQ pad 8. At this time, the convex portion 17 is formed at the same time.
次いで第２図（ｃ）に示すように、上層基板２の凸部１
７と下層基板１の平坦化された酸化膜６とを、例えば特
開昭６０−５１７００号に開示されている方法で接着す
る。上層基板２と下層基板１とを接着した後、第２図（
ｄ）に示すように、上１基板２の凸部１７の外側でかつ
下層基板１のＡＱバッド８よりも内方と対峙する部分を
符号１８で示すように切断する。さらに第２図（ｅ）に
示すように、下層基板１のＡｆｌダイパッド外周部分を
符号１９で示すように切断し、第２図（ｆ）に示すよう
にする。Next, as shown in FIG. 2(c), the convex portion 1 of the upper layer substrate 2 is
7 and the planarized oxide film 6 of the lower substrate 1 are bonded together, for example, by the method disclosed in Japanese Patent Laid-Open No. 60-51700. After bonding the upper layer substrate 2 and the lower layer substrate 1, as shown in FIG.
As shown in d), a portion outside the convex portion 17 of the upper substrate 2 and facing inward from the AQ pad 8 of the lower substrate 1 is cut as shown by reference numeral 18. Further, as shown in FIG. 2(e), the outer circumferential portion of the Afl die pad of the lower substrate 1 is cut as shown by reference numeral 19 to form the shape shown in FIG. 2(f).
最後に第２図（ｆ）に示す半導体チップをセラミックパ
ッケージあるいはリードフレームのダイパッドにダイボ
ンディングし、第２図（ｇ）に示すように上層基板２と
下層基板１のＡΩパッド８゜９同士をＡｕワイヤ１０，
１１などによってワイヤボンディングして半導体装置が
完成する。Finally, the semiconductor chip shown in FIG. 2(f) is die-bonded to the die pad of the ceramic package or lead frame, and the AΩ pads 8°9 of the upper layer substrate 2 and lower layer substrate 1 are bonded together as shown in FIG. 2(g). Au wire 10,
11 and the like to complete the semiconductor device.
このような構造の半導体装置では、上層基板２と下層基
板１との接着面積が上層基板の凸部１７の底面積だけで
あるので、下層基板１および上層基板２を広い面積にわ
たって平坦化する必要がなく、平坦化に要するコストを
低減できる。また上層基板２と下層基板１との電気的接
続がワイヤボンディングによってなされるために電気的
接続部の信頼性が向上する。In a semiconductor device having such a structure, since the bonding area between the upper layer substrate 2 and the lower layer substrate 1 is only the bottom area of the convex portion 17 of the upper layer substrate, it is necessary to flatten the lower layer substrate 1 and the upper layer substrate 2 over a wide area. Therefore, the cost required for planarization can be reduced. Further, since the electrical connection between the upper layer substrate 2 and the lower layer substrate 1 is made by wire bonding, the reliability of the electrical connection is improved.
第３図〜第９図は、第１図に示した半導体装置の応用例
を示したものである。3 to 9 show examples of applications of the semiconductor device shown in FIG. 1.
第３図は、下層基板１にＣＰＵ２０を形成し、上層基板
２にＲＯＭまたはＲＡＭのメモリ素子２１を形成したも
のである。汎用性のＣＰＵ２０を用いれば、用途に応じ
てメモリ素子２１のみを積換えればよく、設計自由度が
向上し、しかも実装密度が小さくなる。In FIG. 3, a CPU 20 is formed on the lower substrate 1, and a memory element 21 of ROM or RAM is formed on the upper substrate 2. If the general-purpose CPU 20 is used, only the memory element 21 needs to be replaced depending on the application, which improves the degree of freedom in design and reduces the packaging density.
第４図は、下層基板１にバイポーラ素子２１を形成し下
層基板２にＣＭＯＳトランジスタなどのＭＯＳデバイス
２３を形成した例である。近年、ＣＭＯ８）−ランジス
タ回路の出力段などにファンアウト（電流容量）の大き
なバイポーラトランジスタを用いたいという要求が高ま
っている。１チツプ上に異種のトランジスタを形成する
場合に素子分離工程が複雑でコストアップとなるが、第
４図に示すような構造をとれば、１チツプ上に異種のデ
バイスを形成することも容易になる。FIG. 4 shows an example in which a bipolar element 21 is formed on the lower substrate 1 and a MOS device 23 such as a CMOS transistor is formed on the lower substrate 2. In recent years, there has been an increasing demand for using bipolar transistors with large fan-out (current capacity) in the output stage of CMO8)-transistor circuits and the like. When forming different types of transistors on one chip, the element isolation process is complicated and costs increase, but if the structure shown in Figure 4 is adopted, it is easy to form different types of devices on one chip. Become.
第５図は、下層基板１にパワーＭＯＳトランジスタ２４
を形成し上層基板２にＣＭＯＳトランジスタ２５を形成
した例である。この構成も第４図に示す構成と同様に素
子分離工程のためのコストを削減することができる。さ
らに、パワーＭＯＳトランジスタ２４のチップ上にＣＭ
ＯＳトランジスタ２５を形成しているので、パワーＭＯ
Ｓトランジスタ２３から発生する熱がＣＭＯＳトランジ
スタ２４に伝わり易くなり過温度検知の停止回路などを
実現することができる。FIG. 5 shows a power MOS transistor 24 on the lower substrate 1.
This is an example in which a CMOS transistor 25 is formed on the upper layer substrate 2. This configuration can also reduce the cost for the element isolation process, similar to the configuration shown in FIG. Furthermore, a CM on the chip of the power MOS transistor 24 is
Since it forms the OS transistor 25, the power MO
The heat generated from the S transistor 23 is easily transmitted to the CMOS transistor 24, making it possible to implement a stop circuit for detecting overtemperature.
第６図は、上層基板２の凹部５にメタル２５を蒸着して
これを接地電位にすることによって下層基板１に形成し
た回路をシールドするようにした例である。下層基板１
に例えば高速のクロックによって作動する高速動作回路
２６を形成した場合、高速動作回路２６からノイズが発
生し他の素子を誤動作させる可能性がある。第６図に示
すように上層基板２の凹部５にメタル２５のシールドを
形成することによって、高速動作回路２６から発生する
ノイズを有効に遮断し他の素子の誤動作を防止できる。FIG. 6 shows an example in which the circuit formed on the lower substrate 1 is shielded by depositing metal 25 in the recess 5 of the upper substrate 2 and setting it at ground potential. Lower substrate 1
For example, if a high-speed operation circuit 26 operated by a high-speed clock is formed, noise may be generated from the high-speed operation circuit 26 and cause other elements to malfunction. As shown in FIG. 6, by forming a metal shield 25 in the recess 5 of the upper layer substrate 2, noise generated from the high-speed operation circuit 26 can be effectively blocked and malfunctions of other elements can be prevented.
また外部ノイズを遮断する効果もある。It also has the effect of blocking external noise.
また第７図は、下層基板１としてＧ検出用片持ち梁２７
をもつＧセンサ２８を用いたものであり、上層基板２の
凸部１７を片持ち梁２７の過振防止用ストッパとした例
である。通常、片持ち梁構造をもつ梁のストッパには、
半導体素子が形成されていない半導体基板を用いるが、
第７図に示すような構造にすればストッパ用の上層基板
２にも例えば信号処理回路２９のような半導体素子を形
成することが可能となり実装面積を小さくすることがで
きる。FIG. 7 also shows a cantilever beam 27 for G detection as the lower substrate 1.
This is an example in which the convex portion 17 of the upper layer substrate 2 is used as a stopper for preventing excessive vibration of the cantilever beam 27. Usually, a stopper for a beam with a cantilever structure is
Although a semiconductor substrate on which no semiconductor element is formed is used,
With the structure shown in FIG. 7, it is possible to form a semiconductor element such as the signal processing circuit 29 on the upper layer substrate 2 for the stopper, and the mounting area can be reduced.
また第８図は、下層基板１としてダイヤフラム３０をも
つ圧力センサ３１を用いると共に、上層基板２の凹部５
を真空室として用いた例である。8 uses a pressure sensor 31 having a diaphragm 30 as the lower substrate 1, and also uses a recess 5 in the upper substrate 2.
This is an example of using a vacuum chamber as a vacuum chamber.
圧力センサ３１のダイヤフラム３０の一方の面を真空圧
にすることにより、絶対圧を検知する圧力センサを構成
することができる。上層基板２に検知回路としての信号
処理回路３２を形成することによって小型の圧力センサ
を構成することができる。なお、第８図に示す半導体装
置は第２図（ｃ）の工程を真空中で行うことによって凹
部５を真空とし、容易に形成できる。By applying vacuum pressure to one surface of the diaphragm 30 of the pressure sensor 31, a pressure sensor that detects absolute pressure can be constructed. By forming the signal processing circuit 32 as a detection circuit on the upper layer substrate 2, a small pressure sensor can be constructed. Note that the semiconductor device shown in FIG. 8 can be easily formed by performing the process shown in FIG. 2(c) in a vacuum to make the recess 5 a vacuum.
第９図も、上層基板２の凹部５を真空室として用いた例
である。下層基板１を１９８４年発行のＰｒｏｃｅｅｄ
ｉｎｇｓ ｏｆ ｔｈｅ Ｉ Ｅ Ｅ Ｅ第７０巻第４
２０頁〜第４５６頁に示されているような片持ち梁構造
の振動センサ３３としている。片持ち梁構造の振動セン
サ３３は、振動の検知感度を向上させるため真空中に形
成する必要があり、第９図に示すような構造を用いれば
１ウ工ハ単位で同時に多数の真空室を形成できるので、
実装工数を低減することができる。また真空室上の上層
基板２内に信号処理回路３４等を形成できるので実装面
積を小さくすることができる。FIG. 9 also shows an example in which the recess 5 of the upper substrate 2 is used as a vacuum chamber. Proceed of lower layer board 1 issued in 1984
ings of the IEE Volume 70 No. 4
The vibration sensor 33 has a cantilever structure as shown on pages 20 to 456. The vibration sensor 33 with a cantilever structure needs to be formed in a vacuum in order to improve the vibration detection sensitivity, and if the structure shown in FIG. Because it can be formed,
Mounting man-hours can be reduced. Furthermore, since the signal processing circuit 34 and the like can be formed in the upper layer substrate 2 above the vacuum chamber, the mounting area can be reduced.
Ｇ０発明の詳細
な説明したように、本発明によれば、第２の半導体基板
の凸部を第１の半導体基板に接合して第１の半導体基板
上に第２の半導体基板を積層し、これにより第１の半導
体基板と第２の半導体基板との接着面積が小さくなり、
このため、両基板の接触面が従来よりも狭くなり、平滑
化に要するコストが低減される。また第１の半導体基板
の配線用電極を１例えばＡｕワイヤあるいはＡｕワイヤ
などを用いたワイヤボンディングなどによって第２の半
導体基板の電極と直接接続したので信頼性が向上する。As described in detail of the G0 invention, according to the present invention, the convex portion of the second semiconductor substrate is bonded to the first semiconductor substrate, and the second semiconductor substrate is laminated on the first semiconductor substrate, This reduces the adhesive area between the first semiconductor substrate and the second semiconductor substrate,
Therefore, the contact surface between both substrates becomes narrower than before, and the cost required for smoothing is reduced. Further, since the wiring electrodes of the first semiconductor substrate are directly connected to the electrodes of the second semiconductor substrate by, for example, Au wire or wire bonding using Au wire, reliability is improved.
第１図は本発明に係る半導体装置の一実施例を示す構成
図、第２図（ａ）〜（ｇ）は本発明に係る半導体装置の
製造工程例を示す図、第３図〜第９図は本発明に係る半
導体装置の応用例を示す図、第１０図は従来の半導体装
置の構成図である。
１：下層基板 ２：上層基板３−１．３−２
．４−１．４−２：半導体素子５：凹部
６二酸化膜
８．９：ＡＱパッド １０．１１：Ａｕワイヤ１７：凸
部
特許出願人 日産自動車株式会社
代理人弁理士 永 井 冬 紀
第２図
第２図
第３図 第６図
第４図 第７図
第５図 第８図
ダイアフラム 圧力センサ
第９図FIG. 1 is a configuration diagram showing an embodiment of a semiconductor device according to the present invention, FIGS. 1 is a diagram showing an application example of a semiconductor device according to the present invention, and FIG. 10 is a configuration diagram of a conventional semiconductor device. 1: Lower layer substrate 2: Upper layer substrate 3-1.3-2
．． 4-1.4-2: Semiconductor element 5: Recessed part
6 Dioxide film 8.9: AQ pad 10.11: Au wire 17: Convex portion Patent applicant: Nissan Motor Co., Ltd. Representative Patent Attorney Fuyuki Nagai Figure 2 Figure 2 Figure 3 Figure 6 Figure 4 Figure 7 Figure 5 Figure 8 Diaphragm Pressure sensor Figure 9
Claims (1)
もに該半導体素子の周囲に配線用電極が設けられた第１
の半導体基板と、 表面に半導体素子が形成されると共に裏面に凹部が形成
された第２の半導体基板とを備え、前記凹部が前記第１
の半導体基板上の半導体素子を囲繞し前記配線用電極を
囲繞しないように、当該凹部を画成する前記第２の半導
体基板の凸部を前記第１の半導体基板に接合して両基板
を一体化したことを特徴とする半導体装置。(1) A first substrate in which a semiconductor element is formed approximately at the center of the substrate and wiring electrodes are provided around the semiconductor element.
and a second semiconductor substrate having a semiconductor element formed on its front surface and a recessed portion formed on its back surface, the recessed portion being the first semiconductor substrate.
A convex portion of the second semiconductor substrate defining the concave portion is bonded to the first semiconductor substrate so that the convex portion of the second semiconductor substrate surrounds the semiconductor element on the semiconductor substrate and does not surround the wiring electrode, so that both substrates are integrated. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62008755A JPS63177451A (en) | 1987-01-17 | 1987-01-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62008755A JPS63177451A (en) | 1987-01-17 | 1987-01-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63177451A true JPS63177451A (en) | 1988-07-21 |
Family
ID=11701740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62008755A Pending JPS63177451A (en) | 1987-01-17 | 1987-01-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63177451A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003506871A (en) * | 1999-08-02 | 2003-02-18 | ハネウエル・インコーポレーテッド | Dual wafer attachment method |
| JP2005268670A (en) * | 2004-03-19 | 2005-09-29 | Nec Electronics Corp | Semiconductor device |
-
1987
- 1987-01-17 JP JP62008755A patent/JPS63177451A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003506871A (en) * | 1999-08-02 | 2003-02-18 | ハネウエル・インコーポレーテッド | Dual wafer attachment method |
| JP4890708B2 (en) * | 1999-08-02 | 2012-03-07 | ハネウェル・インターナショナル・インコーポレーテッド | Dual wafer attachment method |
| JP2005268670A (en) * | 2004-03-19 | 2005-09-29 | Nec Electronics Corp | Semiconductor device |
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