JP2001168270A - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method thereforInfo
- Publication number
- JP2001168270A JP2001168270A JP35182299A JP35182299A JP2001168270A JP 2001168270 A JP2001168270 A JP 2001168270A JP 35182299 A JP35182299 A JP 35182299A JP 35182299 A JP35182299 A JP 35182299A JP 2001168270 A JP2001168270 A JP 2001168270A
- Authority
- JP
- Japan
- Prior art keywords
- connection electrode
- substrate
- integrated circuit
- chip
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、第１の半導体集積
回路装置すなわち子チップと第２の半導体集積回路装置
すなわち親チップを組み合わせて一体化構成とした半導
体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a first semiconductor integrated circuit device, that is, a child chip, and a second semiconductor integrated circuit device, that is, a parent chip, which are integrally formed, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、半導体集積回路の高集積度化に伴
って、特性の異なる２種類の半導体集積回路装置、例え
ばバイポーラチップとＣＭＯＳチップ、アナログ系チッ
プとディジタル系チップ、カスタムチップとスタンダー
ドチップなど、を小さい空間に実装する手段として第１
の半導体集積回路装置を第２の半導体集積回路装置の上
に搭載するチップオンチップ方式の半導体装置が実用さ
れている。2. Description of the Related Art Conventionally, two types of semiconductor integrated circuit devices having different characteristics, for example, a bipolar chip and a CMOS chip, an analog chip and a digital chip, a custom chip and a standard chip, with the increase in the degree of integration of the semiconductor integrated circuit. Is the first means to implement
A chip-on-chip type semiconductor device in which the above semiconductor integrated circuit device is mounted on a second semiconductor integrated circuit device has been put to practical use.
【０００３】図５は、従来のチップオンチップ方式で実
装された半導体装置の構造を示す図である。同図におい
て、第１の半導体集積回路装置５１０には配線パッド５
１１が形成され、この配線パッド５１１に突起電極、す
なわちバンプ５１２が形成されている。第２の半導体集
積回路装置５２０には、第１の半導体集積回路装置５１
０の配線パッド５１１に対向するように、配線パッド５
２１が形成され、この配線パッド５２１に突起電極、す
なわちバンプ５２２が形成されている。FIG. 5 is a diagram showing a structure of a semiconductor device mounted by a conventional chip-on-chip method. In the figure, a first semiconductor integrated circuit device 510 has a wiring pad 5
11 are formed, and a bump electrode, that is, a bump 512 is formed on the wiring pad 511. The second semiconductor integrated circuit device 520 includes the first semiconductor integrated circuit device 51.
0, so that the wiring pad 5
21 is formed, and a bump electrode, that is, a bump 522 is formed on the wiring pad 521.
【０００４】第１の半導体集積回路装置５１０と第２の
半導体集積回路装置５２０との間は、対向するバンプ５
１２とバンプ５２２で電気的に所要の接続が行われてい
る。The first semiconductor integrated circuit device 510 and the second semiconductor integrated circuit device 520 have opposing bumps 5.
A required connection is made electrically between the bump 12 and the bump 522.
【０００５】このように第１の半導体集積回路装置５１
０と接続された第２の半導体集積回路装置５２０が、基
板５３０に載置される。そして、第２の半導体集積回路
装置５２０の周辺部に形成されている電極５２３と基板
５３０の周辺部に形成されている電極５３１とがワイヤ
ーボンディングされたリードワイヤーＷで接続され、ま
た、基板５３０の裏面側から、外部接続用半田バンプＢ
が導出される。As described above, the first semiconductor integrated circuit device 51
Second semiconductor integrated circuit device 520 connected to 0 is mounted on substrate 530. Then, the electrode 523 formed on the periphery of the second semiconductor integrated circuit device 520 and the electrode 531 formed on the periphery of the substrate 530 are connected by a lead wire W which is wire-bonded. From the back side of the solder bump B for external connection
Is derived.
【０００６】そして、樹脂によりモールドして、最終的
にパッケージし、第１の半導体集積回路装置を第２の半
導体集積回路装置の上に搭載し、一体化構成したチップ
オンチップ方式の半導体装置５０が形成されている。Then, the first semiconductor integrated circuit device is mounted on the second semiconductor integrated circuit device by molding with a resin and finally packaged, and a chip-on-chip type semiconductor device 50 is integrally formed. Are formed.
【０００７】このように、第２の半導体集積回路装置で
ある親チップ５２０の上に第１の半導体集積回路装置で
ある子チップ５１０が搭載され一体化されており、比較
的小さい空間に実装することができる。As described above, the child chip 510 as the first semiconductor integrated circuit device is mounted and integrated on the parent chip 520 as the second semiconductor integrated circuit device, and is mounted in a relatively small space. be able to.
【０００８】[0008]
【発明が解決しようとする課題】しかし、この従来のチ
ップオンチップ方式による一体化構成の半導体装置５０
では、寸法の小さい子チップ５１０が搭載された親チッ
プ５２０が、基板５３０に載置される。そして、親チッ
プ５２０から基板５３０への接続は、親チップ５２０の
周辺部に形成されている電極５２３から基板５３０の周
辺部に形成されている電極５３１へ、ワイヤーボンディ
ングされたリードワイヤーＷで行われている。However, the conventional semiconductor device 50 having an integrated structure by the conventional chip-on-chip system is used.
Here, the parent chip 520 on which the small-sized child chip 510 is mounted is mounted on the substrate 530. The connection from the parent chip 520 to the substrate 530 is performed by a lead wire W that is wire-bonded from the electrode 523 formed on the periphery of the parent chip 520 to the electrode 531 formed on the periphery of the substrate 530. Have been done.
【０００９】このために、リードワイヤーＷの分だけ基
板５３０寸法が親チップ５２０の寸法より大きくなり、
チップオンチップ方式による一体化構成の半導体装置５
０がその分だけ大きな寸法となってしまうという問題が
あった。For this reason, the size of the substrate 530 becomes larger than the size of the parent chip 520 by the lead wire W,
Semiconductor device 5 of integrated configuration by chip-on-chip method
There is a problem that the size of “0” becomes larger correspondingly.
【００１０】そこで、本発明は、チップオンチップ方式
による一体化構成の半導体装置において、親チップであ
る第２の半導体集積回路装置とこれを搭載する基板との
間のリードワイヤーを不要とし、チップオンチップ方式
による一体化構成の半導体装置をチップ・サイズド・パ
ッケージＣＳＰ可能とし、より小さく実装することを目
的とする。In view of the above, the present invention provides an integrated semiconductor device using a chip-on-chip system, which eliminates the need for a lead wire between a second semiconductor integrated circuit device as a parent chip and a substrate on which the second semiconductor integrated circuit device is mounted. It is an object of the present invention to enable a chip-sized package CSP for an integrated semiconductor device by an on-chip method and to mount the semiconductor device smaller.
【００１１】[0011]
【課題を解決するための手段】請求項１の半導体装置
は、一面側に接続用電極が設けられた基板と、この基板
の接続用電極が設けられた面であって該接続用電極の存
在しない部分に配置され、この基板と接する面の他面側
に接続用電極が形成された第１の半導体集積回路装置
と、一面側に、前記基板の接続用電極及び前記第１の半
導体集積回路装置の接続用電極に対向するように接続用
電極が設けられた第２の半導体集積回路装置と、を備
え、一体化構成されたことを特徴とする。According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a substrate provided with a connection electrode on one surface; and a surface of the substrate provided with the connection electrode, wherein the connection electrode is provided. A first semiconductor integrated circuit device disposed on a portion not to be contacted and having a connection electrode formed on the other surface side of the surface in contact with the substrate; and a connection electrode of the substrate and the first semiconductor integrated circuit formed on one surface side And a second semiconductor integrated circuit device provided with a connection electrode so as to face the connection electrode of the device.
【００１２】請求項１記載の半導体装置に依れば、基板
上の例えば中央部に寸法の小さい第１の半導体集積回路
装置すなわち子チップを載置し、この子チップと寸法の
大きい第２の半導体集積回路装置すなわち親チップを積
層するよう配置し、子チップと親チップ間及び親チップ
と基板との電気的接続を接続用電極を用いて行う。According to the first aspect of the present invention, a first semiconductor integrated circuit device having a small size, that is, a child chip is mounted on, for example, a central portion on a substrate, and a second chip having a large size is formed with the child chip. A semiconductor integrated circuit device, that is, a parent chip is arranged so as to be stacked, and electrical connection between the child chip and the parent chip and between the parent chip and the substrate are performed using connection electrodes.
【００１３】これにより、親チップである第２の半導体
集積回路装置とこれを搭載する基板との間のリードワイ
ヤーが不要となり、基板の寸法を小さくすることができ
るから、チップオンチップ方式による一体化構成の半導
体装置をチップ・サイズド・パッケージＣＳＰ可能とな
り、より小さく実装することができる。This eliminates the need for a lead wire between the second semiconductor integrated circuit device as the parent chip and the substrate on which the second semiconductor integrated circuit device is mounted, and reduces the size of the substrate. The semiconductor device having the integrated configuration can be made into a chip-sized package CSP, and can be mounted smaller.
【００１４】請求項２の半導体装置は、一面側に接続用
電極が設けられ、他面側に外部接続用電極が設けられた
基板と、この基板の接続用電極が設けられた面であって
該接続用電極の存在しない部分に配置され、この基板と
接する面の他面側に接続用電極が形成された第１の半導
体集積回路装置と、一面側に、前記基板の接続用電極及
び前記第１の半導体集積回路装置の接続用電極に対向す
るように接続用電極が設けられた第２の半導体集積回路
装置と、前記基板の接続用電極と、この基板の接続用電
極と対向する前記第２の半導体集積回路装置の接続用電
極との間に介在するように設けられた異方性導電膜と、
を備え、一体化構成されたことを特徴とする。According to a second aspect of the present invention, there is provided a semiconductor device having a connection electrode provided on one surface and an external connection electrode provided on the other surface, and a surface of the substrate provided with the connection electrode. A first semiconductor integrated circuit device having a connection electrode formed on a portion where the connection electrode does not exist, and a connection electrode formed on the other surface of the surface in contact with the substrate; A second semiconductor integrated circuit device provided with a connection electrode so as to face the connection electrode of the first semiconductor integrated circuit device; a connection electrode of the substrate; and a connection electrode facing the connection electrode of the substrate. An anisotropic conductive film provided so as to be interposed between the connection electrode of the second semiconductor integrated circuit device and
And are integrated.
【００１５】請求項２記載の半導体装置では、請求項１
記載の半導体装置が奏する機能に加えて、子チップと親
チップとの電気的接続は接続用電極にて直接行い、親チ
ップと基板との接続は異方性導電膜を介して行う。In the semiconductor device according to the second aspect, the first aspect is as follows.
In addition to the functions of the described semiconductor device, the electrical connection between the child chip and the parent chip is made directly by the connection electrode, and the connection between the parent chip and the substrate is made via an anisotropic conductive film.
【００１６】これにより、接続用電極の形成が容易とな
り、また接続すべき間隔の異なる接続用電極間の接続も
簡単に行える。This facilitates the formation of the connection electrodes, and also facilitates connection between the connection electrodes having different intervals to be connected.
【００１７】請求項３の半導体装置は、一面側に接続用
電極が設けられ、他面側に外部接続用電極が設けられた
基板と、この基板の接続用電極が設けられた面であって
該接続用電極の存在しない部分に配置され、この基板と
接する面の他面側に接続用電極が形成された第１の半導
体集積回路装置と、一面側に、前記基板の接続用電極及
び前記第１の半導体集積回路装置の接続用電極に対向す
るように接続用電極が設けられた第２の半導体集積回路
装置と、前記基板の接続用電極及び第１の半導体集積回
路装置の接続用電極と、この基板の接続用電極及び前記
第１の半導体集積回路装置の接続用電極と対向する前記
第２の半導体集積回路装置の接続用電極との間に介在す
るようにそれぞれ設けられた異方性導電膜と、を備え、
一体化構成されたことを特徴とする。According to a third aspect of the present invention, there is provided a semiconductor device having a connection electrode provided on one surface side and an external connection electrode provided on the other surface, and a surface of the substrate provided with the connection electrode. A first semiconductor integrated circuit device having a connection electrode formed on a portion where the connection electrode does not exist, and a connection electrode formed on the other surface of the surface in contact with the substrate; A second semiconductor integrated circuit device provided with a connection electrode facing the connection electrode of the first semiconductor integrated circuit device, a connection electrode of the substrate, and a connection electrode of the first semiconductor integrated circuit device And anisotropically provided between the connection electrode of the substrate and the connection electrode of the second semiconductor integrated circuit device facing the connection electrode of the first semiconductor integrated circuit device, respectively. And a conductive film,
It is characterized by being integrated.
【００１８】請求項３記載の半導体装置に依れば、請求
項１記載の半導体装置が奏する機能に加えて、すべての
接続用電極間の電気的接続を異方性導電膜を介して行
う。According to the semiconductor device of the third aspect, in addition to the function of the semiconductor device of the first aspect, the electrical connection between all the connection electrodes is performed through the anisotropic conductive film.
【００１９】これにより、さらに接続用電極の形成が容
易となり、また接続すべき間隔の異なる接続用電極間の
接続も簡単に行える。This makes it easier to form connection electrodes, and also allows connection between connection electrodes having different intervals to be connected easily.
【００２０】請求項４の半導体装置の製造方法は、一面
側に接続用電極が設けられ、他面側に外部接続用電極が
設けられた基板の前記一面側の前記接続用電極の存在し
ない部分に、前記基板と接する面の他面側に接続用電極
が形成された第１の半導体集積回路装置を配置するとと
もに、前記基板の接続用電極上に異方性導電膜を配置す
る第１工程と、一面側に、前記基板の接続用電極及び前
記第１の半導体集積回路装置の接続用電極に対向するよ
うに接続用電極が設けられた第２の半導体集積回路装置
を、前記異方性導電膜及び前記第１の半導体集積回路装
置を配置した基板と対向させる第２工程と、前記第１の
半導体集積回路装置の接続用電極とこれと対向する前記
第２の半導体集積回路装置の接続用電極とを電気的に接
続するとともに、前記基板の接続用電極とこれと対向す
る前記第２の半導体集積回路装置の接続用電極とを前記
異方性導電膜を介して電気的に接続する第３工程とを、
含むことを特徴とする。A method of manufacturing a semiconductor device according to claim 4, wherein the connection electrode is provided on one side and the connection electrode is not present on the one side of the substrate provided with the external connection electrode on the other side. A first step of arranging a first semiconductor integrated circuit device having connection electrodes formed on the other surface side of the surface in contact with the substrate, and arranging an anisotropic conductive film on the connection electrodes of the substrate A second semiconductor integrated circuit device having a connection electrode provided on one surface thereof so as to face the connection electrode of the substrate and the connection electrode of the first semiconductor integrated circuit device. A second step of facing the conductive film and the substrate on which the first semiconductor integrated circuit device is arranged, and a connection between the connection electrode of the first semiconductor integrated circuit device and the second semiconductor integrated circuit device facing the connection electrode; Electrical connection with the A third step of electrically connecting the connection electrode of the second semiconductor integrated circuit device which faces the connecting electrode of the serial board and therewith via the anisotropic conductive film,
It is characterized by including.
【００２１】請求項４の半導体装置の製造方法に依れ
ば、基板上に第１の半導体集積回路装置すなわち子チッ
プ及び接続用の異方性導電膜を配置し、これに第２の半
導体集積回路装置すなわち親チップを対向させ、子チッ
プと親チップとを接続用電極で接続し、親チップと基板
とを異方性導電膜を介して接続する。According to the method of manufacturing a semiconductor device of the fourth aspect, the first semiconductor integrated circuit device, that is, the child chip and the anisotropic conductive film for connection are arranged on the substrate, and the second semiconductor integrated circuit device is provided thereon. The circuit device, that is, the parent chip is opposed, the child chip and the parent chip are connected by connection electrodes, and the parent chip and the substrate are connected via an anisotropic conductive film.
【００２２】これにより、親チップである第２の半導体
集積回路装置とこれを搭載する基板との間の接続が、子
チップと親チップとを接続用電極で接続するだけで、他
の親チップと基板との接続は単に圧着するだけで行われ
るから、リードワイヤーを不要とした、チップ・サイズ
ド・パッケージＣＳＰの一体化構成半導体装置を簡易な
工程で形成することができる。Thus, the connection between the second semiconductor integrated circuit device, which is the parent chip, and the substrate on which the second semiconductor integrated circuit device is mounted is made by simply connecting the child chip and the parent chip with the connection electrode, and connecting the other parent chip to the other chip. Since the connection between the semiconductor device and the substrate is performed simply by press-bonding, a semiconductor device integrated with the chip-sized package CSP and requiring no lead wire can be formed by a simple process.
【００２３】請求項５の半導体装置の製造方法は、一面
側に接続用電極が設けられ、他面側に外部接続用電極が
設けられた基板の前記一面側の前記接続用電極の存在し
ない部分に、前記基板と接する面の他面側に接続用電極
が形成された第１の半導体集積回路装置を配置するとと
もに、前記基板の接続用電極上に第１の異方性導電膜を
配置し、前記第１の半導体集積回路装置の接続用電極上
に第２の異方性導電膜を配置する第１工程と、一面側
に、前記基板の接続用電極及び前記第１の半導体集積回
路装置の接続用電極に対向するように接続用電極が設け
られた第２の半導体集積回路装置を、前記第１の異方性
導電膜、前記第２の異方性導電膜及び前記第１の半導体
集積回路装置を配置した基板と対向させる第２工程と、
前記第１の半導体集積回路装置の接続用電極とこれと対
向する前記第２の半導体集積回路装置の接続用電極とを
前記第２の異方性導電膜を介して電気的に接続するとと
もに、前記基板の接続用電極とこれと対向する前記第２
の半導体集積回路装置の接続用電極とを前記第２の異方
性導電膜を介して電気的に接続する第３工程とを、含む
ことを特徴とする。A method of manufacturing a semiconductor device according to claim 5, wherein the connection electrode is provided on one side and the external connection electrode is provided on the other side of the substrate where the connection electrode does not exist on the one side. A first semiconductor integrated circuit device having a connection electrode formed on the other surface of the surface in contact with the substrate, and a first anisotropic conductive film disposed on the connection electrode of the substrate. A first step of disposing a second anisotropic conductive film on a connection electrode of the first semiconductor integrated circuit device, and a connection electrode of the substrate and the first semiconductor integrated circuit device on one surface side The second anisotropic conductive film, the second anisotropic conductive film, and the first semiconductor A second step of facing the substrate on which the integrated circuit device is arranged;
Electrically connecting a connection electrode of the first semiconductor integrated circuit device and a connection electrode of the second semiconductor integrated circuit device facing the connection electrode via the second anisotropic conductive film; The connection electrode of the substrate and the second electrode facing the connection electrode;
A third step of electrically connecting the connection electrode of the semiconductor integrated circuit device with the connection electrode via the second anisotropic conductive film.
【００２４】請求項５の半導体装置の製造方法に依れ
ば、基板上に第１の半導体集積回路装置すなわち子チッ
プ及び接続用の第１，第２の異方性導電膜を配置し、こ
れに第２の半導体集積回路装置すなわち親チップを対向
させ、子チップと親チップ間及び親チップと基板間とを
異方性導電膜を介して接続する。According to the method of manufacturing a semiconductor device of the fifth aspect, the first semiconductor integrated circuit device, that is, the child chip and the first and second anisotropic conductive films for connection are arranged on the substrate. Then, the second semiconductor integrated circuit device, that is, the parent chip is opposed to each other, and the child chip and the parent chip and between the parent chip and the substrate are connected via the anisotropic conductive film.
【００２５】これにより、親チップ、子チップ、基板の
相互接続が、単に圧着するだけで行われるから、リード
ワイヤーを不要とした、チップ・サイズド・パッケージ
ＣＳＰの一体化構成半導体装置を簡易な工程で形成する
ことができる。Thus, the interconnection of the parent chip, the child chip, and the substrate is performed simply by crimping, so that a lead-wire is not required, and the integrated semiconductor device of the chip-sized package CSP can be manufactured in a simple process. Can be formed.
【００２６】請求項６の半導体装置の製造方法は、一面
側に接続用電極が設けられ、他面側に外部接続用電極が
設けられた基板の接続用電極上に異方性導電膜を配置す
る第１工程と、一面側に接続用電極が形成された第１の
半導体集積回路装置の接続用電極と、一面側に、前記基
板の接続用電極及び前記第１の半導体集積回路装置の接
続用電極に対向するように接続用電極が設けられた第２
の半導体集積回路装置の前記第１の半導体集積回路装置
の接続用電極に対向するように設けられた接続用電極と
を、接合する第２工程と、前記他面側に外部接続用電極
が設けられた前記基板と、前記第１の半導体集積回路装
置が接合された前記第２の半導体集積回路装置とを前記
異方性導電膜を挟んで対向させる第３工程と、前記基板
の接続用電極とこれと対向する前記第２の半導体集積回
路装置の接続用電極とを前記異方性導電膜を介して電気
的に接続する第４工程とを、含むことを特徴とする。According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the anisotropic conductive film is disposed on the connection electrode of the substrate having the connection electrode provided on one side and the external connection electrode provided on the other side. A first step of connecting, a connection electrode of the first semiconductor integrated circuit device having a connection electrode formed on one surface side, and a connection of the connection electrode of the substrate and the first semiconductor integrated circuit device on one surface side Second electrode provided with a connection electrode so as to face the connection electrode
A second step of joining a connection electrode provided to face the connection electrode of the first semiconductor integrated circuit device of the first semiconductor integrated circuit device, and an external connection electrode provided on the other surface side. A third step of causing the substrate provided and the second semiconductor integrated circuit device to which the first semiconductor integrated circuit device is joined to face each other with the anisotropic conductive film interposed therebetween, and a connection electrode of the substrate. And a fourth step of electrically connecting the connection electrode of the second semiconductor integrated circuit device and the connection electrode facing the connection electrode via the anisotropic conductive film.
【００２７】請求項６の半導体装置の製造方法に依れ
ば、まず第１の半導体集積回路装置すなわち子チップと
第２の半導体集積装置すなわち親チップとを一体化し、
子チップを挟み込むように親チップと基板とを異方性導
電膜を介して電気的に接続する。According to the method of manufacturing a semiconductor device of the present invention, first, the first semiconductor integrated circuit device, ie, the child chip, and the second semiconductor integrated device, ie, the parent chip, are integrated,
The parent chip and the substrate are electrically connected via an anisotropic conductive film so as to sandwich the child chip.
【００２８】これにより、子チップと親チップとを接続
用電極で接続した後に、親チップと基板との接続は単に
圧着するだけで行われるから、リードワイヤーを不要と
した、チップ・サイズド・パッケージＣＳＰの一体化構
成半導体装置を簡易な工程で形成することができる。Thus, after the child chip and the parent chip are connected by the connection electrodes, the connection between the parent chip and the substrate is performed simply by crimping, so that a chip-sized package that eliminates the need for lead wires is provided. A semiconductor device having a CSP integrated structure can be formed in a simple process.
【００２９】[0029]
【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照して、順次説明する。図１は、本発明の
第１の実施の形態に係る、チップオンチップ方式による
一体化構成の半導体装置１０の構造を示す図である。Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a diagram showing a structure of a semiconductor device 10 having a chip-on-chip integrated structure according to a first embodiment of the present invention.
【００３０】図１において、第１の半導体集積回路装置
１１０は、子チップと称されるものであり、その一面側
に複数の配線パッド１１１が設けられ、そこに接続用電
極としての突起電極すなわちバンプ１１２が設けられ
る。In FIG. 1, a first semiconductor integrated circuit device 110 is referred to as a child chip. A plurality of wiring pads 111 are provided on one surface side of the first semiconductor integrated circuit device 110. A bump 112 is provided.
【００３１】第２の半導体集積回路装置１２０は、親チ
ップと称されるものであり、その一面側に複数の配線パ
ッド１２１が設けられ、そこに接続用電極としての突起
電極すなわちバンプ１２２が設けられる。このバンプ１
２２は、子チップ１１０のバンプ１１２と対向し、相互
に接続される。また、同じく一面側に複数の配線パッド
１２３が設けられ、そこに接続用電極としての突起電極
すなわちバンプ１２４が設けられる。このバンプ１２４
は、基板１３０と電気的に接続される。The second semiconductor integrated circuit device 120 is called a parent chip. A plurality of wiring pads 121 are provided on one surface of the second semiconductor integrated circuit device 120, and a protruding electrode or bump 122 as a connection electrode is provided thereon. Can be This bump 1
Reference numeral 22 faces the bumps 112 of the child chip 110 and is connected to each other. Similarly, a plurality of wiring pads 123 are provided on one surface side, and a bump electrode 124 as a connection electrode is provided there. This bump 124
Is electrically connected to the substrate 130.
【００３２】基板１３０は、一面側の所定の場所（中央
部分が好ましい）に子チップ１１０が設けられ、同じ面
の空いている場所例えば周辺部に複数の配線パッド１３
１が設けられ、そこに接続用電極としての突起電極すな
わちバンプ１３２が設けられる。このバンプ１３２は、
親チップ１２０のバンプ１２４と対向し、異方性導電膜
１４０を介して相互に接続されている。また、基板５３
０の他面側から、外部接続用半田バンプＢが導出され
る。The substrate 130 is provided with the sub-chips 110 at a predetermined location (preferably at the center) on one side, and a plurality of wiring pads 13 at a vacant location on the same side, for example, at the periphery.
1 are provided, and a bump electrode 132 as a connection electrode is provided thereon. This bump 132
It faces the bump 124 of the parent chip 120 and is connected to each other via an anisotropic conductive film 140. Also, the substrate 53
0, the solder bump B for external connection is led out from the other surface side.
【００３３】この異方性導電膜１４０は、接着性の樹脂
層とこの樹脂層中に散在された導電粒子から構成されて
いるものであり、正方形、長方形などの矩形とされその
中央部が子チップ１１０の外形に合わせて空白とされた
形状とされている。そして、異方性導電膜１４０は親チ
ップ１２０と基板１３０との間に挟まれ、バンプ１２４
とバンプ１３２とが向き合うようにして、対向させた状
態で加圧（或いは加圧および加熱）されている。したが
って、親チップ１２０のバンプ１２４と基板１３０のバ
ンプ１３２に挟まれた部分では、異方性導電膜１４０が
加圧（或いは加圧及び加熱）され、その部分の異方性導
電膜１４０に導電性が生じ、バンプ１２４とバンプ１３
２とが電気的に接続されている。The anisotropic conductive film 140 is composed of an adhesive resin layer and conductive particles scattered in the resin layer. The shape is blank according to the outer shape of the chip 110. The anisotropic conductive film 140 is sandwiched between the parent chip 120 and the substrate 130, and the bumps 124
The pressure (or pressurization and heating) is applied in such a manner that the and the bumps 132 face each other. Therefore, in the portion between the bump 124 of the parent chip 120 and the bump 132 of the substrate 130, the anisotropic conductive film 140 is pressurized (or pressurized and heated), and the anisotropic conductive film 140 in that portion is electrically conductive. And the bumps 124 and 13
2 are electrically connected.
【００３４】このように親チップ１２０と基板１３０と
の間の接続を異方性導電膜１４０を介して行うために、
バンプ１２４，１３２の寸法及び異方性導電膜１４０の
厚みなどは、子チップ１１０の厚みなどを考慮して決定
される。なお、バンプ１２４，１３２の寸法を子チップ
１１０の厚みを吸収できる程度の大き差に設定すること
等の手段により、異方性導電膜１４０を使用することな
く、電気的に接続することも可能である。As described above, the connection between the parent chip 120 and the substrate 130 is made through the anisotropic conductive film 140.
The dimensions of the bumps 124 and 132 and the thickness of the anisotropic conductive film 140 are determined in consideration of the thickness of the child chip 110 and the like. It is also possible to electrically connect the bumps 124 and 132 without using the anisotropic conductive film 140 by, for example, setting the size of the bumps 124 and 132 to a large difference capable of absorbing the thickness of the child chip 110. It is.
【００３５】そして、樹脂によりモールドして、最終的
にパッケージし、基板１３０の上に第１の半導体集積回
路装置すなわち子チップ１１０を載置し、さらにその子
チップ１１０の上に第２の半導体集積回路装置すなわち
親チップ１２０を搭載した、チップオンチップ方式の一
体化構成した半導体装置１０が形成されている。Then, the first semiconductor integrated circuit device, that is, the child chip 110 is mounted on the substrate 130 by molding with a resin and finally packaged, and further, the second semiconductor integrated circuit device is mounted on the child chip 110. A semiconductor device 10 integrated with a circuit device, that is, a chip-on-chip system, on which a parent chip 120 is mounted, is formed.
【００３６】なお、図１では、基板１３０の寸法が親チ
ップ１２０の寸法より若干大きく設定されるように示さ
れているが、基板１３０の寸法を親チップ１２０の寸法
に合わせて形成することなどは、任意になし得ることは
言うまでもない。Although FIG. 1 shows that the dimensions of the substrate 130 are set to be slightly larger than the dimensions of the parent chip 120, the dimensions of the substrate 130 may be adjusted to the dimensions of the parent chip 120. Needless to say, it can be done arbitrarily.
【００３７】このチップオンチップ方式の一体化構成し
た半導体装置１０は、基板１３０上の例えば中央部に寸
法の小さい第１の半導体集積回路装置すなわち子チップ
１１０を載置し、この子チップ１１０と寸法の大きい第
２の半導体集積回路装置すなわち親チップ１２０を積層
するように配置し、子チップ１１０と親チップ１２０間
及び親チップ１２０と基板１３０との電気的接続をバン
プ１１２，１２２，１２４，１３２および異方性電極１
４０を用いて行っている。In the integrated semiconductor device 10 of the chip-on-chip type, a first semiconductor integrated circuit device having a small size, that is, a child chip 110 is placed on, for example, a central portion of a substrate 130, and the child chip 110 and A second semiconductor integrated circuit device having a large dimension, that is, a parent chip 120 is arranged so as to be stacked, and electrical connections between the child chip 110 and the parent chip 120 and between the parent chip 120 and the substrate 130 are made by bumps 112, 122, 124,. 132 and anisotropic electrode 1
40.
【００３８】これにより、親チップ１２０とこれを搭載
する基板１３０との間のリードワイヤーが不要となり、
基板の寸法を小さくすることができるから、チップオン
チップ方式による一体化構成の半導体装置をチップ・サ
イズド・パッケージＣＳＰ可能となり、より小さく実装
することができる。This eliminates the need for lead wires between the parent chip 120 and the substrate 130 on which it is mounted,
Since the size of the substrate can be reduced, a semiconductor device having an integrated configuration by a chip-on-chip method can be chip-sized package CSP, and can be mounted smaller.
【００３９】また、子チップ１１０と親チップ１２０と
の電気的接続はバンプにて直接行い、親チップ１２０と
基板１３０との接続は異方性導電膜１４０を介して行う
から、バンプの形成が容易となり、またバンプ間の接続
も簡単に行うことができる。Further, the electrical connection between the child chip 110 and the parent chip 120 is made directly by bumps, and the connection between the parent chip 120 and the substrate 130 is made via an anisotropic conductive film 140. This facilitates connection between the bumps.
【００４０】図２は、本発明の第２の実施の形態に係
る、チップオンチップ方式による一体化構成の半導体装
置２０の構造を示す図である。FIG. 2 is a diagram showing a structure of a semiconductor device 20 having a chip-on-chip integrated structure according to a second embodiment of the present invention.
【００４１】図２において、図１の第１の実施の形態に
おける半導体装置と異なる点は、子チップ１１０と親チ
ップ１２０との接続を、バンプ同志直接に接続するのに
代えて、親チップ１２０と基板１３０との間の接続と同
様に、異方性導電膜１５０を介して行うように構成して
いる点である。その他の点は図１におけると同様であ
り、対応する箇所には同じ符号を付しており、再度の説
明は省略する。In FIG. 2, the difference from the semiconductor device of the first embodiment shown in FIG. 1 is that the connection between the child chip 110 and the parent chip 120 is not directly connected to the bumps but the parent chip 120. The structure is such that the connection is made via the anisotropic conductive film 150 as in the connection between the substrate and the substrate 130. Other points are the same as those in FIG. 1, and corresponding portions are denoted by the same reference numerals, and description thereof will not be repeated.
【００４２】この図２の第２の実施の形態においては、
子チップ１１０と親チップ１２０との接続及び親チップ
１２０と基板１３０との間の接続をともに異方性導電膜
１４０，１５０を介して行う。けれども、それらの接続
すべき間隔は異なっているから、子チップ１１０と親チ
ップ１２０との接続に関わる異方性導電膜１５０，バン
プ１１２及びバンプ１２２のそれぞれの寸法と、親チッ
プ１２０と基板１３０との接続に関わる異方性導電膜１
４０，バンプ１２４及びバンプ１３２のそれぞれの寸法
とは、同時に良好な接続状態が得られるように、それぞ
れ設定される。In the second embodiment shown in FIG.
Both the connection between the child chip 110 and the parent chip 120 and the connection between the parent chip 120 and the substrate 130 are made via the anisotropic conductive films 140 and 150. However, since the intervals to be connected are different, the dimensions of the anisotropic conductive film 150, the bumps 112, and the bumps 122 relating to the connection between the child chip 110 and the parent chip 120, and the dimensions of the parent chip 120 and the substrate 130 Conductive film 1 related to connection with
The dimensions of the bumps 40, the bumps 124, and the bumps 132 are set so that a good connection state can be obtained at the same time.
【００４３】これにより、第１の実施形態におけると同
様の効果が得られるとともに、さらに各バンプの形成が
容易となり、また接続すべき間隔の異なるバンプ間の接
続も簡単に行える。As a result, the same effects as in the first embodiment can be obtained, the formation of each bump is further facilitated, and the connection between bumps to be connected at different intervals can be easily performed.
【００４４】図３は、本発明の第３の実施の形態に係
り、チップオンチップ方式による一体化構成の半導体装
置１０の製造方法を示す図である。FIG. 3 is a view showing a method of manufacturing a semiconductor device 10 having an integrated structure by a chip-on-chip method according to a third embodiment of the present invention.
【００４５】図３において、各構成部品は図１の第１の
実施の形態におけると同様であり、対応する構成部品に
は同一の符号を付している。In FIG. 3, each component is the same as in the first embodiment of FIG. 1, and corresponding components are denoted by the same reference numerals.
【００４６】まず、一面側に配線パッド１３１とその上
にバンプ１３２を形成し、他面側に外部用半田バンプＢ
を形成した基板を用意する（図３（ａ））。First, a wiring pad 131 and a bump 132 are formed thereon on one side, and an external solder bump B is formed on the other side.
A substrate on which is formed is prepared (FIG. 3A).
【００４７】次に、この基板１３０の一面側のバンプ１
３２の存在しない略中央部に、基板１３０と接する面の
他面側に配線パッド１１１とその上にバンプ１１２を形
成した子チップ１１０を配置する。この時に、子チップ
１１０を接着剤により、基板１３０の所定の場所に固定
することが望ましい（図３（ｂ））。Next, the bumps 1 on one side of the substrate 130 are formed.
A wiring chip 111 and a sub chip 110 on which a bump 112 is formed are disposed on the other surface side of the surface in contact with the substrate 130 at a substantially central portion where the substrate 32 does not exist. At this time, it is desirable to fix the child chip 110 at a predetermined position on the substrate 130 with an adhesive (FIG. 3B).
【００４８】次に、基板１３０のバンプ１３２上に異方
性導電膜１４０を配置する（図３（ｃ））。なお、この
図３（ｂ）の工程と、図３（ｃ）の工程とは、順序が逆
でもよく、また同時に行うこともできる。Next, an anisotropic conductive film 140 is arranged on the bump 132 of the substrate 130 (FIG. 3C). Note that the step of FIG. 3B and the step of FIG. 3C may be performed in the reverse order, or may be performed simultaneously.
【００４９】次に、一面側に、基板１３０のバンプ１３
２及び子チップ１１０のバンプ１１２に対向するよう
に、配線パッド１２１とその上にバンプ１２２および配
線パッド１２３とその上にバンプ１２４を形成した親チ
ップ１２０を用意する。そして、親チップ１２０をその
バンプ１２２およびバンプ１２４が、それぞれ子チップ
１１０のバンプ１１２及び異方性導電膜１４０を挟んで
基板１３０のバンプ１３２に対向するように配置する
（図３（ｄ））。Next, the bump 13 of the substrate 130 is
A parent chip 120 having a wiring pad 121 and a bump 122 and a wiring pad 123 formed thereon and a bump 124 formed thereon is prepared so as to face the bump 112 of the second chip and the child chip 110. Then, the parent chip 120 is arranged such that the bumps 122 and 124 thereof are opposed to the bumps 132 of the substrate 130 with the bumps 112 and the anisotropic conductive film 140 of the child chip 110 interposed therebetween (FIG. 3D). .
【００５０】次に、親チップ１２０を対向させた状態
で、子チップ１１０及び基板１３０に向かって接近させ
ていき、親チップ１２０のバンプ１２２と子チップ１１
０のバンプ１１２とを当接させて接合する。これにより
親チップ１２０と子チップ１１０とが電気的に接続す
る。Next, with the parent chip 120 facing the child chip 110 and the substrate 130, the bumps 122 of the parent chip 120 and the child chip 11 are brought closer.
The bumps 112 are brought into contact with each other and joined. Thus, the parent chip 120 and the child chip 110 are electrically connected.
【００５１】このとき、親チップ１２０のバンプ１２４
と基板１３０のバンプ１３２との間隔が狭まり、その間
に配置されている異方性導電膜１４０が加圧圧縮され、
或いは必要に応じて同時に加熱されるから、バンプ１２
４とバンプ１３２との間は自動的に電気的に接続され
る。すなわち、親チップ１２０と基板１３０とが電気的
に接続される（図３（ｅ））。At this time, the bumps 124 of the parent chip 120
And the distance between the bumps 132 of the substrate 130 is reduced, and the anisotropic conductive film 140 disposed therebetween is pressed and compressed.
Alternatively, the bumps 12 are heated at the same time if necessary.
4 and the bump 132 are automatically electrically connected. That is, the parent chip 120 and the substrate 130 are electrically connected (FIG. 3E).
【００５２】最後に、樹脂によりモールドして、最終的
にパッケージし、チップオンチップ方式の一体化構成し
た半導体装置が形成される（図示は省略）。Finally, the semiconductor device is molded with resin and finally packaged to form a chip-on-chip type integrated semiconductor device (not shown).
【００５３】これにより、親チップ１２０とこれを搭載
する基板１３０との間の接続が、子チップ１１０と親チ
ップ１２０とをバンプ１１２、１２２間で接続するだけ
で、他の親チップ１２０と基板１３０との接続は単に圧
着するだけで行われるから、リードワイヤーを不要とし
た、チップ・サイズド・パッケージＣＳＰの一体化構成
半導体装置を簡易な工程で形成することができる。As a result, the connection between the parent chip 120 and the substrate 130 on which the parent chip 120 is mounted is made by merely connecting the child chip 110 and the parent chip 120 between the bumps 112 and 122, and connecting the other parent chip 120 to the substrate 130. Since the connection with 130 is performed simply by crimping, a semiconductor device integrated with a chip-sized package CSP that does not require a lead wire can be formed in a simple process.
【００５４】以上の、図３に示した本発明の第３の実施
の形態の一部を改変し、子チップ１１０と親チップ１２
０との接続をも、異方性導電膜を介して行うようにし
て、図２に示したようなチップオンチップ方式による一
体化構成の半導体装置２０を製造することができる。A modification of the third embodiment of the present invention shown in FIG.
The semiconductor device 20 having an integrated configuration by the chip-on-chip method as shown in FIG. 2 can be manufactured by connecting the semiconductor device 20 to the zero through the anisotropic conductive film.
【００５５】この製造方法を第４の実施の形態として説
明する。このチップオンチップ方式による一体化構成の
半導体装置２０の製造方法は、第３の実施の形態におい
て、図３（ｃ）の工程に、さらに子チップ１１０のバン
プ１１２上に第２の異方性導電膜１５０を配置する。This manufacturing method will be described as a fourth embodiment. In the manufacturing method of the semiconductor device 20 having the integrated structure by the chip-on-chip method, the third embodiment is different from the third embodiment in that the step of FIG. The conductive film 150 is provided.
【００５６】次に、図３（ｄ）の工程で、さらに、親チ
ップ１２０をそのバンプ１２２およびバンプ１２４が、
それぞれ異方性導電膜１５０を挟んで子チップ１１０の
バンプ１１２及び異方性導電膜１４０を挟んで基板１３
０のバンプ１３２に対向するように配置する。Next, in the step of FIG. 3D, the parent chip 120 is further fitted with its bumps 122 and 124.
The bumps 112 of the child chip 110 and the substrate 13 with the anisotropic conductive film 140 interposed therebetween.
It is arranged so as to face the 0 bump 132.
【００５７】次に、図３（ｅ）の工程で、親チップ１２
０を対向させた状態で、子チップ１１０及び基板１３０
に向かって接近させていく。そして、親チップ１２０の
バンプ１２２と子チップ１１０のバンプ１１２とをその
間に配置されている異方性導電膜１５０で、同様に親チ
ップ１２０のバンプ１２４と基板１３０のバンプ１３２
とをその間に配置されている異方性導電膜１４０で、加
圧圧縮（及び加熱）により自動的に電気的に接続され
る。すなわち、子チップ１１０と親チップ１２０、親チ
ップ１２０と基板１３０とが電気的に接続される。Next, in the step of FIG.
0 and the sub chip 110 and the substrate 130
Approach towards. Then, the bumps 124 of the parent chip 120 and the bumps 132 of the substrate 130 are similarly formed by the anisotropic conductive film 150 disposed between the bumps 122 of the parent chip 120 and the bumps 112 of the child chip 110.
Are electrically connected automatically by pressure compression (and heating) by an anisotropic conductive film 140 disposed therebetween. That is, the child chip 110 and the parent chip 120 are electrically connected, and the parent chip 120 and the substrate 130 are electrically connected.
【００５８】このように、基板１３０上に第１の半導体
集積回路装置すなわち子チップ１１０及び接続用の第
１，第２の異方性導電膜を配置し、これに第２の半導体
集積回路装置すなわち親チップを対向させ、子チップと
親チップ間及び親チップと基板間とを異方性導電膜を介
して接続する。As described above, the first semiconductor integrated circuit device, that is, the child chip 110 and the first and second anisotropic conductive films for connection are arranged on the substrate 130, and the second semiconductor integrated circuit device That is, the parent chips are opposed to each other, and the child chips and the parent chips and between the parent chips and the substrate are connected via the anisotropic conductive film.
【００５９】これにより、親チップ、子チップ、基板の
相互接続が、単に圧着するだけで行われるから、リード
ワイヤーを不要とした、チップ・サイズド・パッケージ
ＣＳＰの一体化構成半導体装置をより簡易な工程で形成
することができる。As a result, the interconnection of the parent chip, the child chip, and the substrate is performed simply by crimping, so that a semiconductor device integrated with a chip-sized package CSP that does not require a lead wire can be simplified. It can be formed in a process.
【００６０】図４は、本発明の第５の実施の形態に係
り、チップオンチップ方式による一体化構成の半導体装
置１０の製造方法を示す図である。FIG. 4 is a view showing a method of manufacturing a semiconductor device 10 having an integrated structure by a chip-on-chip method according to a fifth embodiment of the present invention.
【００６１】図４において、各構成部品は図１の第１の
実施の形態におけると同様であり、対応する構成部品に
は同一の符号を付している。In FIG. 4, each component is the same as in the first embodiment of FIG. 1, and corresponding components are denoted by the same reference numerals.
【００６２】まず、一面側に配線パッド１３１とその上
にバンプ１３２を形成し、他面側に外部用半田バンプＢ
を形成した基板１３０を用意する（図４（ａ））。First, a wiring pad 131 and a bump 132 are formed on one surface thereof, and an external solder bump B is formed on the other surface.
A substrate 130 on which is formed is prepared (FIG. 4A).
【００６３】次に、一面側に配線パッド１１１とその上
にバンプ１１２が形成された子チップ１１０のバンプ１
１２と、一面側に、基板１３０の配線パッド１１１とそ
の上に形成されたバンプ１１２及び子チップ１１０のバ
ンプ１１２に対向するように、配線パッド１２１とその
上に形成されたバンプ１２２及び配線パッド１２３とそ
の上に形成されたバンプ１２４が設けられた親チップ１
２０のバンプ１２２とを、接合する（図４（ｂ））。Next, the bump 1 of the child chip 110 having the wiring pad 111 on one side and the bump 112 formed thereon is provided.
12 and, on one side, a wiring pad 121 and a bump 122 and a wiring pad formed thereon so as to face the wiring pad 111 of the substrate 130, the bump 112 formed thereon, and the bump 112 of the child chip 110. Parent chip 1 provided with 123 and bumps 124 formed thereon
The 20 bumps 122 are joined (FIG. 4B).
【００６４】次に、一面側に配線パッド１３１とその上
に形成されたバンプ１３２が設けられ、他面側に外部接
続用半田バンプＢが設けられた基板１３０のバンプ１３
２上に異方性導電膜１４０を配置する（図４（ｃ））。
なお、図４（ｂ）の工程と図４（ｃ）の工程の順序は、
逆でもかまわない。Next, the bumps 13 on the substrate 130 on which the wiring pads 131 and the bumps 132 formed thereon are provided on one side and the solder bumps B for external connection are provided on the other side.
An anisotropic conductive film 140 is disposed on the substrate 2 (FIG. 4C).
The order of the steps in FIG. 4B and the steps in FIG.
The reverse is also acceptable.
【００６５】次に、他面側に外部接続用半田バンプＢが
設けられた基板１３０のバンプ１３２と、子チップ１１
０が接合された親チップ１２０のバンプ１２４とを異方
性導電膜１４０を挟んで対向させる（図４（ｄ））。Next, the bump 132 of the substrate 130 provided with the solder bump B for external connection on the other surface, and the sub chip 11
The bumps 124 of the parent chip 120 to which the “0” is bonded are opposed to each other with the anisotropic conductive film 140 interposed therebetween (FIG. 4D).
【００６６】次に、この対向させた状態で、親チップ１
２０を基板１３０に向かって接近させていき、親チップ
１２０に接合されている子チップ１１０を基板１３０に
当接させる。Next, the parent chip 1
20 is approached toward the substrate 130, and the child chip 110 bonded to the parent chip 120 is brought into contact with the substrate 130.
【００６７】このとき、親チップ１２０のバンプ１２４
と基板１３０のバンプ１３２との間隔が狭まり、その間
に配置されている異方性導電膜１４０が加圧圧縮され、
或いは必要に応じて同時に加熱されるから、バンプ１２
４とバンプ１３２との間は自動的に電気的に接続され
る。すなわち、親チップ１２０と基板１３０とが電気的
に接続される（図４（ｅ））。At this time, the bumps 124 of the parent chip 120
And the distance between the bumps 132 of the substrate 130 is reduced, and the anisotropic conductive film 140 disposed therebetween is pressed and compressed.
Alternatively, the bumps 12 are heated at the same time if necessary.
4 and the bump 132 are automatically electrically connected. That is, the parent chip 120 and the substrate 130 are electrically connected (FIG. 4E).
【００６８】最後に、樹脂によりモールドして、最終的
にパッケージし、チップオンチップ方式の一体化構成し
た半導体装置が形成される（図示は省略）。Finally, the semiconductor device is molded with resin and finally packaged to form a chip-on-chip integrated semiconductor device (not shown).
【００６９】このように、まず子チップ１１０と親チッ
プ１２０とを一体化し、子チップを挟み込むように親チ
ップ１２０と基板１３０とを異方性導電膜１４０を介し
て電気的に接続する。As described above, first, the child chip 110 and the parent chip 120 are integrated, and the parent chip 120 and the substrate 130 are electrically connected via the anisotropic conductive film 140 so as to sandwich the child chip.
【００７０】これにより、子チップ１１０と親チップ１
２０とをバンプ１１２，１２２間で接続した後に、親チ
ップ１２０と基板１３０との接続は単に圧着するだけで
行われるから、リードワイヤーを不要とした、チップ・
サイズド・パッケージＣＳＰの一体化構成半導体装置を
簡易な工程で形成することができる。Thus, the child chip 110 and the parent chip 1
20 is connected between the bumps 112 and 122, and then the connection between the parent chip 120 and the substrate 130 is performed simply by pressure bonding.
A semiconductor device having an integrated configuration of the size package CSP can be formed in a simple process.
【００７１】[0071]
【発明の効果】本発明の請求項１記載の半導体装置に依
れば、基板上の例えば中央部に寸法の小さい第１の半導
体集積回路装置すなわち子チップを載置し、この子チッ
プと寸法の大きい第２の半導体集積回路装置すなわち親
チップを積層するよう配置し、子チップと親チップ間及
び親チップと基板との電気的接続を接続用電極を用いて
行う。According to the semiconductor device of the first aspect of the present invention, a first semiconductor integrated circuit device having a small size, that is, a child chip is mounted on, for example, a central portion of a substrate, and the child chip and the size are mounted. The second semiconductor integrated circuit device having a large size, that is, the parent chip is arranged to be stacked, and electrical connection between the child chip and the parent chip and between the parent chip and the substrate are performed using the connection electrodes.
【００７２】これにより、親チップである第２の半導体
集積回路装置とこれを搭載する基板との間のリードワイ
ヤーが不要となり、基板の寸法を小さくすることができ
るから、チップオンチップ方式による一体化構成の半導
体装置をチップ・サイズド・パッケージＣＳＰ可能とな
り、より小さく実装することができる。This eliminates the need for lead wires between the second semiconductor integrated circuit device as the parent chip and the substrate on which it is mounted, and reduces the size of the substrate. The semiconductor device having the integrated configuration can be made into a chip-sized package CSP, and can be mounted smaller.
【００７３】本発明の請求項２記載の半導体装置では、
請求項１記載の半導体装置が奏する機能に加えて、子チ
ップと親チップとの電気的接続は接続用電極にて直接行
い、親チップと基板との接続は異方性導電膜を介して行
う。In the semiconductor device according to the second aspect of the present invention,
In addition to the function of the semiconductor device according to claim 1, the electrical connection between the child chip and the parent chip is made directly by the connection electrode, and the connection between the parent chip and the substrate is made via the anisotropic conductive film. .
【００７４】これにより、接続用電極の形成が容易とな
り、また接続すべき間隔の異なる接続用電極間の接続も
簡単に行える。As a result, the formation of the connection electrodes is facilitated, and the connection between the connection electrodes having different intervals to be connected can be easily performed.
【００７５】本発明の請求項３記載の半導体装置に依れ
ば、請求項１記載の半導体装置が奏する機能に加えて、
すべての接続用電極間の電気的接続を異方性導電膜を介
して行う。According to the semiconductor device of the third aspect of the present invention, in addition to the function of the semiconductor device of the first aspect,
Electrical connection between all connection electrodes is performed via an anisotropic conductive film.
【００７６】これにより、さらに接続用電極の形成が容
易となり、また接続すべき間隔の異なる接続用電極間の
接続も簡単に行える。Thus, the formation of the connection electrodes is further facilitated, and the connection between the connection electrodes having different intervals to be connected can be easily performed.
【００７７】本発明の請求項４の半導体装置の製造方法
に依れば、基板上に第１の半導体集積回路装置すなわち
子チップ及び接続用の異方性導電膜を配置し、これに第
２の半導体集積回路装置すなわち親チップを対向させ、
子チップと親チップとを接続用電極で接続し、親チップ
と基板とを異方性導電膜を介して接続する。According to the semiconductor device manufacturing method of the fourth aspect of the present invention, the first semiconductor integrated circuit device, that is, the child chip and the anisotropic conductive film for connection are arranged on the substrate, Semiconductor integrated circuit device, that is, the parent chip is opposed,
The child chip and the parent chip are connected by connection electrodes, and the parent chip and the substrate are connected via an anisotropic conductive film.
【００７８】これにより、親チップである第２の半導体
集積回路装置とこれを搭載する基板との間の接続が、子
チップと親チップとを接続用電極で接続するだけで、他
の親チップと基板との接続は単に圧着するだけで行われ
るから、リードワイヤーを不要とした、チップ・サイズ
ド・パッケージＣＳＰの一体化構成半導体装置を簡易な
工程で形成することができる。Thus, the connection between the second semiconductor integrated circuit device, which is the parent chip, and the substrate on which the second semiconductor integrated circuit device is mounted is made by simply connecting the child chip and the parent chip with the connection electrodes, and connecting the other parent chip with the other chip. Since the connection between the semiconductor device and the substrate is performed simply by press-bonding, a semiconductor device integrated with the chip-sized package CSP and requiring no lead wire can be formed by a simple process.
【００７９】本発明の請求項５の半導体装置の製造方法
に依れば、基板上に第１の半導体集積回路装置すなわち
子チップ及び接続用の第１，第２の異方性導電膜を配置
し、これに第２の半導体集積回路装置すなわち親チップ
を対向させ、子チップと親チップ間及び親チップと基板
間とを異方性導電膜を介して接続する。According to the method of manufacturing a semiconductor device of the fifth aspect of the present invention, the first semiconductor integrated circuit device, that is, the child chip and the first and second anisotropic conductive films for connection are arranged on the substrate. Then, the second semiconductor integrated circuit device, that is, the parent chip is made to face this, and the child chip and the parent chip and between the parent chip and the substrate are connected via the anisotropic conductive film.
【００８０】これにより、親チップ、子チップ、基板の
相互接続が、単に圧着するだけで行われるから、リード
ワイヤーを不要とした、チップ・サイズド・パッケージ
ＣＳＰの一体化構成半導体装置を簡易な工程で形成する
ことができる。Thus, the interconnection of the parent chip, the child chip, and the substrate is performed simply by crimping, so that the lead-wire is not required, and the integrated semiconductor device of the chip-sized package CSP can be manufactured in a simple process. Can be formed.
【００８１】本発明の請求項６の半導体装置の製造方法
に依れば、まず第１の半導体集積回路装置すなわち子チ
ップと第２の半導体集積装置すなわち親チップとを一体
化し、子チップを挟み込むように親チップと基板とを異
方性導電膜を介して電気的に接続する。According to the method of manufacturing a semiconductor device of the present invention, first, the first semiconductor integrated circuit device, that is, the child chip, and the second semiconductor integrated device, that is, the parent chip are integrated, and the child chip is sandwiched. Thus, the parent chip and the substrate are electrically connected via the anisotropic conductive film.
【００８２】これにより、子チップと親チップとを接続
用電極で接続した後に、親チップと基板との接続は単に
圧着するだけで行われるから、リードワイヤーを不要と
した、チップ・サイズド・パッケージＣＳＰの一体化構
成半導体装置を簡易な工程で形成することができる。Thus, after the child chip and the parent chip are connected by the connection electrodes, the connection between the parent chip and the substrate is performed simply by crimping, so that a chip-sized package that does not require a lead wire is provided. A semiconductor device having a CSP integrated structure can be formed in a simple process.
【図１】本発明の第１の実施の形態に係る半導体装置の
構造を示す図。FIG. 1 is a diagram showing a structure of a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第２の実施の形態に係る半導体装置の
構造を示す図。FIG. 2 is a diagram showing a structure of a semiconductor device according to a second embodiment of the present invention.
【図３】本発明の第３の実施の形態に係る半導体装置の
製造方法を示す図。FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
【図４】本発明の第５の実施の形態に係る半導体装置の
製造方法を示す図。FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.
【図５】従来の一体化構成の半導体装置を示す図。FIG. 5 is a diagram showing a conventional semiconductor device having an integrated configuration.
１１０ 第１の半導体集積回路装置：子チップ １２０ 第２の半導体集積回路装置：親チップ １３０ 基板 １４０，１５０ 異方性導電膜 １１２，１２２、１２４，１３２ バンプ 110 first semiconductor integrated circuit device: child chip 120 second semiconductor integrated circuit device: parent chip 130 substrate 140, 150 anisotropic conductive film 112, 122, 124, 132 bump
Claims (6)
と、 この基板の接続用電極が設けられた面であって該接続用
電極の存在しない部分に配置され、この基板と接する面
の他面側に接続用電極が形成された第１の半導体集積回
路装置と、 一面側に、前記基板の接続用電極及び前記第１の半導体
集積回路装置の接続用電極に対向するように接続用電極
が設けられた第２の半導体集積回路装置と、 を備え、一体化構成されたことを特徴とする半導体装
置。1. A substrate provided with a connection electrode on one side, and a surface of the substrate provided with the connection electrode, which is disposed in a portion where the connection electrode does not exist and which is in contact with the substrate. A first semiconductor integrated circuit device having a connection electrode formed on the other surface; and a connection electrode formed on one surface facing the connection electrode of the substrate and the connection electrode of the first semiconductor integrated circuit device. And a second semiconductor integrated circuit device provided with electrodes, wherein the semiconductor device is integrated.
に外部接続用電極が設けられた基板と、 この基板の接続用電極が設けられた面であって該接続用
電極の存在しない部分に配置され、この基板と接する面
の他面側に接続用電極が形成された第１の半導体集積回
路装置と、 一面側に、前記基板の接続用電極及び前記第１の半導体
集積回路装置の接続用電極に対向するように接続用電極
が設けられた第２の半導体集積回路装置と、 前記基板の接続用電極と、この基板の接続用電極と対向
する前記第２の半導体集積回路装置の接続用電極との間
に介在するように設けられた異方性導電膜と、 を備え、一体化構成されたことを特徴とする半導体装
置。2. A substrate having a connection electrode provided on one surface side and an external connection electrode provided on the other surface, and a surface of the substrate provided with the connection electrode, wherein the connection electrode is provided. A first semiconductor integrated circuit device arranged on a portion not to be contacted and having a connection electrode formed on the other surface side of the surface in contact with the substrate; a connection electrode of the substrate and the first semiconductor integrated circuit formed on one surface side A second semiconductor integrated circuit device provided with a connection electrode facing the connection electrode of the device; a connection electrode of the substrate; and the second semiconductor integrated circuit facing the connection electrode of the substrate. And an anisotropic conductive film provided so as to be interposed between the device and a connection electrode of the device.
に外部接続用電極が設けられた基板と、 この基板の接続用電極が設けられた面であって該接続用
電極の存在しない部分に配置され、この基板と接する面
の他面側に接続用電極が形成された第１の半導体集積回
路装置と、 一面側に、前記基板の接続用電極及び前記第１の半導体
集積回路装置の接続用電極に対向するように接続用電極
が設けられた第２の半導体集積回路装置と、 前記基板の接続用電極及び第１の半導体集積回路装置の
接続用電極と、この基板の接続用電極及び前記第１の半
導体集積回路装置の接続用電極と対向する前記第２の半
導体集積回路装置の接続用電極との間に介在するように
それぞれ設けられた異方性導電膜と、 を備え、一体化構成されたことを特徴とする半導体装
置。3. A substrate provided with a connection electrode on one surface side and an external connection electrode provided on the other surface; and a surface of the substrate provided with the connection electrode, wherein the connection electrode is provided. A first semiconductor integrated circuit device arranged on a portion not to be contacted and having a connection electrode formed on the other surface side of the surface in contact with the substrate; a connection electrode of the substrate and the first semiconductor integrated circuit formed on one surface side A second semiconductor integrated circuit device provided with a connection electrode facing the connection electrode of the device; a connection electrode of the substrate and a connection electrode of the first semiconductor integrated circuit device; and connection of the substrate And an anisotropic conductive film provided between the connection electrode of the first semiconductor integrated circuit device and the connection electrode of the second semiconductor integrated circuit device facing the connection electrode. Semiconductor, characterized by being integrated and configured Apparatus.
に外部接続用電極が設けられた基板の前記一面側の前記
接続用電極の存在しない部分に、前記基板と接する面の
他面側に接続用電極が形成された第１の半導体集積回路
装置を配置するとともに、前記基板の接続用電極上に異
方性導電膜を配置する第１工程と、 一面側に、前記基板の接続用電極及び前記第１の半導体
集積回路装置の接続用電極に対向するように接続用電極
が設けられた第２の半導体集積回路装置を、前記異方性
導電膜及び前記第１の半導体集積回路装置を配置した基
板と対向させる第２工程と、 前記第１の半導体集積回路装置の接続用電極とこれと対
向する前記第２の半導体集積回路装置の接続用電極とを
電気的に接続するとともに、前記基板の接続用電極とこ
れと対向する前記第２の半導体集積回路装置の接続用電
極とを前記異方性導電膜を介して電気的に接続する第３
工程と、 を含むことを特徴とする半導体装置の製造方法。4. A substrate provided with a connection electrode on one surface side and an external connection electrode on the other surface side, on a portion of the substrate where the connection electrode does not exist on the one surface side, and on a surface in contact with the substrate. A first step of arranging a first semiconductor integrated circuit device having connection electrodes formed on one surface side and arranging an anisotropic conductive film on the connection electrodes of the substrate; A second semiconductor integrated circuit device provided with a connection electrode so as to face the connection electrode and the connection electrode of the first semiconductor integrated circuit device; A second step of facing the substrate on which the circuit device is arranged; and electrically connecting the connection electrode of the first semiconductor integrated circuit device and the connection electrode of the second semiconductor integrated circuit device facing the connection electrode. With the connection electrode of the substrate and facing it Third electrically connecting that the connection electrode of the second semiconductor integrated circuit device via the anisotropic conductive film
A method for manufacturing a semiconductor device, comprising:
に外部接続用電極が設けられた基板の前記一面側の前記
接続用電極の存在しない部分に、前記基板と接する面の
他面側に接続用電極が形成された第１の半導体集積回路
装置を配置するとともに、前記基板の接続用電極上に第
１の異方性導電膜を配置し、前記第１の半導体集積回路
装置の接続用電極上に第２の異方性導電膜を配置する第
１工程と、 一面側に、前記基板の接続用電極及び前記第１の半導体
集積回路装置の接続用電極に対向するように接続用電極
が設けられた第２の半導体集積回路装置を、前記第１の
異方性導電膜、前記第２の異方性導電膜及び前記第１の
半導体集積回路装置を配置した基板と対向させる第２工
程と、 前記第１の半導体集積回路装置の接続用電極とこれと対
向する前記第２の半導体集積回路装置の接続用電極とを
前記第２の異方性導電膜を介して電気的に接続するとと
もに、前記基板の接続用電極とこれと対向する前記第２
の半導体集積回路装置の接続用電極とを前記第２の異方
性導電膜を介して電気的に接続する第３工程と、 を含むことを特徴とする半導体装置の製造方法。5. A substrate provided with a connection electrode on one surface side and an external connection electrode on the other surface side, on a portion of the substrate on which the connection electrode does not exist on the one surface side, other than a surface in contact with the substrate. A first semiconductor integrated circuit device having a connection electrode formed on a surface side, and a first anisotropic conductive film disposed on the connection electrode of the substrate; A first step of arranging a second anisotropic conductive film on the connection electrode of (a), and, on one surface side, facing the connection electrode of the substrate and the connection electrode of the first semiconductor integrated circuit device. A second semiconductor integrated circuit device provided with a connection electrode is opposed to a substrate on which the first anisotropic conductive film, the second anisotropic conductive film, and the first semiconductor integrated circuit device are arranged. A second process to be performed, a connection electrode of the first semiconductor integrated circuit device, Thereby connecting the connection electrode of the second semiconductor integrated circuit device the second anisotropic conductive film electrically through to the second opposite connecting electrodes and therewith of the substrate
A third step of electrically connecting the connection electrode of the semiconductor integrated circuit device with the connection electrode via the second anisotropic conductive film.
に外部接続用電極が設けられた基板の接続用電極上に異
方性導電膜を配置する第１工程と、 一面側に接続用電極が形成された第１の半導体集積回路
装置の接続用電極と、一面側に、前記基板の接続用電極
及び前記第１の半導体集積回路装置の接続用電極に対向
するように接続用電極が設けられた第２の半導体集積回
路装置の前記第１の半導体集積回路装置の接続用電極に
対向するように設けられた接続用電極とを、接合する第
２工程と、 前記他面側に外部接続用電極が設けられた前記基板と、
前記第１の半導体集積回路装置が接合された前記第２の
半導体集積回路装置とを前記異方性導電膜を挟んで対向
させる第３工程と、 前記基板の接続用電極とこれと対向する前記第２の半導
体集積回路装置の接続用電極とを前記異方性導電膜を介
して電気的に接続する第４工程と、 を含むことを特徴とする半導体装置の製造方法。6. A first step of disposing an anisotropic conductive film on a connection electrode of a substrate having a connection electrode provided on one surface side and an external connection electrode provided on the other surface side; A connection electrode of the first semiconductor integrated circuit device on which the connection electrode is formed, and a connection electrode on one side facing the connection electrode of the substrate and the connection electrode of the first semiconductor integrated circuit device. A second step of joining a connection electrode provided to face the connection electrode of the first semiconductor integrated circuit device of the second semiconductor integrated circuit device provided with the electrode; The substrate provided with external connection electrodes,
A third step of opposing the second semiconductor integrated circuit device to which the first semiconductor integrated circuit device is bonded, with the anisotropic conductive film interposed therebetween; and a connection electrode of the substrate and the opposing electrode. A fourth step of electrically connecting a connection electrode of the second semiconductor integrated circuit device with the connection electrode via the anisotropic conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35182299A JP3815933B2 (en) | 1999-12-10 | 1999-12-10 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35182299A JP3815933B2 (en) | 1999-12-10 | 1999-12-10 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001168270A true JP2001168270A (en) | 2001-06-22 |
| JP3815933B2 JP3815933B2 (en) | 2006-08-30 |
Family
ID=18419856
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35182299A Expired - Fee Related JP3815933B2 (en) | 1999-12-10 | 1999-12-10 | Semiconductor device and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3815933B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005034238A1 (en) * | 2003-10-01 | 2005-04-14 | Koninklijke Philips Electronics, N.V. | Electrical shielding in stacked dies by using conductive die attach adhesive |
| US7138706B2 (en) | 2002-06-25 | 2006-11-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing the same |
| CN102301467A (en) * | 2008-12-30 | 2011-12-28 | 英特尔公司 | Removable Package Underside Device Attach |
| US8304877B2 (en) | 2009-01-06 | 2012-11-06 | Elpida Memory, Inc. | Semiconductor device |
| US8748229B2 (en) | 2008-06-11 | 2014-06-10 | Fujitsu Semiconductor Limited | Manufacturing method including deformation of supporting board to accommodate semiconductor device |
| US8981574B2 (en) | 2012-12-20 | 2015-03-17 | Samsung Electronics Co., Ltd. | Semiconductor package |
| JP2015230990A (en) * | 2014-06-05 | 2015-12-21 | 株式会社日立製作所 | Power semiconductor device and resin-sealed motor |
-
1999
- 1999-12-10 JP JP35182299A patent/JP3815933B2/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7138706B2 (en) | 2002-06-25 | 2006-11-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing the same |
| WO2005034238A1 (en) * | 2003-10-01 | 2005-04-14 | Koninklijke Philips Electronics, N.V. | Electrical shielding in stacked dies by using conductive die attach adhesive |
| US8748229B2 (en) | 2008-06-11 | 2014-06-10 | Fujitsu Semiconductor Limited | Manufacturing method including deformation of supporting board to accommodate semiconductor device |
| CN102301467A (en) * | 2008-12-30 | 2011-12-28 | 英特尔公司 | Removable Package Underside Device Attach |
| JP2012514333A (en) * | 2008-12-30 | 2012-06-21 | インテル・コーポレーション | Removable device attachment on the bottom of the package |
| US8304877B2 (en) | 2009-01-06 | 2012-11-06 | Elpida Memory, Inc. | Semiconductor device |
| US8497576B2 (en) | 2009-01-06 | 2013-07-30 | Elpida Memory, Inc. | Semiconductor device |
| US8981574B2 (en) | 2012-12-20 | 2015-03-17 | Samsung Electronics Co., Ltd. | Semiconductor package |
| US9633973B2 (en) | 2012-12-20 | 2017-04-25 | Samsung Electronics Co., Ltd. | Semiconductor package |
| JP2015230990A (en) * | 2014-06-05 | 2015-12-21 | 株式会社日立製作所 | Power semiconductor device and resin-sealed motor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3815933B2 (en) | 2006-08-30 |
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