JP2963952B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2963952B2 JP2963952B2 JP4309425A JP30942592A JP2963952B2 JP 2963952 B2 JP2963952 B2 JP 2963952B2 JP 4309425 A JP4309425 A JP 4309425A JP 30942592 A JP30942592 A JP 30942592A JP 2963952 B2 JP2963952 B2 JP 2963952B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- lead
- semiconductor chip
- semiconductor device
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
チップ上リード配線型パッケージの半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device of a lead-on-chip type package.
【０００２】[0002]
【従来の技術】従来のチップ上リード配線型パッケージ
（ＬＯＣパッケージ）の半導体装置は、図３（ａ）及び
（ｂ）にそれぞれ縦断面図と横断面図を示すように半導
体チップ１と、半導体チップ１上を通るリード配線２
と、半導体チップ１とリード配線２を接着する接着フィ
ルム３を有している。リード配線２を接着フィルム３を
用いて半導体チップ１上に接着し、半導体チップ１のボ
ンディングパッド１ａとリード配線２をボンディングワ
イヤ４により接続し、モールド樹脂５で封止を行う。こ
れにより、リードフレーム上に半導体チップを搭載し、
この半導体チップの周辺部に設けたリードにボンディン
グワイヤを用いて電気接続を行う構成の半導体装置より
も、同一のパッケージサイズでより大きな半導体チップ
が搭載可能となる。2. Description of the Related Art A conventional semiconductor device of an on-chip lead wiring type package (LOC package) has a semiconductor chip 1 and a semiconductor chip 1 as shown in FIGS. 3 (a) and 3 (b). Lead wiring 2 passing over chip 1
And an adhesive film 3 for bonding the semiconductor chip 1 and the lead wiring 2. The lead wiring 2 is adhered on the semiconductor chip 1 using the adhesive film 3, the bonding pad 1 a of the semiconductor chip 1 is connected to the lead wiring 2 by the bonding wire 4, and sealing is performed with the mold resin 5. As a result, the semiconductor chip is mounted on the lead frame,
A larger semiconductor chip can be mounted with the same package size as compared to a semiconductor device having a configuration in which electrical connections are made to the leads provided on the periphery of the semiconductor chip using bonding wires.
【０００３】[0003]
【発明が解決しようとする課題】この従来のチップ上リ
ード配線型パッケージの半導体装置は、リード配線２が
半導体チップ１上を通るため、半導体チップの周辺にリ
ードフレームを設けた半導体装置よりもリード配線２が
長くなる。このため、各リード配線２に寄生する容量が
大きくなり、半導体装置の動作速度の低下等種々の問題
が生じる。この寄生容量を小さくするため、リード配線
を細くしたり薄くしたりすることが考えられるが、リー
ド配線の強度が低下されるという問題がある。本発明の
目的は、リード配線における寄生容量の低減を図ったチ
ップ上リード配線型パッケージの半導体装置を提供する
ことにある。In this conventional semiconductor device of a lead-on-chip type wiring package, the lead wiring 2 passes over the semiconductor chip 1, so that the lead device is more lead-free than a semiconductor device provided with a lead frame around the semiconductor chip. The wiring 2 becomes longer. For this reason, the parasitic capacitance of each lead wire 2 increases, and various problems such as a decrease in the operation speed of the semiconductor device occur. To reduce the parasitic capacitance, it is conceivable to make the lead wiring thinner or thinner, but there is a problem that the strength of the lead wiring is reduced. An object of the present invention is to provide a semiconductor device of a lead-on-chip type package in which a parasitic capacitance in a lead wiring is reduced.
【０００４】[0004]
【課題を解決するための手段】本発明は、半導体チップ
上に、絶縁フィルム表面に細い配線を一体に形成した配
線フィルムを配設し、前記半導体チップと前記配線フィ
ルム、及び前記配線フィルムと前記リード配線とをそれ
ぞれボンディングワイヤによって電気的に接続した構成
とする。Means for Solving the Problems The present invention, on a semiconductor chip, a thin wire in the insulating film surface is disposed a wiring film formed integrally, the wiring and the semiconductor chip Fi
And the wiring film and the lead wiring
Each is electrically connected by a bonding wire .
【０００５】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。図１（ａ）及び（ｂ）は本発明の第１実施例の半導
体装置の縦断面図及び横断面図である。図において、半
導体チップ１には多数個のボンディングパッド１ａが配
列形成される。この半導体チップ１の表面上の周辺部に
はリード配線２の一部が延設され、接着フィルム３によ
り半導体チップ１の表面に接着する。また、前記リード
配線２で挟まれる領域の半導体チップ１の表面上には配
線フィルム６を接着してある。この配線フィルム６は、
絶縁性のフィルム６ａの表面に印刷技術等によって薄膜
でかつ細幅の配線６ｂを一体的に形成したものである。
そして、この配線フィルム６を介して前記リード配線２
とボンディングパッド１ａとをボンディングワイヤ４に
より相互に電気接続し、更に全体をモールド樹脂５で封
止を行っている。Next, the present invention will be described with reference to the drawings. 1A and 1B are a longitudinal sectional view and a transverse sectional view of a semiconductor device according to a first embodiment of the present invention. In the figure, a large number of bonding pads 1a are formed on a semiconductor chip 1 in an array. A part of the lead wiring 2 is extended to a peripheral portion on the surface of the semiconductor chip 1 and adheres to the surface of the semiconductor chip 1 by the adhesive film 3. A wiring film 6 is adhered on the surface of the semiconductor chip 1 in a region sandwiched between the lead wires 2. This wiring film 6
A thin and narrow wiring 6b is integrally formed on the surface of the insulating film 6a by a printing technique or the like.
Then, the lead wiring 2 is provided through the wiring film 6.
And the bonding pad 1a are electrically connected to each other by a bonding wire 4, and the whole is sealed with a mold resin 5.
【０００６】したがって、この構成の半導体装置では、
半導体チップ１の表面に延在されるリード配線の一部と
して配線フィルム６を用いており、この種の配線フィル
ムは配線６ｂの幅を細くしても絶縁性フィルムによって
その強度が充分高いものとすることができる。したがっ
て、配線フィルム６によって寄生容量を低減することが
できる一方で、配線の強度を高め、信頼性を向上するこ
とができる。特にこの実施例では、ボンディングパッド
１ａが半導体チップ１の長辺方向の片側に配置されてお
り、この場合ボンディングパッドが存在しない側のリー
ド配線が長くなるが、配線フィルム６を用いることで寄
生容量を小さくしている。Therefore, in the semiconductor device having this configuration,
The wiring film 6 is used as a part of the lead wiring extending on the surface of the semiconductor chip 1. This type of wiring film has a sufficiently high strength due to the insulating film even if the width of the wiring 6b is reduced. can do. Therefore, while the parasitic capacitance can be reduced by the wiring film 6, the strength of the wiring can be increased and the reliability can be improved. Particularly, in this embodiment, the bonding pad 1a is arranged on one side in the long side direction of the semiconductor chip 1. In this case, the lead wiring on the side where no bonding pad is present becomes longer. Is smaller.
【０００７】図２は本発明の第２実施例を示しており、
同図（ａ）及び（ｂ）はその縦断面図及び横断面図であ
る。なお、図１の実施例と等価な部分には同一符号を付
してある。この実施例ではボンディングパッド１ａが半
導体チップ１の短辺方向の中央部に配置されたチップの
例である。この場合、半導体チップ１のコーナー部にお
けるリード配線２が長くなるため、ボンディングパッド
１ａを挟むように半導体チップ１の表面に２枚の配線フ
ィルム６を接着し、この配線フィルム６を利用してボン
ディングパッド１ａとリード配線２との電気接続を行っ
ている。FIG. 2 shows a second embodiment of the present invention.
FIGS. 7A and 7B are a longitudinal sectional view and a transverse sectional view, respectively. Note that parts equivalent to those in the embodiment of FIG. 1 are denoted by the same reference numerals. This embodiment is an example of a chip in which the bonding pads 1a are arranged at the center of the semiconductor chip 1 in the short side direction. In this case, since the lead wires 2 at the corners of the semiconductor chip 1 become longer, two wiring films 6 are adhered to the surface of the semiconductor chip 1 so as to sandwich the bonding pad 1a, and bonding is performed using the wiring film 6. The electrical connection between the pad 1a and the lead wiring 2 is made.
【０００８】この実施例においても、配線フィルムを用
いることで、配線６ｂを細く薄くして寄生容量を小さく
し、かつ一方で充分な強度を確保して信頼性を向上する
ことができる。なお、配線フィルムは前記各実施例の形
状，構造に関わらず種々のものが利用できることは言う
までもない。Also in this embodiment, by using a wiring film, the wiring 6b can be made thinner and thinner to reduce the parasitic capacitance, while at the same time ensuring sufficient strength to improve reliability. It goes without saying that various wiring films can be used irrespective of the shape and structure of each of the above embodiments.
【０００９】[0009]
【発明の効果】以上説明したように本発明は、半導体チ
ップ上リード配線型パッケージの半導体装置において、
リード配線の一部を配線フィルムで構成し、前記半導体
チップと前記配線フィルム、及び前記配線フィルムと前
記リード配線とをそれぞれボンディングワイヤによって
電気的に接続しているので、配線幅を細く薄くして寄生
容量を低減することができるとともに、配線強度を高め
て信頼性を向上することができるという効果を有する。
また、半導体装置チップと配線フィルムの相対位置、及
び配線フィルムとリード配線の相対位置が一定しない場
合においても、ボンディングワイヤにおいて相互間を好
適に電気接続することが可能となる。 As described above, the present invention relates to a semiconductor device of a lead wiring type package on a semiconductor chip.
A part of the lead wiring is composed of a wiring film, and the semiconductor
Chip and the wiring film, and the wiring film and the front
The lead wire and the bonding wire
Since they are electrically connected , the wiring width can be made thinner and thinner to reduce the parasitic capacitance, and the wiring strength can be increased to improve the reliability.
In addition, the relative positions of the semiconductor device chip and the wiring film,
If the relative positions of the wiring film and the lead wiring are not
The bonding wires are
It is possible to make an appropriate electrical connection.
【図１】本発明の第１実施例の縦断面図及び横断面図で
ある。FIG. 1 is a longitudinal sectional view and a transverse sectional view of a first embodiment of the present invention.
【図２】本発明の第２実施例の縦断面図及び横断面図で
ある。FIG. 2 is a longitudinal sectional view and a transverse sectional view of a second embodiment of the present invention.
【図３】従来のチップ状リード配線型パッケージの半導
体装置の一例の縦断面図及び横断面図である。FIG. 3 is a longitudinal sectional view and a transverse sectional view of an example of a semiconductor device of a conventional chip-shaped lead wiring type package.
１ 半導体チップ １ａ ボンディングパッド ２ リード配線 ３ 接着フィルム ４ ボンディングワイヤ ５ モールド樹脂 ６ 配線フィルム DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Bonding pad 2 Lead wiring 3 Adhesive film 4 Bonding wire 5 Mold resin 6 Wiring film
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/50 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 23/50
Claims (1)
在されるパッケージ構造の半導体装置において、前記半
導体チップ上には絶縁フィルム表面に細い配線を一体に
形成した配線フィルムを配設し、前記半導体チップと前
記配線フィルム、及び前記配線フィルムと前記リード配
線とをそれぞれボンディングワイヤによって電気的に接
続したことを特徴とする半導体装置。1. A semiconductor device having a package structure in which a part of lead wiring extends on a semiconductor chip, a wiring film having thin wiring integrally formed on an insulating film surface is provided on the semiconductor chip. The semiconductor chip and the front
A wiring film, and the wiring film and the lead wiring;
A semiconductor device, wherein the wires are electrically connected to each other by bonding wires .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4309425A JP2963952B2 (en) | 1992-10-24 | 1992-10-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4309425A JP2963952B2 (en) | 1992-10-24 | 1992-10-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06140562A JPH06140562A (en) | 1994-05-20 |
| JP2963952B2 true JP2963952B2 (en) | 1999-10-18 |
Family
ID=17992856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4309425A Expired - Fee Related JP2963952B2 (en) | 1992-10-24 | 1992-10-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2963952B2 (en) |
-
1992
- 1992-10-24 JP JP4309425A patent/JP2963952B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06140562A (en) | 1994-05-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |