JPS63170A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63170A JPS63170A JP14361586A JP14361586A JPS63170A JP S63170 A JPS63170 A JP S63170A JP 14361586 A JP14361586 A JP 14361586A JP 14361586 A JP14361586 A JP 14361586A JP S63170 A JPS63170 A JP S63170A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- algaas
- gaas
- doped
- gallium arsenide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 15
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 46
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 8
- 229910000838 Al alloy Inorganic materials 0.000 claims description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 33
- 230000000694 effects Effects 0.000 abstract description 7
- 230000002411 adverse Effects 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000013139 quantization Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
- H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
- H01L29/155—Comprising only semiconductor materials
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
この発明は、２次元電子ガスをチャネルとするＧａＡｓ
／ＡｌＧａＡｓ系半導体装置にかかり、バッファ層とし
てノンドープのＡｌＧａＡｓ層とＧａＡｓ／ＡｌＧａＡ
ｓ超格子構造とを設け、ノンドープのＧａＡｓチャネル
層を該ＡｌＧａＡｓバッファ層より薄くして、ＡｌＧａ
Ａｓ電子供給層を設けることにより、その特性を向上し
、加えてＭＯ−ＣＶＤ法により半導体基体を形成して実
用化に対処することを可能とする。[Detailed Description of the Invention] [Summary] This invention relates to a GaAs film using a two-dimensional electron gas as a channel.
/AlGaAs-based semiconductor device, with a non-doped AlGaAs layer and a GaAs/AlGaA buffer layer.
s superlattice structure, and the non-doped GaAs channel layer is made thinner than the AlGaAs buffer layer.
By providing the As electron supply layer, its characteristics are improved, and in addition, it becomes possible to form a semiconductor substrate by the MO-CVD method for practical use.
本発明は半導体装置、特に空間分離ドーピングと界面量
子化による高移動度のキャリアをチャネルとする、例え
ば高電子移動度電界効果トランジスタ（ＨＥＭＴ）等の
ＧａＡｓ ／へ１ＧａＡｓ系半導体装置の改善に関する
。The present invention relates to improvements in semiconductor devices, particularly GaAs/GaAs-based semiconductor devices such as high electron mobility field effect transistors (HEMTs), which use high-mobility carriers as channels through spatial separation doping and interface quantization.
例えばＨＥｌ’ｌＴは、２次元状態の電子が移動する領
域と不純物をドーピングする領域とを空間的に分離して
キャリア移動度の増大を実現し、高速デバイスとして強
い期待が寄せられているが、その実用化のためになお一
層の改善が要望されている。For example, HEl'IT spatially separates the region where two-dimensional electrons move and the region where impurities are doped to increase carrier mobility, and there are strong expectations as a high-speed device. Further improvements are required for its practical use.
空間分離ドーピングとキャリアの界面量子化により高移
動度を実現している半導体装置の例として、ＨＥ？ＩＴ
の一例の模式側断面図を第２図（ａｌに示す。HE? is an example of a semiconductor device that achieves high mobility through spatial separation doping and interfacial quantization of carriers. IT
A schematic side sectional view of an example is shown in FIG. 2 (al).
その半導体基体は半絶縁性砒化ガリウム（ＧａＡｓ）基
板２１上に、バッファ層を兼ねるノンドープのＧａＡｓ
チャネル層２５、これより電子親和力が小さい砒化アル
ミニウムガリウム（ＡＩＧａＡｓ）電子供給層２６及び
ｎ型ＧａＡｓ層２７が積層され、このＡｌＧａＡｓ電子
供給層２６はＧａＡｓチャネル層２５とのへテロ接合界
面近傍に例えば厚さ５ｎｍ程度のノンドープのスペーサ
領域２６ａを設けて、その他を例えばシリコン（Ｓｉ）
を濃度２ ＸＩＯ”ｃｍ−’程度にドープしたｎ型領域
２６ｂとすることが多い。The semiconductor substrate is made of non-doped GaAs that also serves as a buffer layer on a semi-insulating gallium arsenide (GaAs) substrate 21.
A channel layer 25, an aluminum gallium arsenide (AIGaAs) electron supply layer 26 having a lower electron affinity than the channel layer 25, and an n-type GaAs layer 27 are laminated. A non-doped spacer region 26a with a thickness of about 5 nm is provided, and the rest is made of silicon (Si), for example.
The n-type region 26b is often doped to a concentration of about 2XIO"cm-'.
このＡｌＧａＡｓ電子供給層２６からＧａＡｓチャネル
１２５へ遷移した電子によってヘテロ接合界面近傍に２
次元電子ガス２５ｅが形成される。この２次元電子ガス
２５ｅの面密度をゲート電極２９によるショットキ空乏
層で制御してトランジスタ動作が行われるが、２次元電
子ガス２５ｅは不純物散乱による移動度低下が殆どなく
、格子散乱が減少する例えば７７に程度以下の低温にお
いて最も高い移動度が得られる。The electrons transferred from the AlGaAs electron supply layer 26 to the GaAs channel 125 cause 2
A dimensional electron gas 25e is formed. Transistor operation is performed by controlling the areal density of this two-dimensional electron gas 25e with a Schottky depletion layer formed by the gate electrode 29. However, the two-dimensional electron gas 25e has almost no mobility decrease due to impurity scattering, and lattice scattering is reduced, for example. The highest mobility is obtained at low temperatures below 77°C.
また第２図（ｂ）に示す従来例では、前記従来例と同等
の各半導体層とＧａＡｓ基板２１との間にバ・７フア層
としてノンドープのＡｌＧａＡｓ層２２を設けている。In the conventional example shown in FIG. 2(b), a non-doped AlGaAs layer 22 is provided as a buffer layer between each semiconductor layer and the GaAs substrate 21, which are the same as in the conventional example.
実用化に備えて次第に適用されている有機金属熱分解気
相成長（ＭＯ−ＣＶＤ）法による半導体基体では、この
ＡｌＧａＡｓバッファＪｉ！２２は成長初期に生じ易い
組成の偏りの回避、ＧａＡｓ基板２１に含まれる不純物
等の拡散の阻止などを従来上たる目的としている。In semiconductor substrates produced by metal organic pyrolysis vapor deposition (MO-CVD), which is gradually being applied in preparation for practical use, this AlGaAs buffer Ji! The conventional purpose of 22 is to avoid compositional imbalance that tends to occur in the initial stage of growth, and to prevent diffusion of impurities and the like contained in the GaAs substrate 21.
上述の第２図（ａｌの従来例では、ＧａＡｓチャネル層
２５はバッファ層を兼ねてその厚さが例えば０．５〜１
−程度と大きく、ゲート電圧がマイナスであるときに２
次元電子ガス２５ｅがへテロ接合界面近傍から深さ方向
に拡がり、ピンチオフ電圧のずれを生ずる傾向がある。In the conventional example shown in FIG.
− degree, and when the gate voltage is negative, 2
The dimensional electron gas 25e tends to spread in the depth direction from the vicinity of the heterojunction interface, causing a deviation in the pinch-off voltage.
第２図（ｂｌの従来例ではＧａＡｓチャネル層２５を薄
くし、ＡｌＧａＡｓバッファ層２２によって２次元電子
ガス２５ｅの深さ方向の拡がりを抑制することが試みら
れている。しかしながらＡｌＧａＡｓバッファ層２２の
結晶成長表面にはＴＥＭ（Ｔｒａｎｓｍｉｓｓｉｏｎ
Ｅｌｅｃｔｒｏ Ｍｉｃｒ。In the conventional example shown in FIG. 2 (bl), an attempt is made to thin the GaAs channel layer 25 and suppress the spread of the two-dimensional electron gas 25e in the depth direction by the AlGaAs buffer layer 22. However, the crystal of the AlGaAs buffer layer 22 A TEM (Transmission) is placed on the growth surface.
Electro Micro.
５ｃｏｐｙ）観察で明らかにされている様に凹凸の乱れ
を生じ、この面上に成長するＧａＡｓチャネル層２５を
薄くすれば２次元電子ガス２５ｅがこの界面の乱れの影
響を受けて、その移動度が低下するなどの問題を伴って
いる。5copy) As revealed by observation, irregularities occur in the unevenness, and if the GaAs channel layer 25 grown on this surface is thinned, the two-dimensional electron gas 25e will be affected by the disturbance at this interface, and its mobility will decrease. This is accompanied by problems such as a decline in
他方前記の半導体基体のＭＯ−ＣＶＤ法による成長では
、ｎ型ＡｌＧａＡｓ電子供給層２６のへテロ接合界面近
傍にキャリア濃度が低いデイプリージョン領域を生ずる
問題がある。On the other hand, the above-mentioned growth of the semiconductor substrate by the MO-CVD method has a problem in that a depletion region with a low carrier concentration is generated near the heterojunction interface of the n-type AlGaAs electron supply layer 26.
第３図はこの現象を調査するための試料の深さ方向のキ
ャリア濃度分布を示す図であり、本試料では半絶縁性Ｇ
ａＡｓ基板上に、厚さが何れも１１００ｎのノンドープ
のＡｌＧａＡｓ層２２ａ１ノンドープのｉ型ＧａＡｓ層
２５ａ及び電子供給層２６に相当し不純物濃度を５ Ｘ
ＩＯ”Ｃｍ−’と低くしたｎ型ＡｌＧａＡｓ層２６ａを
積層しているが、ｎ型ＡｌＧａＡｓ層２６ａのＧａＡｓ
層２５ａとのへテロ接合界面近傍に、ＧａＡｓ層２５ａ
にノンドープでも生ずる１０１５ ｃ 「３程度以下の
キャリア濃度より更に低い例えば５ ＸＩＯ”ｃｍ−’
程度の低濃度領域Ａを生じて、ＧａＡｓ層２５ａに２次
元電子ガスが形成されない。Figure 3 is a diagram showing the carrier concentration distribution in the depth direction of a sample to investigate this phenomenon.
On an aAs substrate, a non-doped AlGaAs layer 22a, each having a thickness of 1100 nm, corresponds to a non-doped i-type GaAs layer 25a and an electron supply layer 26, and has an impurity concentration of 5X.
Although the n-type AlGaAs layer 26a with a low IO"Cm-' is laminated, the GaAs of the n-type AlGaAs layer 26a
A GaAs layer 25a is located near the heterojunction interface with the layer 25a.
1015c occurs even when non-doped.
As a result, a relatively low concentration region A is generated, and no two-dimensional electron gas is formed in the GaAs layer 25a.
これらの試料に生ずる低キヤリア濃度領域ＡはＭＯ−Ｃ
ＶＤ法によるＡｌＧａＡｓ層成長の初期に発生し、反応
管内表面でアルミニウム（ＡＩ）と例えば酸素（０）等
の不純物との化合物ができ、これが結晶成長面に到達す
るためと考えられ、目的とするＡｌＧａＡｓ層の前に成
長するＧａＡｓ層が薄く、その成長時間が短い場合には
この問題が現れない。The low carrier concentration region A that occurs in these samples is MO-C.
It is thought that this occurs at the beginning of AlGaAs layer growth by the VD method, and a compound of aluminum (AI) and impurities such as oxygen (0) is formed on the inner surface of the reaction tube, and this reaches the crystal growth surface. This problem does not occur if the GaAs layer grown before the AlGaAs layer is thin and the growth time is short.
本発明は上述の各問題点を解決して、高速デバイスとし
て期待が大きいＯＥＭＴ等の実用化を推進することを目
的とする。The present invention aims to solve the above-mentioned problems and promote the practical use of OEMT, etc., which have high expectations as high-speed devices.
前記問題点は、半絶縁性砒化ガリウム基板上に、ノンド
ープの砒化アルミニウムガリウム・バッファ層と、
砒化ガリウム層と砒化アルミニウムガリウム層とからな
るノンドープのバッファ超格子構造と、該砒化アルミニ
ウムガリウム・バッファ層より薄いノンドープの砒化ガ
リウム・チャネル層と、ドナー不純物をドープした砒化
アルミニウムガリウム電子供給層とを備えて、
該砒化ガリウム・チャネル層に２次元電子ガスが形成さ
れる本発明による半導体装置により解決される。The problem is that a non-doped aluminum gallium arsenide buffer layer is formed on a semi-insulating gallium arsenide substrate, a non-doped buffer superlattice structure consisting of a gallium arsenide layer and an aluminum gallium arsenide layer, and the aluminum gallium arsenide buffer layer is formed on a semi-insulating gallium arsenide substrate. Solved by a semiconductor device according to the invention, comprising a thinner undoped gallium arsenide channel layer and an aluminum gallium arsenide electron supply layer doped with donor impurities, in which a two-dimensional electron gas is formed in the gallium arsenide channel layer. Ru.
なおＭＯ−ＣＶＤ法による半導体基体では、前記砒化ア
ルミニウムガリウム・バッファ層のアルミニウム混晶比
をｘ、前記バッファ超格子構造のアルミニウム混晶比の
平均値をｙ１前記砒化アルミニウムガリウム電子供給層
のアルミニウム混晶比を２として、
ｙ≧ｘ＞ｚ
とすることが望ましい。In the semiconductor substrate formed by the MO-CVD method, x is the aluminum alloy ratio of the aluminum gallium arsenide buffer layer, and y is the average value of the aluminum alloy ratio of the buffer superlattice structure. It is desirable to set the crystal ratio to 2 and to satisfy y≧x>z.
本発明によれば、ＡｌＧａＡｓバッファ層上にＧａＡｓ
／ＡｌＧａＡｓ超格子構造を設けることによりバッフ
ァ層／チャネル層界面の乱れを抑制して、ＧａＡｓチャ
ネル層が薄い場合にも２次元電子ガスに移動度低下等の
悪影響が及ぶことを防止する。According to the present invention, GaAs is deposited on the AlGaAs buffer layer.
By providing the /AlGaAs superlattice structure, disturbances at the buffer layer/channel layer interface are suppressed, and even when the GaAs channel layer is thin, adverse effects such as a decrease in mobility on the two-dimensional electron gas are prevented.
この様に障害を排除することにより、ＧａＡｓチャネル
層を薄くして、２次元電子ガスの拡がりによるピンチオ
フ電圧のずれ等の特性を改善すること、更にＭＯ−ＣＶ
Ｄ法による半導体基体ではｎ型Ａ ｌＧａＡｓ電子供給
層のへテロ接合界面近傍のデイプリージョン領域を防止
すること等の効果が得られる。By eliminating obstacles in this way, it is possible to make the GaAs channel layer thinner, improve characteristics such as deviation in pinch-off voltage due to two-dimensional electron gas spread, and further improve MO-CV
In the semiconductor substrate manufactured by the D method, effects such as prevention of a depletion region near the heterojunction interface of the n-type AlGaAs electron supply layer can be obtained.
以下本発明を実施例により具体的に説明する。 The present invention will be specifically explained below using examples.
第１図はＨＥＭＴにかかる本発明の実施例を示す模式側
断面図である。FIG. 1 is a schematic side sectional view showing an embodiment of the present invention related to a HEMT.
本実施例の半導体基体は半絶縁性ＧａＡｓ基板１上に、
ＡｌＧａＡｓバッファ層２及び４、バッファ超格子構造
３、ＧａＡｓチャネル層５、層６ａ、 ６ｂから−なる
ＡｌＧａＡｓ電子供給層６ 、ＧａＡｓキャップＮ７が
例えば下記の如＜ ＭＯ−ＣＶＤ法により形成されてい
る。The semiconductor substrate of this example is on a semi-insulating GaAs substrate 1,
AlGaAs buffer layers 2 and 4, a buffer superlattice structure 3, a GaAs channel layer 5, an AlGaAs electron supply layer 6 consisting of layers 6a and 6b, and a GaAs cap N7 are formed, for example, by the MO-CVD method as described below.
符号 組成 不純物 厚さｃｍ−”
ｎｍ
７ ＧａＡｓ ２ ｘｌＱｌａ
３０６ｂ Ａｌ５Ｇａｔ−Ｊｓ； ｚ□０
．３ ２ ｘｌＱｌａ ３０５ａ Ａ１．
Ｇａｌ−、Ａｓ； ｚ＝０．３ ノンドープ 嬌５
５ ＧａＡｓ ノンドープ 下記
４ Ａｌ５Ｇａｔ−ｗＡｓ； ｗ＝０．５ ノ
ンドープ ＃５０３ 超格子構造 ３ａ×５層＋３ｂ
×５層３ｂ ＧａＡｓ ノンドープ
１３ａ Ａｌ５Ｇａｔ−ｙＡｓＨｙ＝ｘ、ｏ
ノンドープ １２Ａ１ｘＧａｌ−ｘＡｓ； ｘ
＝０．５ ノンドープ ≧５０本実施例のバッファ
は基板１側がらＡｌＧａＡｓ層２、超格子構造３、Ａｌ
ＧａＡｓ層４で構成しているが、ＡｌＧａＡｓ層２及び
４はＡｌ混晶比を０．５として、へｌＧａＡｓ電子供給
層６ａ、６ｂの０．３より大きくしている。Code Composition Impurity Thickness cm-”
nm 7 GaAs 2 xlQla
306b Al5Gat-Js; z□0
．． 3 2 xlQla 305a A1.
Gal-, As; z=0.3 Non-doped 5
5 GaAs Non-doped Below 4 Al5Gat-wAs; w=0.5 Non-doped #503 Superlattice structure 3a x 5 layers + 3b
×5 layer 3b GaAs non-doped 13a Al5Gat-yAsHy=x, o
Non-doped 12A1xGal-xAs; x
=0.5 Non-doped ≧50 The buffer of this example has an AlGaAs layer 2, a superlattice structure 3, and an Al layer from the substrate 1 side.
The AlGaAs layers 2 and 4 have an Al mixed crystal ratio of 0.5, which is larger than 0.3 of the GaAs electron supply layers 6a and 6b.
超格子構造３は上記の如＜Ｙ＝１．０のＡｌ５Ｇａｔ−
ｙＡｓすなわちＡｌＡｓとＧａＡｓとで構成し、その厚
さ及び層数を重みづけした混晶比の平均値ｙを０．５以
上としている。The superlattice structure 3 is made of Al5Gat- with <Y=1.0 as described above.
It is composed of yAs, that is, AlAs and GaAs, and the average value y of the mixed crystal ratio weighted by the thickness and number of layers is set to 0.5 or more.
ＧａＡｓチャネルＮ５はこの本発明によるバッファ上に
、厚さ例えば５〜５０ｎｍ程度の範囲で任意に成長する
ことができ、ＡｌＧａＡｓ電子供給層６とのへテロ接合
界面近傍に２次元電子ガス５ｅが形成され、ＡｌＧａＡ
ｓバッファ層５とのへテロ接合界面も十分に滑らかであ
って、電子移動度の低下等の障害が解決されている。The GaAs channel N5 can be grown arbitrarily on the buffer according to the present invention to a thickness of, for example, about 5 to 50 nm, and a two-dimensional electron gas 5e is formed near the heterojunction interface with the AlGaAs electron supply layer 6. and AlGaA
The heterojunction interface with the s-buffer layer 5 is also sufficiently smooth, and problems such as a decrease in electron mobility are solved.
この半導体基体上に従来技術により、ソース、ドレイン
電極８を例えば金ゲルマニウム／金（ＡｕＧｅ／Ａｕ）
を用いて、ゲート電極９を例えばアルミニウム（ＡＩ）
を用いて配設する。On this semiconductor substrate, source and drain electrodes 8 are formed using, for example, gold germanium/gold (AuGe/Au) using a conventional technique.
The gate electrode 9 is made of aluminum (AI), for example.
Arrange using.
本実施例ではＧａＡｓチャネル層を薄くシて井戸構造と
した効果が、バッファ層界面の乱れによる悪影響なく得
られ本発明の効果を実証している。In this example, the effect of forming a well structure by thinning the GaAs channel layer was obtained without any adverse effects caused by disturbances at the interface of the buffer layer, thus demonstrating the effect of the present invention.
なお本発明はＩＩＥＭＴにその適用を限られるものでは
なく、空間分離ドーピングと界面量子化による高移動度
のキャリアを利用する他のＧａＡｓ／ＡｌＧａＡｓ系半
導体装置にも適用することが可能である。The application of the present invention is not limited to IIEMT, but can also be applied to other GaAs/AlGaAs-based semiconductor devices that utilize high-mobility carriers due to spatial separation doping and interface quantization.
以上説明した如く本発明によれば、空間分離ドーピング
と界面量子化による２次元電子ガスをチャネルとするＧ
ａＡｓ／ＡｌＧａＡｓ系半導体装置において、ＧａＡｓ
チャネル層を薄くし井戸構造としてその特性を向上し、
加えてＮｏ−ＣＶＤ法により半導体基体を形成して実用
化に良く対処することが可能となる。As explained above, according to the present invention, a G
In aAs/AlGaAs semiconductor devices, GaAs
By thinning the channel layer and creating a well structure, its characteristics are improved.
In addition, it becomes possible to form a semiconductor substrate by the No-CVD method, which is suitable for practical use.
第１図はＨＥＭＴにかかる実施例の模式側断面図、第２
図（ａ）、（ｂ）はＨＥＭＴの従来例の模式側断面図、
第３図はＭＯ−ＣＶＤ法による試料のキャリア濃度分布
の例を示す図である。
図において、
１は半絶縁性ＧａＡｓ基板、
２及び４はノンドープのＡｌＧａＡｓバッファ層、３は
ＧａＡｓ ／＾ｌＧａＡｓ超格子構造、５はノンドープ
のＧａＡｓチャネル層、５ｅは２次元電子ガス、
６ａはノンドープのＡｌＧａＡｓスペーサ層、６ｂはｎ
型ＡｌＧａＡｓ電子供給層、
７はｎ型ＧａＡｓキャップ層翫
８はソース、ドレイン電極、
９はゲート電極を示す。
Ｘ党り］の榎武゛震１１餠［有］図
竿 １ 呟
（α）
（し）
ＨＥ、”ＩＴのイ道ｆ：、グ″ｊの、涙式：侵″１町韻
【子 ２ 図Figure 1 is a schematic side sectional view of an embodiment related to HEMT, Figure 2
Figures (a) and (b) are schematic side sectional views of conventional examples of HEMT,
FIG. 3 is a diagram showing an example of the carrier concentration distribution of a sample obtained by the MO-CVD method. In the figure, 1 is a semi-insulating GaAs substrate, 2 and 4 are non-doped AlGaAs buffer layers, 3 is a GaAs/^lGaAs superlattice structure, 5 is a non-doped GaAs channel layer, 5e is a two-dimensional electron gas, and 6a is a non-doped AlGaAs buffer layer. AlGaAs spacer layer, 6b is n
7 is an n-type GaAs cap layer; 8 is a source and drain electrode; and 9 is a gate electrode. [X party] Enobu゛Shin 11 [Yes] Zukan 1 murmur (α) (shi) HE, ``IT's path f:, gu''j's tearful ceremony: invasion'' 1 town rhyme [child 2 figure
Claims (1)
アルミニウムガリウム・バッファ層と、砒化ガリウム層
と砒化アルミニウムガリウム層とからなるノンドープの
バッファ超格子構造と、該砒化アルミニウムガリウム・
バッファ層より薄いノンドープの砒化ガリウム・チャネ
ル層と、ドナー不純物をドープした砒化アルミニウムガ
リウム電子供給層とを備えて、 該砒化ガリウム・チャネル層に２次元電子ガスが形成さ
れることを特徴とする半導体装置。 ２）前記砒化アルミニウムガリウム・バッファ層のアル
ミニウム混晶比をｘ、前記バッファ超格子構造のアルミ
ニウム混晶比の平均値をｙ、前記砒化アルミニウムガリ
ウム電子供給層のアルミニウム混晶比をｚとして、 ｙ≧ｘ＞ｚ なることを特徴とする特許請求の範囲第１項記載の半導
体装置。[Scope of Claims] 1) A non-doped aluminum gallium arsenide buffer layer on a semi-insulating gallium arsenide substrate, a non-doped buffer superlattice structure consisting of a gallium arsenide layer and an aluminum gallium arsenide layer, and the aluminum gallium arsenide.・
A semiconductor comprising a non-doped gallium arsenide channel layer thinner than a buffer layer and an aluminum gallium arsenide electron supply layer doped with a donor impurity, in which a two-dimensional electron gas is formed in the gallium arsenide channel layer. Device. 2) The aluminum alloy ratio of the aluminum gallium arsenide buffer layer is x, the average value of the aluminum alloy ratio of the buffer superlattice structure is y, and the aluminum alloy ratio of the aluminum gallium arsenide electron supply layer is z, and y The semiconductor device according to claim 1, characterized in that ≧x>z.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14361586A JPS63170A (en) | 1986-06-19 | 1986-06-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14361586A JPS63170A (en) | 1986-06-19 | 1986-06-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63170A true JPS63170A (en) | 1988-01-05 |
Family
ID=15342859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14361586A Pending JPS63170A (en) | 1986-06-19 | 1986-06-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63170A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6464367A (en) * | 1987-09-04 | 1989-03-10 | Nec Corp | Semiconductor device |
| JPH036030A (en) * | 1989-06-02 | 1991-01-11 | Sharp Corp | Field-effect type semiconductor device |
| US5146295A (en) * | 1988-03-29 | 1992-09-08 | Omron Tateisi Electronic Co. | Semiconductor light emitting device having a superlattice buffer layer |
| US5254863A (en) * | 1990-10-19 | 1993-10-19 | U.S. Philips Corp. | Semiconductor device such as a high electron mobility transistor |
| US5283445A (en) * | 1991-11-29 | 1994-02-01 | Fujitsu Limited | Quantum semiconductor device employing quantum boxes for enabling compact size and high-speed operation |
| JPH06188272A (en) * | 1992-12-21 | 1994-07-08 | Nec Corp | Hetero junction field effect transistor |
-
1986
- 1986-06-19 JP JP14361586A patent/JPS63170A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6464367A (en) * | 1987-09-04 | 1989-03-10 | Nec Corp | Semiconductor device |
| US5146295A (en) * | 1988-03-29 | 1992-09-08 | Omron Tateisi Electronic Co. | Semiconductor light emitting device having a superlattice buffer layer |
| JPH036030A (en) * | 1989-06-02 | 1991-01-11 | Sharp Corp | Field-effect type semiconductor device |
| US5254863A (en) * | 1990-10-19 | 1993-10-19 | U.S. Philips Corp. | Semiconductor device such as a high electron mobility transistor |
| US5283445A (en) * | 1991-11-29 | 1994-02-01 | Fujitsu Limited | Quantum semiconductor device employing quantum boxes for enabling compact size and high-speed operation |
| JPH06188272A (en) * | 1992-12-21 | 1994-07-08 | Nec Corp | Hetero junction field effect transistor |
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