JPS63160227A - Dry etching - Google Patents
Dry etchingInfo
- Publication number
- JPS63160227A JPS63160227A JP31485586A JP31485586A JPS63160227A JP S63160227 A JPS63160227 A JP S63160227A JP 31485586 A JP31485586 A JP 31485586A JP 31485586 A JP31485586 A JP 31485586A JP S63160227 A JPS63160227 A JP S63160227A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- wafer
- resist
- mask
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001312 dry etching Methods 0.000 title claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims 1
- 238000001816 cooling Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 239000005011 phenolic resin Substances 0.000 abstract description 2
- 239000002826 coolant Substances 0.000 abstract 1
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 8
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000498 cooling water Substances 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003189 isokinetic effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
不発ＢＡは、ドライエツチング方法に関し、特に多層レ
ジスト法における下層有機膜の異方性エツチングに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] Non-explosion BA relates to dry etching methods, particularly to anisotropic etching of underlying organic films in multilayer resist methods.
従来、半導体基板上の段差上に微細なパターンを形成す
る方法として、上層にフォトレジストや、絶縁膜、金属
膜ｌ１ｌＩを形成し、パターニング後、該上層膜をマス
クに下層有機ＰＡｔエツチングするという、多層レジス
ト法がある。この時の下層有機膜の異方性エツチングは
、第３図に示す様な、平行平板型リアクティブイオンエ
ツチング装置で行っている。この時、半導体基板の冷却
は、水冷のみによる冷却であり、半導体基板と下部電極
の間にすき間が生じるため、熱伝導率が悪く、半導体基
板上の温度を２０Ｃ以下に保つのは、むずかしい。半導
体基板上の温度が２０Ｃを越えるとＯ。Conventionally, as a method for forming a fine pattern on a step on a semiconductor substrate, a photoresist, an insulating film, or a metal film is formed as an upper layer, and after patterning, the lower organic PAt layer is etched using the upper layer film as a mask. There is a multilayer resist method. The anisotropic etching of the lower organic film at this time is performed using a parallel plate type reactive ion etching apparatus as shown in FIG. At this time, the semiconductor substrate is cooled only by water cooling, and since a gap is created between the semiconductor substrate and the lower electrode, the thermal conductivity is poor and it is difficult to maintain the temperature on the semiconductor substrate below 20C. O when the temperature on the semiconductor substrate exceeds 20C.
ガスを用いたりアクティブイオンエツチングにおいて、
解離した０ （ラジカル）が工、チングに寄与する友め
、等力性エツチングとなシ、第４図に示す様なエツチン
グ形状となる。In gas or active ion etching,
The dissociated 0 (radicals) contribute to etching, resulting in isokinetic etching, resulting in an etching shape as shown in FIG.
上述した従来のドライエツチング方法においては半導体
基板表面の温度が２０Ｃ以上となるため０、ガスによる
下層有機膜のエツチングにおいて、マスクからのサイド
エツチングが入るという欠点がある。In the conventional dry etching method described above, since the temperature of the surface of the semiconductor substrate is 20C or more, there is a drawback that side etching from the mask occurs when etching the lower organic film using gas.
本発明のドライエッチング力法は、静電吸着、あるいは
ガス冷却など、効果的な半導体基板の冷却を行い、表面
温度を２０Ｃ以下に保つことを有している。The dry etching force method of the present invention includes effective cooling of the semiconductor substrate by electrostatic adsorption or gas cooling to maintain the surface temperature at 20C or lower.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図に不発明を適用するためのエツチング装置例を示
す。（（ａｌ ）は下部電極にＤＣバイアスを印加し、
静電吸着を用いてワエハーを電極密着させる方法。（（
ｂｌ ）は、熱伝導率の良いガスを、９エバーの下に流
し、冷却する例である。FIG. 1 shows an example of an etching apparatus to which the invention is applied. ((al) applies a DC bias to the lower electrode,
A method of bringing a wafer into close contact with an electrode using electrostatic adsorption. ((
bl) is an example in which a gas with good thermal conductivity is cooled by flowing it under 9-ever.
第２図は本発明を適用した実施例の縦断面図である。第
１の実施例としてまず下層レジストとしてフェノール慟
脂系ポジレジストを２μｍ厚で塗布し、２５０ＣＮ１
１’ｈｒのベークをし次アと、約１００ＯＡの８０Ｇを
スピン塗布し、２００ ＣｅＮ、、３０分のベークを行
う。その後、上ＩＩヲボジレジストを用いて、バターニ
ングし、そのレジストをマスクにＳ ＯＧ ｋ ＣＦ
４ガスを用いて、ドライエツチングする。その後、上層
レジストと中間層８０Ｇをマスクに、第１図で示した平
行平板型リアクティブイオンエツチング装置ｔ−用い、
つ′エバー表面の温度を２０ｒ以下に保ちなから０゜ガ
スを用いて、下層レジストの異方性エツチングを行った
。FIG. 2 is a longitudinal sectional view of an embodiment to which the present invention is applied. In the first example, a phenol resin-based positive resist was applied as a lower layer resist to a thickness of 2 μm, and 250CN1
Bake for 1'hr, then spin coat 80G at about 100OA, apply 200CeN, and bake for 30 minutes. After that, buttering was performed using the upper II body resist, and SOG k CF was applied using the resist as a mask.
Dry etching using 4 gas. After that, using the upper resist layer and the intermediate layer 80G as a mask, using the parallel plate type reactive ion etching apparatus shown in FIG.
The lower resist layer was anisotropically etched using 0° gas while keeping the temperature of the Ever surface below 20°.
また、第２因で下層有機膜にポリイミド樹脂膜を２ｔｔ
ｍはど塗布し、３０ＵＣ，Ｎ、、ｌｈｒべ一りを行った
後、上記第１の実施例と同様の工程を経て、下層ポリイ
ミド県側脂膜の異方性エツチングを行うことも可能であ
った。In addition, for the second reason, 2tt of polyimide resin film was added to the lower organic film.
It is also possible to perform anisotropic etching of the lower polyimide side fat film through the same process as in the first embodiment described above, after applying 30 UC, N, and lhr of baking. there were.
以上、説明したように本発明は、下層有機膜のエツチン
グ中の半導体基板表面の温度を２０Ｃ以下に保つことで
、下層有機膜のエツチングにおけるサイドエツチング量
を抑制することができる効果がある。As described above, the present invention has the effect of suppressing the amount of side etching during etching of the lower organic film by keeping the temperature of the surface of the semiconductor substrate below 20C during etching of the lower organic film.
第１図は、本発明を適用するためのエツチング装置の例
、第２図は本発明を適用し友２階レジストにおける下層
レジストドライエツチング後の形状を示す。第３図は、
従来のエツチング装置の例であり、第４因は従来のエツ
チング装置によるエツチング形状を示す。
ｌ・・・・・・Ｓｒクエノ・−１２・・・・・・ポリイ
ミドテープ、３・・・・・・ステンレス電極、４・・・
・・・冷却された水（入水）、５・・・・・・冷却水（
排水）、６・・・・・・ＤＣバイアス、７・・・・・・
ＲＦｔｌ源、８・・・・・・上部電極、９・・・・・・
８ ｒ ７エハー、１０・・・・・・クラン７’、１１
・・・・・・ステンレス電極、１２・・・・・・Ｉ’ｔ
Ｆ’Ｉｌ！源、１３．１４・・・・・・ガス冷却、１５
・・・・・・上部′ｌ！極、１６・・・・・・レジスト
またはポリイミド樹脂、１７・・・・・・８０Ｇ（マス
ク材）、１８・・・・・・Ｓｉｎ、、１９・・・・・・
シリコン基板、２０・・・・・・８１’７エハー、２１
・・・・・・スレンレス下部電極、２２・・・・・・冷
却水（注水）、２３・・・・・・冷却水（排水）、２４
・・・・・・ＲＦｉ１１源、２５・・・・・・上部電極
、２６・・・・・・８０Ｇ。
２７・・・・・・レジスト、２８・・・・・・５ｉ０２
，２９・・・・・・シリコン基板代理人 弁理士 内
原 晋、、ハ・・・７・、（（Ｌ）
茅 １ 図
第 ３Ｉ！Ｉ
茅 ４ 図FIG. 1 shows an example of an etching apparatus to which the present invention is applied, and FIG. 2 shows the shape of a lower layer resist after dry etching of a second-layer resist to which the present invention is applied. Figure 3 shows
This is an example of a conventional etching device, and the fourth factor shows the shape etched by the conventional etching device. l...Sr Kueno-12...Polyimide tape, 3...Stainless steel electrode, 4...
...Cooled water (water inflow), 5...Cooled water (
drainage), 6...DC bias, 7...
RFtl source, 8... Upper electrode, 9...
8 r 7 Eher, 10... Clan 7', 11
......Stainless steel electrode, 12...I't
F'Il! Source, 13.14...Gas cooling, 15
...Top 'l! Pole, 16...Resist or polyimide resin, 17...80G (mask material), 18...Sin, 19...
Silicon substrate, 20...81'7 wafer, 21
...Stainless lower electrode, 22 ... Cooling water (water injection), 23 ... Cooling water (drainage), 24
...RFi11 source, 25...Top electrode, 26...80G. 27...Regist, 28...5i02
,29...Silicon substrate agent Susumu Uchihara, patent attorney,,Ha...7, ((L) Kaya 1 Figure 3I!I Kaya 4 Figure
Claims (1)
マスクとして、その下部に形成された有機膜層を、Ｏ＿
２ガスを用いて、平行平板電極型リアクティブオンエッ
チング装置で異方性エッチングを行う工程において、エ
ッチング中の表面の温度を２０℃以下に保つことを特徴
とするドライエッチング方法。Using a layer made of photoresist, insulating film, or metal film as a mask, the organic film layer formed under it is exposed to O_
A dry etching method characterized in that the temperature of the surface during etching is maintained at 20° C. or less in the step of performing anisotropic etching using two gases in a parallel plate electrode type reactive on etching apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61314855A JPH0713960B2 (en) | 1986-12-23 | 1986-12-23 | Dry etching equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61314855A JPH0713960B2 (en) | 1986-12-23 | 1986-12-23 | Dry etching equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63160227A true JPS63160227A (en) | 1988-07-04 |
| JPH0713960B2 JPH0713960B2 (en) | 1995-02-15 |
Family
ID=18058423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61314855A Expired - Lifetime JPH0713960B2 (en) | 1986-12-23 | 1986-12-23 | Dry etching equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0713960B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453157A (en) * | 1994-05-16 | 1995-09-26 | Texas Instruments Incorporated | Low temperature anisotropic ashing of resist for semiconductor fabrication |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4261762A (en) * | 1979-09-14 | 1981-04-14 | Eaton Corporation | Method for conducting heat to or from an article being treated under vacuum |
| JPS60158627A (en) * | 1984-01-27 | 1985-08-20 | Hitachi Ltd | Controlling method of surface reaction |
| JPS60175424A (en) * | 1984-02-22 | 1985-09-09 | Hitachi Ltd | Plasma treating apparatus |
| JPS60189950A (en) * | 1984-03-09 | 1985-09-27 | Tokuda Seisakusho Ltd | Method of removing charge of electrostatic chuck |
| JPS61103530A (en) * | 1984-10-25 | 1986-05-22 | Ulvac Corp | Cooling mechanism of substrate in vacuum treatment device |
| JPS61103531A (en) * | 1984-10-25 | 1986-05-22 | Ulvac Corp | Cooling mechanism of substrate in vacuum treating apparatus |
-
1986
- 1986-12-23 JP JP61314855A patent/JPH0713960B2/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4261762A (en) * | 1979-09-14 | 1981-04-14 | Eaton Corporation | Method for conducting heat to or from an article being treated under vacuum |
| JPS60158627A (en) * | 1984-01-27 | 1985-08-20 | Hitachi Ltd | Controlling method of surface reaction |
| JPS60175424A (en) * | 1984-02-22 | 1985-09-09 | Hitachi Ltd | Plasma treating apparatus |
| JPS60189950A (en) * | 1984-03-09 | 1985-09-27 | Tokuda Seisakusho Ltd | Method of removing charge of electrostatic chuck |
| JPS61103530A (en) * | 1984-10-25 | 1986-05-22 | Ulvac Corp | Cooling mechanism of substrate in vacuum treatment device |
| JPS61103531A (en) * | 1984-10-25 | 1986-05-22 | Ulvac Corp | Cooling mechanism of substrate in vacuum treating apparatus |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453157A (en) * | 1994-05-16 | 1995-09-26 | Texas Instruments Incorporated | Low temperature anisotropic ashing of resist for semiconductor fabrication |
| EP0683512A2 (en) * | 1994-05-16 | 1995-11-22 | Texas Instruments Incorporated | Anisotropic plasma etching of semiconductor device |
| EP0683512A3 (en) * | 1994-05-16 | 1997-11-19 | Texas Instruments Incorporated | Anisotropic plasma etching of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0713960B2 (en) | 1995-02-15 |
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