JPH01140629A - Pattern forming method - Google Patents
Pattern forming methodInfo
- Publication number
- JPH01140629A JPH01140629A JP30065087A JP30065087A JPH01140629A JP H01140629 A JPH01140629 A JP H01140629A JP 30065087 A JP30065087 A JP 30065087A JP 30065087 A JP30065087 A JP 30065087A JP H01140629 A JPH01140629 A JP H01140629A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- pattern
- forming
- submicron
- resist pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000009713 electroplating Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 239000011521 glass Substances 0.000 abstract description 2
- 238000007747 plating Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明はパターン形成において、サブミクロンパターン
の形成及びサブミクロンパターンとサブミクロン以上の
パターンが共存するパターン形成方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> In pattern formation, the present invention relates to the formation of submicron patterns and a pattern formation method in which submicron patterns and patterns larger than submicron coexist.
〈従来の技術〉
近年、半導体素子の集積回路の高密度化及び高周波化等
に伴ない、サブミクロンパターンの加工技術が必要とさ
れている。<Prior Art> In recent years, with the increase in density and frequency of integrated circuits of semiconductor devices, submicron pattern processing technology is required.
この加工技術として、ＥＢ露元法及びＸ線露光法等が新
規技術として前者は実用されつつあり、後者も開発中で
ある。As new processing techniques such as EB exposure method and X-ray exposure method, the former is being put into practical use as a new technique, and the latter is also under development.
しかし、両者共、装置のコストが高く、スルーブツトも
低く、かつ安価で良好なレジストがない等の問題があり
、未だ量産には適していない。そこで従来装置及び従来
技術を駆使して量産に適したサブミクロンパターン加工
技術が多種提案されている。However, both methods have problems such as high equipment cost, low throughput, and lack of inexpensive and good resists, and are not yet suitable for mass production. Therefore, various submicron pattern processing techniques suitable for mass production have been proposed by making full use of conventional equipment and techniques.
この方法の１つにパターン反転法がある。One of these methods is a pattern inversion method.
この方法は、フォトレジストを用いて過剰露光又は過剰
現像を施せば、０．５μｍ以下のラインパターンが形成
出来ることに着目して、このサブミクロンラインパター
ンをサブミクロンスペースパターンに反転してパターン
を形成する方法で特に高周波デバイスの電界効果トラン
ジスタのゲートパターンの形成等に有効な方法である。This method focuses on the fact that a line pattern of 0.5 μm or less can be formed by overexposure or overdevelopment using a photoresist, and inverts this submicron line pattern into a submicron space pattern to create a pattern. This method is particularly effective for forming gate patterns of field effect transistors of high frequency devices.
次に、この従来の方法について第２図（ａ）〜（ｄ）を
参照して説明する。Next, this conventional method will be explained with reference to FIGS. 2(a) to 2(d).
まず、第２図（ａ）に示すように基板２１上に適当な有
機物質で第１の層２２が形成され、その上にレジストパ
ターン２４が形成される。次に第２図（ｂ）に示すよう
に５ＯＧ（Ｓｐｉｎ ｏｎ ｇｌａｓｓ）等が塗布
及びベークされてレジストパターンを平坦化する平坦化
層２５が形成される。このとき有機膜２２上のＳＯＧの
膜厚ｄ、とレジストパターン２４上の膜厚ｄ２とはパタ
ーン平坦化率の関係でｄ＋＞ｄ２となる。次にＳＯＧ膜
２膜上５Ｆ４ガスを用いた反応性イオンエツチング（Ｒ
ＩＥ）により、上記のレジストパターン２４が露出する
迄、エツチングが施され（エッチバックされ）レジスト
パターン２４の頭出しが行なわれる。このときレジスト
パターン２４のない有機膜上にはｆｉ２図（Ｃ）に示す
ように、ｄ、−ｄ２の膜厚のＳＯＧ膜２膜上５在する。First, as shown in FIG. 2(a), a first layer 22 of a suitable organic material is formed on a substrate 21, and a resist pattern 24 is formed thereon. Next, as shown in FIG. 2(b), 5OG (Spin on Glass) or the like is applied and baked to form a flattening layer 25 for flattening the resist pattern. At this time, the film thickness d of the SOG on the organic film 22 and the film thickness d2 on the resist pattern 24 have a relationship of d+>d2 due to the pattern flattening rate. Next, reactive ion etching (R) using 5F4 gas was performed on the two SOG films.
By IE), etching is performed (etched back) until the resist pattern 24 is exposed, and the beginning of the resist pattern 24 is located. At this time, on the organic film without the resist pattern 24, there are 5 SOG films 2 with a film thickness of d and -d2, as shown in FIG. fi2 (C).
最後にこのＳＯＧ膜２膜上５スクとして第２図（ｄ）に
示すように、０２ガスを用いて、レジストパターン２４
と有機物膜２２にＲＩＥが施されて、上記のレジストパ
ターン２４を反転したパターンが得られる。Finally, as shown in FIG. 2(d), a resist pattern 24 is formed on the two SOG films using 02 gas.
Then, RIE is applied to the organic film 22 to obtain a pattern that is an inversion of the resist pattern 24 described above.
〈発明が解決しようとする問題点〉
上記した従来のパターン反転法を用いて、サブミクロン
ポジパターンを形成することが出来るが、このような方
法を用いた場合、ＳＯＧ膜を均一にかつ再現性良く制御
することは困難であり、またＳＯＧ膜の平坦化率の関係
で、レジストパターン幅が大きくなればなる程（ｄ＋−
ｄ２）の値が零に近づく為、サブミクロン幅のパターン
とサブミクロン以上の幅のパターンが共存するようなパ
ターンを形成するには、マージンが小さくなり、第３図
（ａ） 、 （ｂ）に示すような不良が発生したりして
、量産等が困難になるという問題点があった。<Problems to be Solved by the Invention> Submicron positive patterns can be formed using the conventional pattern inversion method described above, but when such a method is used, it is difficult to form an SOG film uniformly and reproducibly. It is difficult to control well, and due to the flattening rate of the SOG film, the larger the resist pattern width (d+-
Since the value of d2) approaches zero, the margin becomes small in order to form a pattern in which a pattern with a submicron width and a pattern with a width of submicron or more coexist, as shown in Figures 3 (a) and (b). There is a problem in that defects such as those shown in the figure below occur, making mass production difficult.
本発明は、上記の点に鑑みて創案されたものであり、上
記従来の問題点を除去した新規なパターン形成方法を提
供することを目的としている。The present invention was devised in view of the above points, and an object of the present invention is to provide a novel pattern forming method that eliminates the above conventional problems.
〈問題点を解決するための手段〉
上記の目的を達成するため、本発明のパターン形成方法
は、基板上に第１の層を形成する工程と、この第１の層
上に導電性材料により第２の層を形成する工程と、この
第２の層上に所望のホトレジストを塗布し、露光、現像
を施して第３の層としてのレジストパターンを形成する
工程と、上記の第２の層に通電して、上記のレジストパ
ターンをマスク材として、上記の第２の層上に第４の層
としての所望の金属を電解メッキ等により形成する工程
と、この第４の層をマスク材として上記の第３、第２及
び第１の層にエツチングを施して、上記の第３の層のレ
ジストパターンを反転したパターンを形成する工程とを
含んでなるように構成している。<Means for Solving the Problems> In order to achieve the above object, the pattern forming method of the present invention includes a step of forming a first layer on a substrate, and a step of forming a conductive material on the first layer. a step of forming a second layer; a step of applying a desired photoresist on the second layer, exposing and developing it to form a resist pattern as a third layer; and a step of forming a resist pattern as a third layer; a step of forming a desired metal as a fourth layer on the second layer by electrolytic plating or the like using the resist pattern as a mask material, and using the fourth layer as a mask material. The method includes the step of etching the third, second, and first layers to form a pattern that is an inversion of the resist pattern of the third layer.
即ち、より具体的には本発明は、上記した従来のパター
ン反転法に於ける問題点を解決する為に、適当な有機膜
等で第１の層を形成した後、この第１の層の上に導電性
を示す金属等で第２の層を形成した後、この第２の層の
上に適当なホトレジストを塗布し、露光、現像を施して
、レジストパターンを形成して第３の層とし、その後、
上記した第２の層を通電し、上記のレジストパターンを
マスク材とし、第２の層上−のレジストパターンのない
部分にだけ、第２の層のエツチングに対して選択比の高
い金属等を、電界メッキ等で形成して第４の層とし、そ
の後第４の層をマスク材として、第３．第２及び第１の
層をＲＩＥ等で順次エツチングしてサブミクロンパター
ンを形成するものである。That is, more specifically, in order to solve the problems in the conventional pattern inversion method described above, the present invention forms a first layer of an appropriate organic film, etc., and then processes the first layer. After forming a second layer of conductive metal, etc. on top, a suitable photoresist is applied on top of this second layer, exposed and developed to form a resist pattern, and a third layer is formed. and then,
The above-mentioned second layer is energized, the above-mentioned resist pattern is used as a mask material, and a metal or the like having a high selectivity for etching of the second layer is applied only to the areas on the second layer where there is no resist pattern. , by electroplating or the like to form a fourth layer, and then use the fourth layer as a mask material to form a third layer. The second and first layers are sequentially etched by RIE or the like to form a submicron pattern.
〈作用〉
上記のように本発明では、ＳＯＧ膜による平坦化工程が
ない為、前記した様なＳＯＧの特性の為に起こる問題点
が無い。<Function> As described above, in the present invention, since there is no planarization process using the SOG film, there are no problems caused by the characteristics of SOG as described above.
又第４の層が第２の層のエツチングに対して選択比の高
いものを用いることにより、第４の層かえ
必要な部分に一定以上の量され形成出来れば、原理上問
題が無い為、第４の層の均−性及び制御性を必要としな
い。したがって量産に適していることになる。In addition, if the fourth layer has a high etching selectivity for the second layer and can be formed in a certain amount or more in the area where the fourth layer needs to be replaced, there is no problem in principle. The uniformity and controllability of the fourth layer is not required. Therefore, it is suitable for mass production.
〈実施例〉
次に、本発明の一実施例を図面を参照して詳細に説明す
る。<Example> Next, an example of the present invention will be described in detail with reference to the drawings.
第１図（ａ）〜（ｃ）は本発明の一実施例に係わるパタ
ーン形成工程を示す図である。FIGS. 1(a) to 1(c) are diagrams showing a pattern forming process according to an embodiment of the present invention.
まず第１図（ａ）に示す如く基板１にレジスト０ＦＰＲ
−８００（東京応化製）を１μｍの厚さで塗布し、１４
０℃で２０分ベークして第１の層２を形成し、次いで、
ＥＢ蒸着法でＴｉ膜を４００ＯＡ蒸着し、第２の層３を
形成し、その上にレジス）ＯＦＰＲ−８００で０．５μ
ｍ幅と６μｍ幅のラインパターンをそれぞれ形成し、第
３の層４Ｉ及び４２を形成した。First, as shown in FIG. 1(a), a resist 0FPR is applied to the substrate 1.
-800 (manufactured by Tokyo Ohka) with a thickness of 1 μm,
Bake at 0°C for 20 minutes to form the first layer 2, then
A Ti film of 400 OA was deposited using the EB evaporation method to form the second layer 3, and a resist film of 0.5 μm was formed using OFPR-800 on top of the second layer 3.
Line patterns of m width and 6 μm width were respectively formed to form the third layers 4I and 42.
次に、電解メッキ法を用いて第２の層３を電極とし、第
３の層４１及び４２をマスク材として、第１図（ｂ）に
示すように第３の層４１及び４２の無い部分に、Ａｕ膜
を１００ＯＡ形成し、第４の層５を形成した。Next, using the electrolytic plating method, the second layer 3 is used as an electrode, and the third layers 41 and 42 are used as a mask material, and the parts without the third layers 41 and 42 are removed as shown in FIG. Then, a 100 OA Au film was formed to form the fourth layer 5.
その次に、ＲＩ’Ｅ法で第４の層５をマスク材として、
まず第２の層３をＣＦ４ガスを用いてエツチングした。Next, by using the RI'E method, the fourth layer 5 is used as a mask material,
First, the second layer 3 was etched using CF4 gas.
このとき、第４の層のＡｕ膜と第２の層のＴｉ膜との選
択比は１００以上あるので、良好なエツチングが出来る
。次いで第４の層５と前工程で選択エツチングで形成さ
れた第２の層３Ｉをマスクとして、０２ガスを用いて第
１の層２をエツチングした。その結果、第１図（ｃ）に
示すようにパターン幅が０．５μｍと６μｍのスペース
パターンを形成することができた。At this time, since the selectivity between the fourth layer of Au film and the second layer of Ti film is 100 or more, good etching can be achieved. Next, using the fourth layer 5 and the second layer 3I formed by selective etching in the previous step as a mask, the first layer 2 was etched using 02 gas. As a result, space patterns with pattern widths of 0.5 μm and 6 μm could be formed as shown in FIG. 1(c).
〈発明の効果〉
以上のように本発明によれば、パターンの反転ｌこ
化〜℃金属メッキ等を用いることにより、ノ（ターン幅
がサブミクロン以下のスペースパターン及び、パターン
幅がサブミクロン以下のものとサブミクロン以上のもの
が混在するスペースパターンを、歩留り良く並びに再現
性良く得ることが出来、量産が容易となる。<Effects of the Invention> As described above, according to the present invention, by using pattern inversion to C metal plating, etc. It is possible to obtain a space pattern with a mixture of micron and submicron or larger dimensions with good yield and reproducibility, making mass production easy.
第１図（ａ）乃至（ｃ）は、それぞれ本発明の一実施例
の工程を示す断面図、第２図（ａ）乃至（ｄ）及び第３
図（ａ） 、 （ｂ）はそれぞれ従来の方法及びその問
題点を説明するための断面図である。
ｌ・・・基板、２・・・有機膜層、３・・・導電層、４
１゜４２・・レジストパターン。
代理人 弁理士 杉 山 毅 至（他！名）（Ｃ１
第１図FIGS. 1(a) to (c) are cross-sectional views showing the steps of an embodiment of the present invention, FIGS. 2(a) to (d) and 3.
Figures (a) and (b) are cross-sectional views for explaining the conventional method and its problems, respectively. l...Substrate, 2...Organic film layer, 3...Conductive layer, 4
1゜42...Resist pattern. Agent: Patent attorney Takeshi Sugiyama (and others!) (C1 Figure 1)
Claims (1)
程と、 該第２の層上に所望のホトレジストを塗布し、露光、現
像を施して第３の層としてのレジストパターンを形成す
る工程と、 上記第２の層に通電し、上記レジストパターンをマスク
材として、上記第２の層上に第４の層としての所望の金
属を電解メッキ等により形成する工程と、 該第４の層をマスク材として上記第３、第２及び第１の
層にエッチングを施して、上記第３の層のレジストパタ
ーンを反転したパターンを形成する工程を含んでなるこ
とを特徴とするパターン形成方法。 ２、前記第４の層が第２の層のエッチングに対して、選
択比が高い材料の組み合わせで構成してなることを特徴
とする特許請求の範囲第１項記載のパターン形成方法。 ３、前記第３の層のパターン幅が、サブミクロンのもの
とサブミクロン以上のものが共存することを特徴とする
特許請求の範囲第１項記載のパターン形成方法。[Claims] 1. A step of forming a first layer on a substrate; a step of forming a second layer of a conductive material on the first layer; and a step of forming a desired layer on the second layer. a step of applying a photoresist, exposing and developing to form a resist pattern as a third layer; and applying electricity to the second layer and using the resist pattern as a mask material to form a resist pattern on the second layer. A step of forming a desired metal as a fourth layer by electrolytic plating or the like, and etching the third, second and first layers using the fourth layer as a mask material to form the third layer. A pattern forming method comprising the step of forming a pattern that is an inversion of a resist pattern. 2. The pattern forming method according to claim 1, wherein the fourth layer is made of a combination of materials that have a high etching selectivity for the second layer. 3. The pattern forming method according to claim 1, wherein the pattern width of the third layer is submicron or larger than submicron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30065087A JPH01140629A (en) | 1987-11-26 | 1987-11-26 | Pattern forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30065087A JPH01140629A (en) | 1987-11-26 | 1987-11-26 | Pattern forming method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01140629A true JPH01140629A (en) | 1989-06-01 |
Family
ID=17887410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30065087A Pending JPH01140629A (en) | 1987-11-26 | 1987-11-26 | Pattern forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01140629A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0358350A2 (en) * | 1988-09-08 | 1990-03-14 | Kabushiki Kaisha Toshiba | Forming a Prescribed Pattern on a Semiconductor Device Layer |
| JP2006303500A (en) * | 2005-04-19 | 2006-11-02 | Samsung Electronics Co Ltd | Fine pattern formation method of semiconductor device using fine-pitch hard mask |
-
1987
- 1987-11-26 JP JP30065087A patent/JPH01140629A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0358350A2 (en) * | 1988-09-08 | 1990-03-14 | Kabushiki Kaisha Toshiba | Forming a Prescribed Pattern on a Semiconductor Device Layer |
| JP2006303500A (en) * | 2005-04-19 | 2006-11-02 | Samsung Electronics Co Ltd | Fine pattern formation method of semiconductor device using fine-pitch hard mask |
| US8062981B2 (en) | 2005-04-19 | 2011-11-22 | Samsung Electronics Co., Ltd. | Method of forming pattern using fine pitch hard mask |
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