JPS63155813A - Hysteresis circuit - Google Patents
Hysteresis circuitInfo
- Publication number
- JPS63155813A JPS63155813A JP61301502A JP30150286A JPS63155813A JP S63155813 A JPS63155813 A JP S63155813A JP 61301502 A JP61301502 A JP 61301502A JP 30150286 A JP30150286 A JP 30150286A JP S63155813 A JPS63155813 A JP S63155813A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output
- operational amplifier
- positive
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
- 239000006185 dispersion Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は入出力伝達特性にある一定幅の不感帯を設け
たヒステリシス回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hysteresis circuit in which a dead zone of a certain width is provided in input/output transfer characteristics.
第３図は従来のヒステリシス回路を示す回路図である。 FIG. 3 is a circuit diagram showing a conventional hysteresis circuit.
同図において、１は入力信号Ｍｉｎが入力する入力端子
、２は反転入力端子に入力信号Ｍｉｎが入力する演算増
幅器、３はこの演算増幅器２の出力端子に接続され、出
力信号Ｖｏｕｔ ｆＩ：出力する出力端子、４は一端が
出力端子３に接続され、他端が演算増幅器２の非反転入
力端子に接続された抵抗値Ｒ１の抵抗、５は一端が抵抗
４の他端に接続され、他端が接地された抵抗値Ｒ２の抵
抗である。次に、上記構成によるヒステリシス回路は入
力端子Ｗｉｎが演算増幅器２の反転入力端子に入力する
。そして、演算増幅器２の非反転入力端子に、演算増幅
器２の出力端子と接地間に直列接続された抵抗４および
抵抗５の中点が接続され、正帰還をかけて出力端子３か
ら出力画号Ｖｏｕｔが出力する。そして、この回路の入
出力伝達特性を第４図に示すことができる。まず、λカ
信号Ｖｌｎが負から正へと変化する場合、出力信号Ｖｏ
ｕｔが正から負へと急激に変化するときの入力信号レベ
ル＋ｖ１は演算増幅器２の正の最大出力電圧をＥ＋ と
すると（１）式で与えられる。In the figure, 1 is an input terminal to which the input signal Min is input, 2 is an operational amplifier to which the input signal Min is input to the inverting input terminal, and 3 is connected to the output terminal of this operational amplifier 2, and outputs an output signal Vout fI. The output terminal 4 is a resistor with a resistance value R1, one end of which is connected to the output terminal 3, the other end of which is connected to the non-inverting input terminal of the operational amplifier 2, and 5, one end of which is connected to the other end of the resistor 4, and the other end of which is connected to the non-inverting input terminal of the operational amplifier 2. is a grounded resistor with a resistance value R2. Next, in the hysteresis circuit having the above configuration, the input terminal Win is inputted to the inverting input terminal of the operational amplifier 2. Then, the midpoint of a resistor 4 and a resistor 5 connected in series between the output terminal of the operational amplifier 2 and the ground is connected to the non-inverting input terminal of the operational amplifier 2, and positive feedback is applied to the output image signal from the output terminal 3. Vout outputs. The input/output transfer characteristics of this circuit can be shown in FIG. First, when the λ power signal Vln changes from negative to positive, the output signal Vo
The input signal level +v1 when ut suddenly changes from positive to negative is given by equation (1), where E+ is the maximum positive output voltage of the operational amplifier 2.
逆に、出力信号が負から正へと急激に変化するときの入
力信号レベル−ｖ２は演算増幅器２の負の最大出力電圧
を−Ｅ！とすると（２）式で与えられる。Conversely, the input signal level -v2 when the output signal changes rapidly from negative to positive is the negative maximum output voltage of operational amplifier 2 -E! Then, it is given by equation (2).
したがって、ビステリシス幅は（３）式で与えられる。Therefore, the bisteresis width is given by equation (3).
上述した従来のビステリシス回路は、その演算増幅器の
最大出力電圧が製造条件、温度などの猪条件によりバラ
ツキや変動があり、特に集積化した場合に更にバラツキ
や変動が大きくなるという欠点がある。The conventional bisteresis circuit described above has the drawback that the maximum output voltage of its operational amplifier varies and fluctuates depending on manufacturing conditions, temperature, and other conditions, and especially when it is integrated, the dispersion and fluctuation become even larger.
この発明のヒステリシス回路は、演算増幅器の非反転入
力端子に、この演算増幅器の出力信号の極性によりどち
らか一方が導通するスイクチング素子を介して所定の基
準電圧を供給するようにしたものである。The hysteresis circuit of the present invention supplies a predetermined reference voltage to a non-inverting input terminal of an operational amplifier via a switching element, one of which is rendered conductive depending on the polarity of the output signal of the operational amplifier.
この発明は演算増幅器の最大出力電圧を所望の値にバラ
ツキや変動がなく、安定に保つことができる。According to the present invention, the maximum output voltage of the operational amplifier can be kept stable at a desired value without variations or fluctuations.
第１図はこの発明に係るビステリシス回路の一実施例を
示す回路図でちる。同図において、６は一端が基準電源
端子Ｔに接続され、他端が別の基準電源端子８に接続さ
れ、第１可変端子に電圧子ｖ、 １生成し第２可変端子
に電圧−ｖ２を生成する可変抵抗、９は入力端子が出力
端子３に接続されたインバーｉ、１ａはゲートがインバ
ータ９の出力端子に接続され、ドレインが演算増幅器２
の非反転入力端子に接続され、ソースが可変抵抗６の第
２可変端子に接続された第１スインテング素子、１１は
ゲートがインバータ９の入力端子に接続され、ドレイン
が可変抵抗８の第１可変端子に接続され、ソースが演算
増幅器２の非反転入力端子に接続された第２スイッチン
グ素子である。FIG. 1 is a circuit diagram showing an embodiment of a bisteresis circuit according to the present invention. In the same figure, 6 has one end connected to a reference power supply terminal T, and the other end connected to another reference power supply terminal 8, and generates a voltage V, 1 at the first variable terminal and a voltage -V2 at the second variable terminal. The generated variable resistor, 9 is an inverter i whose input terminal is connected to the output terminal 3, 1a is the gate of which is connected to the output terminal of the inverter 9, and the drain of which is the operational amplifier 2.
A first swinging element 11 has a gate connected to the input terminal of the inverter 9 and a drain connected to the first variable terminal of the variable resistor 8. a second switching element whose source is connected to the non-inverting input terminal of the operational amplifier 2;
次に、上記構成によるヒステリシス回路は入力信号ｖｌ
ｎが演算増幅器２の反転入力端子に入力する。そして、
演算増幅器２の非反転入力端子に第１スイッチング素子
１Ｇのドレインと第２スイッチング素子１１のソースと
の接続点が接続され正帰還をかけて出力端子３から出力
信号Ｖｏｕ ｔが出力する。そして、この回路の入出力
伝達特性を第２図に示すことができる。まず、入力信号
が負から正へと変化する場合に、入力信号Ｖｉｎが負の
とき演算増幅器２の出力は正の最大出力電圧になってお
シ、第２スイッチング素子１１が導通し第１スイッチン
グ素子１Ｇがインバータ９によシ非導通になる。したが
って、電源端子Ｔおよび８の間に接続された可変抵抗６
の第１可変端子に生成される電圧子Ｖ、が演算増幅器２
の非反転入力端子に入力し、反転入力端子に入力する入
力信号Ｍｉｎが電圧子Ｖ、 を超えると出力信号は急
激に正から負へと変化する。次に入力信号Ｗｉｎが正か
ら負へと変化するが、入力信号Ｍｉｎが正のとき演算増
幅器２の出力は負の最大出力電圧になっておρ、第１ス
イッチング素子１０が導通し第２スイッチング素子１１
が非導通になる。したがって、可変抵抗８の第２可変端
子に生成される電圧−■２が演算増幅器２の非反転入力
端子に入力し、入力信号Ｍｉｎが電圧−ｖ２を超えると
出力信号Ｖｏｕｔは急激に負から正へと変化する。した
がって、ヒステリシス幅は＋Ｖｌ （Ｖｉ）で与えら
れるので、この値は電源端子７および８に供給される電
源電圧と抵抗６の抵抗分割比のみから決まり、演算増幅
器２の最大出力電圧に依存しないのでヒステリシス幅を
安定にすることができる。Next, the hysteresis circuit with the above configuration receives the input signal vl
n is input to the inverting input terminal of operational amplifier 2. and,
A connection point between the drain of the first switching element 1G and the source of the second switching element 11 is connected to the non-inverting input terminal of the operational amplifier 2, and positive feedback is applied thereto, and an output signal Vout is output from the output terminal 3. The input/output transfer characteristics of this circuit can be shown in FIG. First, when the input signal changes from negative to positive, the output of the operational amplifier 2 becomes the positive maximum output voltage when the input signal Vin is negative, and the second switching element 11 conducts and the first switching element 11 becomes conductive. Element 1G becomes non-conductive due to inverter 9. Therefore, variable resistor 6 connected between power supply terminals T and 8
The voltage voltage V generated at the first variable terminal of the operational amplifier 2
When the input signal Min input to the non-inverting input terminal and input to the inverting input terminal exceeds the voltage voltage V, the output signal suddenly changes from positive to negative. Next, the input signal Win changes from positive to negative, but when the input signal Min is positive, the output of the operational amplifier 2 becomes the negative maximum output voltage, and the first switching element 10 becomes conductive and the second switching element 10 becomes conductive. Element 11
becomes non-conductive. Therefore, when the voltage -2 generated at the second variable terminal of the variable resistor 8 is input to the non-inverting input terminal of the operational amplifier 2, and the input signal Min exceeds the voltage -v2, the output signal Vout suddenly changes from negative to positive. Changes to. Therefore, since the hysteresis width is given by +Vl (Vi), this value is determined only by the power supply voltage supplied to power supply terminals 7 and 8 and the resistance division ratio of resistor 6, and does not depend on the maximum output voltage of operational amplifier 2. The hysteresis width can be stabilized.
以上詳細に説明したように、この発明に係るヒステリシ
ス回路によれば、演算増幅器の最大出力電圧に依存しな
い電圧を非反転入力端子に供給することによシ、ヒステ
リシス＠を所望の値に安定に保つことができる効果があ
る。As explained in detail above, according to the hysteresis circuit according to the present invention, the hysteresis can be stably maintained at a desired value by supplying a voltage that does not depend on the maximum output voltage of the operational amplifier to the non-inverting input terminal. There is an effect that can be maintained.
【図面の簡単な説明】
第１図はこの発明に係るヒステリシス回路の−実施例を
示す回路図、第２図は第１図の入出力伝達特性を示す図
、第３図は従来のヒステリシス回路を示す回路図、第４
図は第３図の入出力伝達特性を示す図である。
１・・・拳入力端子、２・・・・演算増幅器、３・・・
・出力端子、４および５・・・・抵抗、６・・・・可変
抵抗、Ｔおよび８・・・・電源端子、９・Φ・・インバ
ータ、１０・・・−第１スイッチング素子、１１・・・
・第２スイッチング素子。[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing an embodiment of the hysteresis circuit according to the present invention, Fig. 2 is a diagram showing the input/output transfer characteristics of Fig. 1, and Fig. 3 is a conventional hysteresis circuit. Circuit diagram showing 4th
The figure is a diagram showing the input/output transfer characteristics of FIG. 3. 1... fist input terminal, 2... operational amplifier, 3...
- Output terminals, 4 and 5...Resistor, 6...Variable resistor, T and 8...Power supply terminal, 9, Φ...Inverter, 10...-First switching element, 11...・・・
-Second switching element.
Claims (1)
どちらか一方が導通し他方が非導通に制御され、それぞ
れ一方の端子が共に前記演算増幅器の非反転入力端子に
接続された第１スイッチング素子および第２スイッチン
グ素子と、この第１スイッチング素子および第２スイッ
チング素子の他方の端子に相異なる基準電圧を供給する
手段とを備え、前記演算増幅器の反転入力端子に信号が
入力し、出力端子から信号を取り出すことを特徴とする
ヒステリシス回路。an operational amplifier; and a first switching element, one of which is controlled to be conductive and the other to be non-conductive depending on the polarity of the output signal of the operational amplifier, and each of which has one terminal connected to a non-inverting input terminal of the operational amplifier; a second switching element, and means for supplying different reference voltages to the other terminals of the first switching element and the second switching element, wherein a signal is input to the inverting input terminal of the operational amplifier, and a signal is input from the output terminal. A hysteresis circuit characterized by taking out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61301502A JPS63155813A (en) | 1986-12-19 | 1986-12-19 | Hysteresis circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61301502A JPS63155813A (en) | 1986-12-19 | 1986-12-19 | Hysteresis circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63155813A true JPS63155813A (en) | 1988-06-29 |
Family
ID=17897684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61301502A Pending JPS63155813A (en) | 1986-12-19 | 1986-12-19 | Hysteresis circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63155813A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0355912A (en) * | 1989-07-24 | 1991-03-11 | Nec Corp | Hysteresis circuit |
| JPH05167400A (en) * | 1991-12-13 | 1993-07-02 | Yamatake Honeywell Co Ltd | Hysteresis circuit |
| EP1235348A1 (en) * | 2001-02-14 | 2002-08-28 | Siemens Aktiengesellschaft | Hysteresis circuit |
-
1986
- 1986-12-19 JP JP61301502A patent/JPS63155813A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0355912A (en) * | 1989-07-24 | 1991-03-11 | Nec Corp | Hysteresis circuit |
| JPH05167400A (en) * | 1991-12-13 | 1993-07-02 | Yamatake Honeywell Co Ltd | Hysteresis circuit |
| EP1235348A1 (en) * | 2001-02-14 | 2002-08-28 | Siemens Aktiengesellschaft | Hysteresis circuit |
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