JPH051646B2 - - Google Patents
Info
- Publication number
- JPH051646B2 JPH051646B2 JP59142362A JP14236284A JPH051646B2 JP H051646 B2 JPH051646 B2 JP H051646B2 JP 59142362 A JP59142362 A JP 59142362A JP 14236284 A JP14236284 A JP 14236284A JP H051646 B2 JPH051646 B2 JP H051646B2
- Authority
- JP
- Japan
- Prior art keywords
- mos
- load
- differential amplifier
- offset adjustment
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003321 amplification Effects 0.000 claims description 9
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 9
- 101710132461 Molybdenum cofactor sulfurase Proteins 0.000 description 47
- 230000000694 effects Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 101150090280 MOS1 gene Proteins 0.000 description 4
- 101100401568 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) MIC10 gene Proteins 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101100402276 Arabidopsis thaliana MOS14 gene Proteins 0.000 description 1
- 101710116852 Molybdenum cofactor sulfurase 1 Proteins 0.000 description 1
- 101710116850 Molybdenum cofactor sulfurase 2 Proteins 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45624—Indexing scheme relating to differential amplifiers the LC comprising balancing means, e.g. trimming means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45632—Indexing scheme relating to differential amplifiers the LC comprising one or more capacitors coupled to the LC by feedback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45664—Indexing scheme relating to differential amplifiers the LC comprising one or more cascaded inverter stages as output stage at one output of the dif amp circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45681—Indexing scheme relating to differential amplifiers the LC comprising offset compensating means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45722—Indexing scheme relating to differential amplifiers the LC comprising one or more source followers, as post buffer or driver stages, in cascade in the LC
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は差動増幅回路に係り、特にオフセツト
調整を良好に行うのに好適な差動増幅回路に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a differential amplifier circuit, and particularly to a differential amplifier circuit suitable for performing offset adjustment well.
従来のオフセツト調整付モノリシツク差動増幅
回路としては、CMOS増幅回路を例にとれば第
１図に示す回路構成のものがある。第１図におい
て、１は反転入力端子、２は非反転入力端子、３
は出力端子、４ａ，４ｂはオフセツト調整端子、
５は高電位電源電圧端子、６は低電位電源電圧端
子で、定電流源１０、駆動MOS１１，１２、負
荷MOS１３，１４および抵抗１５，１６で第１
の増幅段を構成し、定電流源２０と駆動MOS２
１とで第２の増幅段を構成し、また、定電流源３
０と駆動MOS３１とでソースフオロワ形の出力
段を構成し、さらに周波数補償用コンデンサ３２
を設けてある。
As a conventional monolithic differential amplifier circuit with offset adjustment, there is a CMOS amplifier circuit having a circuit configuration shown in FIG. 1, for example. In Figure 1, 1 is an inverting input terminal, 2 is a non-inverting input terminal, and 3 is an inverting input terminal.
is the output terminal, 4a and 4b are the offset adjustment terminals,
5 is a high potential power supply voltage terminal, 6 is a low potential power supply voltage terminal, and the first
constitutes an amplification stage, and includes a constant current source 20 and a drive MOS 2.
1 constitutes a second amplification stage, and constant current source 3
0 and a drive MOS 31 constitute a source follower type output stage, and a frequency compensation capacitor 32
is provided.
オフセツト調整は、第１図に示すように、負荷
MOS１３，１４にそれぞれ直列に抵抗１５，１
６を接続した回路のそれぞれの接続点の電位が等
しくなるようにオフセツト調整端子４ａ，４ｂの
外部に可変抵抗を接続してパランスをとつて行う
ようにしてある。 Offset adjustment is performed by adjusting the load as shown in Figure 1.
Resistors 15 and 1 are connected in series with MOS13 and 14, respectively.
Variable resistors are connected externally to the offset adjustment terminals 4a and 4b so that the potentials at the respective connection points of the circuit connected to the offset adjustment terminals 4a and 4b are balanced.
しかし、オフセツト調整のために負荷MOS１
３，１４にそれぞれ抵抗１５，１６を直列に接続
したことにより負荷MOS１３，１４が分担する
電圧が増加し、駆動MOS１１および１２の動作
範囲がせばめられ、その結果、扱える入力電圧の
範囲がせまくなるという欠点を有している。すな
わち、第１図の構成では、単一電源で動作させる
場合に零入力電圧が扱えないという問題がある。 However, due to offset adjustment, load MOS1
By connecting resistors 15 and 16 in series to MOS transistors 3 and 14, respectively, the voltage shared by load MOS transistors 13 and 14 increases, the operating range of drive MOS transistors 11 and 12 becomes narrower, and as a result, the range of input voltage that can be handled becomes narrower. It has the following drawbacks. That is, the configuration shown in FIG. 1 has a problem in that it cannot handle quiescent voltage when operated with a single power supply.
本発明は上記に鑑みてなされたもので、その目
的とするところは、入力電圧範囲が広く、しか
も、オフセツト調整を良好に行うことができる差
動増幅回路を提供することにある。
The present invention has been made in view of the above, and an object of the present invention is to provide a differential amplifier circuit that has a wide input voltage range and can perform offset adjustment well.
本発明の特徴は、駆動素子と負荷素子を直列接
続したものを一対もつ差動増幅対を備えた差動増
幅回路において、前記差動増幅対の少なくともど
ちらか一方の負荷素子に副負荷素子を並列に接続
し、前記副負荷素子の制御電圧を可変として前記
差動増幅回路のオフセツト調整を行なうように構
成した点にある。
A feature of the present invention is that, in a differential amplifier circuit equipped with a differential amplifier pair having a pair of drive elements and load elements connected in series, an auxiliary load element is provided for at least one of the load elements of the differential amplifier pair. The differential amplifier circuit is connected in parallel, and the control voltage of the sub load element is made variable to adjust the offset of the differential amplifier circuit.
以下本発明を第２図〜第４図、第６図、第７図
に示した実施例および第５図を用いて詳細に説明
する。
The present invention will be described in detail below with reference to the embodiments shown in FIGS. 2 to 4, FIG. 6, and FIG. 7, and FIG.
第２図は本発明の差動増幅回路の一実施例を示
す回路図で、第１図と同一部分は同じ符号で示
し、ここでは説明する。第２図においては、第１
図の負荷MOS１３，１４をそれぞれ負荷MOS１
３ａと副負荷MOS１３ｂ、負荷MOS１４ａと副
負荷MOS１４ｂとを並列接続したものに代えて
あり、これらを図のように接続して抵抗１５，１
６をなくした構成としてある。なお、駆動MOS
１１，１２はＰ−チヤネル形、その他のものはＮ
−チヤネル形で、また、駆動MOS３１のように
サブストレー電極が図示してないものは、Ｐ−チ
ヤネル形のものは低電位電源電圧端子５、Ｎ−チ
ヤネル形のものは低電位電源電圧端子６に接続し
てある。そして、負荷MOS１３ａ，１４ａおよ
び副負荷MOS１３ｂ，１４ｂの寸法の設定に当
つては、第１図の負荷MOS１３，１４の寸法と
なるようにそれぞれ分割したものを用いるように
してもよく、負荷MOS１３，１４と同一寸法の
負荷MOS１３ａ，１４ａに副負荷MOS１３ｂ，
１４ｂを追加するようにしてもよい。ただし、こ
の場合、ゲート幅の寸法のみを可変にし、ゲート
長は同寸法で固定とすることが必要である。 FIG. 2 is a circuit diagram showing an embodiment of the differential amplifier circuit of the present invention, and the same parts as in FIG. 1 are designated by the same reference numerals and will be explained here. In Figure 2, the first
Load MOS13 and 14 in the figure are respectively load MOS1.
3a and the auxiliary load MOS 13b, and the load MOS 14a and the auxiliary load MOS 14b are connected in parallel, and these are connected as shown in the figure and the resistors 15 and 1 are connected in parallel.
It has a configuration that eliminates the number 6. In addition, the drive MOS
11 and 12 are P-channel type, others are N
- channel type, and those with no substray electrodes such as the drive MOS 31 are connected to the low potential power supply voltage terminal 5 for the P-channel type and the low potential power supply voltage terminal 6 for the N-channel type. It's connected. When setting the dimensions of the load MOSs 13a and 14a and the auxiliary load MOSs 13b and 14b, they may be divided so that they have the dimensions of the load MOSs 13 and 14 shown in FIG. Load MOS 13a and 14a with the same dimensions as 14 and auxiliary load MOS 13b,
14b may be added. However, in this case, it is necessary to make only the dimension of the gate width variable and to fix the gate length to the same dimension.
次に、オフセツト調整方法について説明する。
反転入力端子１と出力端子３とを接続し、非反転
入力端子２を接地電位にしてからオフセツト調整
端子４ｂに印加する電圧を変え、出力端子３の電
圧が零になるように調整する。 Next, the offset adjustment method will be explained.
After connecting the inverting input terminal 1 and the output terminal 3 and setting the non-inverting input terminal 2 to the ground potential, the voltage applied to the offset adjustment terminal 4b is changed so that the voltage at the output terminal 3 becomes zero.
このようなオフセツト調整動作により、負荷
MOS１４ａに並列に副負荷MOS１４ｂの制御電
圧VGが変化するため、副負荷MOS１４ｂに流れ
る電流ISUBは、MOSの飽和領域動作で考えると、
次式の関係により変わることになり、オフセツト
調整端子４ｂがある側の第１の増幅段の増幅回路
（駆動MOS１２、負荷MOS１４ａ、副負荷MOS
１４ｂからなる部分）に流れる電流の増減とな
る。 This offset adjustment operation reduces the load
Since the control voltage V G of the auxiliary load MOS 14b in parallel with the MOS 14a changes, the current I SUB flowing through the auxiliary load MOS 14b is calculated as follows when considering the operation in the saturation region of the MOS.
It changes according to the relationship of the following equation, and the amplifier circuit (drive MOS 12, load MOS 14a, auxiliary load MOS 14a, auxiliary load MOS
14b)).
ISUB＝１／２βＷ／Ｌ（VG−VT）2 ……(1)
ここに、
β；副負荷MOS１４ｂのプロセス定数
Ｗ／Ｌ；副負荷MOS１４ｂの寸法比
VT；副負荷MOS１４ｂのしきい電圧
すなわち、VGを大きくすると、オフセツト調
整端子４ｂ側の増幅回路の電流ISUBが増し、VGを
小さくすると、電流ISUBが減少する。一方、オフ
セツト調整端子４ｂのある側と反対側の増幅回路
に流れる電流は、上記の場合と反対方向に変化す
る。この結果、第１の増幅段の両側の対となる増
幅回路がバランスするようにすることができ、オ
フセツトの調整が可能となる。 I SUB = 1/2βW/L (V G −V T ) 2 ...(1) Here, β: Process constant W/L of the sub-load MOS14b; Dimensional ratio of the sub-load MOS14b V T ; When the threshold voltage, that is, V G, is increased, the current I SUB of the amplifier circuit on the offset adjustment terminal 4b side increases, and when V G is decreased, the current I SUB is decreased. On the other hand, the current flowing through the amplifier circuit on the side opposite to the side where the offset adjustment terminal 4b is located changes in the opposite direction to that in the above case. As a result, the pair of amplifier circuits on both sides of the first amplifier stage can be balanced, and the offset can be adjusted.
また、反転入力端子１または非反転入力端子２
に印加できる低電位側の入力電圧は駆動MOS１
１および１２のしきい電圧をそれぞれVTD、負荷
MOS１３ａと副負荷MOS１３ｂおよび負荷
MOS１４ａと副負荷MOS１４ｂのしきい電圧を
それぞれVTLとすると、MOSが飽和領域動作を行
う範囲では、ほぼ｜VTD｜−VTLの値まで扱うこ
とができる。したがつて、入力電圧は使用する
MOSのしきい電圧のみに依存するため、オフセ
ツト調整しているにもかかわらず、最小限の電圧
振幅損失にとどまり、広範囲な動作領域が得られ
る。そして、｜VTD｜、VTLをほぼ等しいしきい電
圧値に選んでおけば、駆動MOS１１および１２
には基板バイアス効果が加わるため、さらに｜
VTD｜が大きくなるので、｜VTD｜−VTL＞０の条
件を十分に満足し、単一電源動作において零入力
電圧まで扱えることになり、広い入力電圧範囲を
得ることができる。 Also, inverting input terminal 1 or non-inverting input terminal 2
The input voltage on the low potential side that can be applied to the drive MOS1
1 and 12 threshold voltages, V TD and load, respectively.
MOS13a and auxiliary load MOS13b and load
Assuming that the threshold voltages of the MOS 14a and the sub-load MOS 14b are VTL , it is possible to handle values up to approximately |V TD |−V TL in the range where the MOS operates in the saturation region. Therefore, the input voltage used is
Because it depends only on the threshold voltage of the MOS, voltage amplitude loss is kept to a minimum despite offset adjustment, and a wide operating range can be obtained. If |V TD | and V TL are selected to have approximately equal threshold voltage values, the drive MOSs 11 and 12
Since the substrate bias effect is added to |
Since V TD | becomes large, the condition of |V TD |−V TL >0 is fully satisfied, and even a zero input voltage can be handled in single power supply operation, making it possible to obtain a wide input voltage range.
上記した本発明の実施例によれば、差動増幅回
路の第１の増幅段の対となる増幅回路の負荷
MOS１３ａ，１４ａにそれぞれ副負荷MOS１３
ｂ，１４ｂを並列に設け、その副負荷MOS１４
ｂを制御することにより上記各増幅回路の電流を
互いに反対方向に可変できるので、オフセツト調
整が可能である。 According to the embodiment of the present invention described above, the load of the amplifier circuit that is a pair of the first amplifier stage of the differential amplifier circuit is
MOS13a and 14a each have auxiliary load MOS13
b, 14b are provided in parallel, and its auxiliary load MOS14
By controlling b, the currents of the respective amplifier circuits can be varied in opposite directions, so offset adjustment is possible.
また、オフセツト調整のために付加した副負荷
MOS１３ｂ，１４ｂは上記各増幅回路の負荷
MOS１３ａ，１４ａにそれぞれ並列に設けてあ
るので、電圧損失がなく、しかも、入力電圧範囲
を広くとることができる。 In addition, the auxiliary load added for offset adjustment
MOS13b and 14b are the loads of each of the above amplifier circuits.
Since they are provided in parallel with the MOSs 13a and 14a, there is no voltage loss and the input voltage range can be widened.
なお、第２図に示す実施例では、副負荷MOS
１４ｂの制御によりオフセツト調整をしている
が、第３図に示すように、他方の副負荷MOS１
３ｂにもオフセツト調整端子４ａを設けて、両者
でオフセツト調整を行うようにしてもよく、同様
の効果を得ることができる。 Note that in the embodiment shown in Fig. 2, the auxiliary load MOS
Offset adjustment is performed by controlling MOS 14b, but as shown in Fig. 3, the other auxiliary load MOS 1
3b may also be provided with an offset adjustment terminal 4a so that both can perform offset adjustment, and the same effect can be obtained.
また、第４図は本発明の他の実施例を示す第２
図に相当する回路図で、第２図と同一部は同じ符
号で示してある。第２図と異なる点は、副負荷
MOS１４ｂはMOS１４ｃとカレントミラーを構
成し、オフセツト調整端子４ｂに電流を注入して
制御するようにしたことにある。これによる効果
は、カレントミラーにより第１の増幅段の電流を
微小にできることであり、第２図と第４図の回路
を比較したとき、オフセツト調整端子４ｂから見
た電圧Vpff（第４図ではVpffは電流の換算値）と出
力端子３に得られる電圧Vpとの関係は第５図に
示すようになる。第５図において、ａ曲線は第２
図の回路の場合、ｂ曲線は第４図の回路の場合で
あり、オフセツト調整としては傾斜Vp／Vpffが小
さい方が好ましく、ｂ曲線の場合の方がよい。こ
のことは、Vpffの範囲が広くとれるため、Vpffを
大きく変えても、Vpの変化を小さくできること
を示している。したがつて、第２図の回路に比
べ、オフセツト調整時の微調整が容易になり、さ
らに安定にオフセツト調整をすることができる。
しかも、この場合も第２図の回路の場合と同様、
第１の増幅段にオフセツト調整による電圧振幅損
失が生じないので、広範囲の入力電圧を扱うこと
ができる。 In addition, FIG. 4 shows a second embodiment of the present invention.
This is a circuit diagram corresponding to the figure, and the same parts as in FIG. 2 are designated by the same reference numerals. The difference from Figure 2 is that the auxiliary load
The MOS 14b forms a current mirror with the MOS 14c, and is controlled by injecting a current into the offset adjustment terminal 4b. The effect of this is that the current in the first amplification stage can be made very small by the current mirror, and when comparing the circuits in FIGS. 2 and 4, the voltage V pff seen from the offset adjustment terminal 4b ( The relationship between V pff (current conversion value) and the voltage V p obtained at the output terminal 3 is as shown in FIG. In Figure 5, the a curve is the second
In the case of the circuit shown in the figure, the b curve corresponds to the circuit shown in FIG. 4, and for offset adjustment, it is preferable that the slope V p /V pff is smaller, and the b curve is better. This shows that since the range of V pff can be wide, even if V pff is changed significantly, the change in V p can be made small. Therefore, compared to the circuit shown in FIG. 2, fine adjustment during offset adjustment is easier, and offset adjustment can be performed more stably.
Moreover, in this case as well, as in the case of the circuit in Figure 2,
Since no voltage amplitude loss occurs in the first amplification stage due to offset adjustment, a wide range of input voltages can be handled.
また、第６図は本発明のさらに他の実施例を示
す第２図に相当する回路図で、第２図、第４図と
同一部分は同じ符号で示してある。第６図の第４
図と異なるところは、MOS１４ｃとオフセツト
調整端子４ｂとの間に抵抗４１を接続した点にあ
る。第６図によれば、第４図のオフセツト調整は
電流であつたのに対して電圧で行うようになるだ
けで、効果は同一である。 Further, FIG. 6 is a circuit diagram corresponding to FIG. 2 showing still another embodiment of the present invention, and the same parts as in FIGS. 2 and 4 are indicated by the same reference numerals. 4 in Figure 6
The difference from the figure is that a resistor 41 is connected between the MOS 14c and the offset adjustment terminal 4b. According to FIG. 6, the offset adjustment in FIG. 4 is performed by voltage instead of current, and the effect is the same.
また、以上述べた実施例においては、すべてＰ
−チヤネル形MOSを第１の増幅段の駆動MOS１
１，１２として用いているが、これをＮ−チヤネ
ル形MOSとしてもよく、そのときの実施例を第
７図に示す。第７図において、１００，２００，
３０は定電流源、１０１，１０２は第１の増幅段
の駆動MOS、１０３，１０４は負荷MOS、１０
５，１０６はそれぞれ負荷MOS１０３，１０４
に並列に設けた副負荷MOS、２０１は第２の増
幅段の駆動MOS、３１は出力段の駆動MOS、３
２はコンデンサである。オフセツト調整端子４ａ
はセルフバイアス側の負荷MOS１０３に並列に
接続した副負荷MOS１０５から取り出してある。
この場合、これまでの実施例の場合と同様、副負
荷MOS１０６を制御するようにしてもよく、い
ずれも同様の効果が得られる。なお、この場合、
単一電源動作においては、定電流源１００が低電
位電源電圧端子６側に付いているので、零入力電
圧は扱えないが、高電位電圧側の範囲が拡大する
ので、入力電圧範囲を広くとれるという効果が得
られる。また、第７図の回路は、第４図、第６図
の場合と同様の効果もある。 In addition, in the embodiments described above, all P
-Channel type MOS is the drive MOS1 of the first amplification stage.
1 and 12, but this may also be an N-channel type MOS, and an embodiment thereof is shown in FIG. In FIG. 7, 100, 200,
30 is a constant current source, 101 and 102 are drive MOSs for the first amplification stage, 103 and 104 are load MOSs, and 10
5 and 106 are load MOS103 and 104 respectively
201 is a drive MOS for the second amplification stage, 31 is a drive MOS for the output stage, 3
2 is a capacitor. Offset adjustment terminal 4a
is taken out from the auxiliary load MOS 105 connected in parallel to the load MOS 103 on the self-bias side.
In this case, the auxiliary load MOS 106 may be controlled as in the previous embodiments, and the same effect can be obtained in either case. In this case,
In single power supply operation, the constant current source 100 is attached to the low potential power supply voltage terminal 6 side, so it cannot handle quiescent voltage, but since the range on the high potential voltage side is expanded, the input voltage range can be widened. This effect can be obtained. Further, the circuit shown in FIG. 7 has the same effects as those shown in FIGS. 4 and 6.
また、これまで述べてきた差動増幅回路は、
CMOSを用いてあるが、単チヤネルMOS、バイ
ポーラトランジスタ等を用いて構成してもよく、
同様の効果を得ることができる。 In addition, the differential amplifier circuit described so far is
Although CMOS is used, it may also be constructed using single channel MOS, bipolar transistors, etc.
A similar effect can be obtained.
以上本発明によれば、差動増幅対に使用する素
子のバラツキによるオフセツト電圧の発生を防止
できること、オフセツト調整として負荷素子に副
負荷素子を並列に設けたことにより負荷素子の分
担電圧の増加が無くなることから零入力電圧まで
扱え、広い入力電圧範囲の増幅動作が実現できる
という効果を奏する。
As described above, according to the present invention, it is possible to prevent the generation of offset voltage due to variations in the elements used in the differential amplifier pair, and by providing the sub-load element in parallel with the load element for offset adjustment, the shared voltage of the load element can be increased. Since the input voltage is zero, it is possible to handle up to 0 input voltage, and it is possible to realize amplification operation over a wide input voltage range.
第１図は従来のオフセツト調整付モノリシツク
差動増幅回路の回路図、第２図は本発明の差動増
幅回路の一実施例を示す回路図、第３図、第４
図、第６図、第７図はそれぞれ本発明の他の実施
例を示す第２図に相当する回路図、第５図は第２
図と第４図の場合のオフセツト調整端子から見た
電圧Vpffと出力端子に得られる電圧Vpとの関係の
比較を示す線図である。
１……反転入力端子、２……非反転入力端子、
３……出力端子、４ａ，４ｂ……オフセツト調整
端子、５……高電位電源電圧端子、６……低電位
電源電圧端子、１０，２０，３０，１００，２０
０……定電流源、１１，１２，２１，３１，１０
１，１０２，２０１……駆動MOS、１３ａ，１
４ａ，１０３，１０４……負荷MOS、１３ｂ，
１４ｂ，１０５，１０６……副負荷MOS、１４
ｃ……MOS、３２……コンデンサ。
FIG. 1 is a circuit diagram of a conventional monolithic differential amplifier circuit with offset adjustment, FIG. 2 is a circuit diagram showing an embodiment of the differential amplifier circuit of the present invention, and FIGS.
6, 7 are circuit diagrams corresponding to FIG. 2 showing other embodiments of the present invention, and FIG. 5 is a circuit diagram corresponding to FIG.
5 is a diagram showing a comparison of the relationship between the voltage V pff seen from the offset adjustment terminal and the voltage V p obtained at the output terminal in the cases of FIG. 4 and FIG. 1...Inverting input terminal, 2...Non-inverting input terminal,
3... Output terminal, 4a, 4b... Offset adjustment terminal, 5... High potential power supply voltage terminal, 6... Low potential power supply voltage terminal, 10, 20, 30, 100, 20
0... Constant current source, 11, 12, 21, 31, 10
1, 102, 201...Drive MOS, 13a, 1
4a, 103, 104...Load MOS, 13b,
14b, 105, 106...auxiliary load MOS, 14
c...MOS, 32...capacitor.
Claims (1)
対もつ差動増幅対を備えた差動増幅回路におい
て、 前記差動増幅対の少なくともどちらか一方の負
荷素子に副負荷素子を並列に接続し、 前記副負荷素子の制御電圧を可変として前記差
動増幅回路のオフセツト調整を行なうように構成
してある ことを特徴とする差動増幅回路。 ２ 特許請求範囲第１項において、前記オフセツ
ト調整を行なう前記副負荷素子の制御電圧は、前
記差動増幅回路の入力及び出力端子の電位に基づ
いて可変させるように構成したことを特徴とする
差動増幅回路。[Scope of Claims] 1. In a differential amplifier circuit including a differential amplifier pair having a pair of drive elements and load elements connected in series, at least one of the load elements of the differential amplifier pair is provided with an auxiliary load element. are connected in parallel, and the control voltage of the auxiliary load element is made variable to adjust the offset of the differential amplifier circuit. 2. The differential amplifier according to claim 1, wherein the control voltage of the auxiliary load element that performs the offset adjustment is configured to be varied based on the potentials of the input and output terminals of the differential amplifier circuit. dynamic amplification circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59142362A JPS6123403A (en) | 1984-07-11 | 1984-07-11 | Differential amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59142362A JPS6123403A (en) | 1984-07-11 | 1984-07-11 | Differential amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6123403A JPS6123403A (en) | 1986-01-31 |
| JPH051646B2 true JPH051646B2 (en) | 1993-01-08 |
Family
ID=15313614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59142362A Granted JPS6123403A (en) | 1984-07-11 | 1984-07-11 | Differential amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6123403A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6338314A (en) * | 1986-08-01 | 1988-02-18 | Nec Corp | Differential input circuit |
| JP2559032B2 (en) * | 1986-09-13 | 1996-11-27 | 富士通株式会社 | Differential amplifier circuit |
| JP4702921B2 (en) * | 2004-01-29 | 2011-06-15 | パナソニック株式会社 | Amplifier circuit for optical disk device |
| JP2005223627A (en) * | 2004-02-05 | 2005-08-18 | Asahi Kasei Microsystems Kk | Operational amplifier circuit |
| JP6520062B2 (en) | 2014-11-14 | 2019-05-29 | 富士電機株式会社 | Amplifier and offset voltage correction method |
| KR102560967B1 (en) * | 2023-03-27 | 2023-07-27 | 사공근 | Steam boiler system with an improved catch steam separate structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5097705A (en) * | 1974-01-09 | 1975-08-04 |
-
1984
- 1984-07-11 JP JP59142362A patent/JPS6123403A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5097705A (en) * | 1974-01-09 | 1975-08-04 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6123403A (en) | 1986-01-31 |
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