JPS63155735A - Wiring substrate for semiconductor device - Google Patents
Wiring substrate for semiconductor deviceInfo
- Publication number
- JPS63155735A JPS63155735A JP30332886A JP30332886A JPS63155735A JP S63155735 A JPS63155735 A JP S63155735A JP 30332886 A JP30332886 A JP 30332886A JP 30332886 A JP30332886 A JP 30332886A JP S63155735 A JPS63155735 A JP S63155735A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor
- wiring
- semiconductor device
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 239000000758 substrate Substances 0.000 title claims abstract description 17
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 235000019219 chocolate Nutrition 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は表面に配線層を形成しである半導体装置搭載用
基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a substrate for mounting a semiconductor device, which has a wiring layer formed on its surface.
工Ｃ＠の半導体素子はセラミック基板やリードフレーム
等の金属基板に塔載され、実装されて半導体装置が構成
される。即ち、第２図の従来の半導体装置の一例に示す
ように、金属の基板ｌの表面に絶縁層２を設け、絶縁層
２」―にＡ４等で配線３を形成し、この基板１の半導体
素子塔載部りに半導体素子５をグイボンディングし、半
導体素子５の電極と配線３とをＡ７！やＡｌ −Ｓｊ、
等のボンディングワイヤ７で結線しである。The semiconductor element of C@ is mounted on a metal substrate such as a ceramic substrate or a lead frame, and is mounted to form a semiconductor device. That is, as shown in an example of a conventional semiconductor device in FIG. The semiconductor element 5 is bonded to the element mounting part, and the electrode of the semiconductor element 5 and the wiring 3 are connected to A7! or Al-Sj,
The wires are connected using bonding wires 7 such as the above.
しかし、か＼る従来の半導体装置においては、ボンディ
ングワイヤ７が半導体素子５の周縁角部に接触しないよ
うに、半導体素子塔載部りと配線３の先端との間に四角
枠状にボンディング化ｌを設ける必要がある。又、１枚
のウエノ・−から各半導体素子５を切り出す際には、電
極６を有する表面側からレーザー等で形成したハーフエ
ッチに沿ってウェハーをチョコレートブレイクして分割
するので、半導体素子５の裏面側にバリ８が発生する。However, in such conventional semiconductor devices, in order to prevent the bonding wire 7 from coming into contact with the peripheral corner of the semiconductor element 5, bonding is performed in a rectangular frame shape between the semiconductor element mounting part and the tip of the wiring 3. It is necessary to provide l. Furthermore, when cutting out each semiconductor element 5 from a single wafer, the wafer is divided by chocolate breaking along the half-etch formed by a laser or the like from the surface side with the electrode 6, so that the semiconductor elements 5 are cut out. Burrs 8 are generated on the back side.
このバリ８を配線３に接触させなｌ／）Ａ４こも、半導
体素子塔載部りと配線３の先端との間に四角枠状のボン
ディング化ｔが必要となる。To prevent this burr 8 from coming into contact with the wiring 3, a rectangular frame-shaped bonding t is required between the semiconductor element mounting portion and the tip of the wiring 3.
この四角枠状のボンディング化ｔは半導体素子が大きく
なるほど必然的に大さくなり、通常の５〜６隨角の半導
体素子５でも一般に幅約０．４〜０．５酩程度が必要で
あった。四角枠状のボンディング化ｌは半導体装置の動
作に全く寄与しない無駄なスペースであり、半導体素子
の高密度な実装の妨げとなっていた。This rectangular frame-shaped bonding t inevitably becomes larger as the semiconductor element becomes larger, and a width of about 0.4 to 0.5 mm is generally required even for a normal 5 to 6 square semiconductor element 5. . The rectangular frame-shaped bonding l is wasted space that does not contribute at all to the operation of the semiconductor device, and has been an obstacle to high-density packaging of semiconductor elements.
本発明は、か＼る従来の事情に鑑み、無駄なポンディン
グ化を設けなくても半導体素子を搭載でき、従来よりも
高密度な実装を可能にする半導体素子用配線基板を提供
することを目的とする。In view of the conventional circumstances, it is an object of the present invention to provide a wiring board for semiconductor elements, which allows semiconductor elements to be mounted without unnecessary bonding and which enables higher-density mounting than before. purpose.
本発明の半導体素子用配線基板は、基板表面上に半導体
素子の塔載部にまで延在して形成した配線と、半導体素
子塔載部内の上記配線上であって半導体素子電極と対向
する位置に形成した電極接続用バンブとを具えたことを
特徴とする。The wiring board for a semiconductor element of the present invention has a wiring formed on the surface of the substrate extending to the mounting part of the semiconductor element, and a position on the wiring in the mounting part of the semiconductor element facing the semiconductor element electrode. It is characterized by comprising an electrode connection bump formed in the.
本発明においては、第１図に示すように、半導体素子５
はその電極６を半導体素子塔載部りで基板１の配線３と
対面させ、対向して当接した電極６と配線３上のバンプ
４とを熱圧着又は超音波溶着により直接固着させる。従
って、バンプの材質としては、熱圧着又は超音波溶着が
容易なアルミニウム、金または銅、若しくはこれらの少
なくとも一種を含む合金が好ましい。In the present invention, as shown in FIG.
The electrode 6 is made to face the wiring 3 of the substrate 1 on the semiconductor element mounting part, and the electrode 6 and the bump 4 on the wiring 3, which are facing and in contact with each other, are directly fixed by thermocompression bonding or ultrasonic welding. Therefore, the material of the bump is preferably aluminum, gold, copper, or an alloy containing at least one of these, which can be easily thermocompressed or ultrasonic welded.
また、バンプ４の高さは熱圧着又は超音波溶着が可能で
あれば出来るだけ薄い方が好ましく、特に１０〜１．０
０μｍの範囲の高さが半導体装置の薄型化のために好ま
しい。Further, the height of the bump 4 is preferably as thin as possible if thermocompression bonding or ultrasonic welding is possible, especially 10 to 1.0
A height in the range of 0 μm is preferable for making the semiconductor device thinner.
更に、バンプ４を半導体素子５側に形成することも考え
られるが、その場合は半導体素子の大幅なコストアップ
を招くだけでなく、工程の付加により半導体素子の信頼
性を低下させることにもなるので好ましくない。Furthermore, it is possible to form the bumps 4 on the side of the semiconductor element 5, but in that case, not only will the cost of the semiconductor element increase significantly, but also the reliability of the semiconductor element will be reduced due to the additional process. So I don't like it.
本発明によれば、第１図に示すように基板１の半導体素
子塔載部り内で配線３上に設けたバンプ４に直接半導体
素子５の電極６を接続するので、従来の如く最シデイン
グワイヤを使用せず、従ってボンディングワイヤと半導
体素子５の周縁角部との接触は起こり得ない。又、本発
明の配線基板では、第１図の如く半導体素子５を従来と
は上下逆にするギヤング・ボンドにより塔載するので、
ウェハーから切り出す際に半導体素子５の裏面側に発生
するバリ８が基板１の配線３と接触することもない。According to the present invention, as shown in FIG. 1, the electrodes 6 of the semiconductor element 5 are directly connected to the bumps 4 provided on the wiring 3 within the semiconductor element mounting portion of the substrate 1. No bonding wire is used, so contact between the bonding wire and the peripheral corner of the semiconductor element 5 cannot occur. In addition, in the wiring board of the present invention, as shown in FIG. 1, the semiconductor element 5 is mounted using a gigantic bond that is upside down compared to the conventional method.
The burrs 8 generated on the back side of the semiconductor element 5 when cut out from the wafer do not come into contact with the wiring 3 of the substrate 1.
従って、本発明の配線基板ではボンディング化のような
無駄なスペースを設ける必要がなく、実装面積をその分
だけ小さくすることができる。Therefore, in the wiring board of the present invention, there is no need to provide wasted space such as bonding, and the mounting area can be reduced accordingly.
また、本発明の配線基板を配線密度の高い薄膜配線基板
に適用すれば、より一層の高密度実装ないし半導体装置
の薄型化に有効である。Further, if the wiring board of the present invention is applied to a thin film wiring board with high wiring density, it is effective for achieving even higher density packaging and making semiconductor devices thinner.
第１図に示す金属基板１の表面上に半導体素子塔載部り
まで延在したＡｔ配線３を形成し、半導体素子塔載部り
内の配線３上にＡ４のバンプ４を形成した。このバンプ
４に６朋角で厚さＱ、５ｍｓの半導体素子５の電極６を
熱圧着により直接接続して第１図の半導体装置を構成し
た。On the surface of the metal substrate 1 shown in FIG. 1, an At wiring 3 extending up to the semiconductor element mounting area was formed, and an A4 bump 4 was formed on the wiring 3 within the semiconductor element mounting area. An electrode 6 of a semiconductor element 5 having a diameter of 6 mm and a thickness of Q and 5 ms was directly connected to the bump 4 by thermocompression bonding to form the semiconductor device shown in FIG.
一方、上記と同じ寸法の半導体素子５を用いて従来の如
くワイヤボンディングにより第２図の半導体装置を構成
するためには、幅０．４間の四角枠状のボンディング化
！が必要であった。On the other hand, in order to construct the semiconductor device shown in FIG. 2 by conventional wire bonding using the semiconductor element 5 having the same dimensions as above, bonding must be performed in the form of a rectangular frame with a width of 0.4! was necessary.
従って、従来の配線基板では必要な実装面積が４６．２
４ｍｍ を占めるのに対して、本発明の配線基板では実
装面積は３５ｍｍであり、従来よりも実装密度を約２２
．１５％向上させることができた。Therefore, the required mounting area for the conventional wiring board is 46.2
4mm, whereas the wiring board of the present invention has a mounting area of 35mm, making the mounting density approximately 22mm higher than that of the conventional wiring board.
．． We were able to improve this by 15%.
尚、以上の説明ではリードフレームのよウナ金属基板を
用いる例を示したが、本発明はビングリッドアレイ等の
従来ワイヤボンディングにより結線していた半導体装置
に使用する配線基板の全てに適用できるものである。In the above explanation, an example is shown in which a metal substrate such as a lead frame is used, but the present invention can be applied to all wiring substrates used in semiconductor devices such as bin grid arrays, which are conventionally connected by wire bonding. It is.
本発明の半導体装置用配線基板によれば、無駄なボンデ
ィング化を設けなくても半導体素子を搭載でさ、従来よ
りも高密度な実装が可能である。According to the wiring board for a semiconductor device of the present invention, semiconductor elements can be mounted without unnecessary bonding, and higher-density packaging than before is possible.
第１図は本発明の配線基板を用いた半導体装置の断面図
であり、第２図は従来の配線基板を用いてワイヤボンデ
ィングした半導体装置の断面図である。
１・・基板 ３・・配線 ４・・バンブ５・・半導体素
子 ６・・電極
７・・ボンディングワイヤ
第１区
策２図FIG. 1 is a cross-sectional view of a semiconductor device using the wiring board of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device wire-bonded using a conventional wiring board. 1. Substrate 3. Wiring 4. Bump 5. Semiconductor element 6. Electrode 7. Bonding wire 1st section plan 2 diagram
Claims (3)
形成した配線と、半導体素子塔載部内の上記配線上であ
つて半導体素子電極と対向する位置に形成した電極接続
用バンプとを具えたことを特徴とする半導体装置用配線
基板。(1) Wiring formed on the substrate surface extending to the mounting part of the semiconductor element, and electrode connection bumps formed on the wiring in the semiconductor element mounting part at a position facing the semiconductor element electrode. A wiring board for a semiconductor device, comprising:
はこれらの少なくとも一種を含む合金からなることを特
徴とする、特許請求の範囲（１）項に記載の半導体装置
用配線基板。(2) The wiring board for a semiconductor device according to claim (1), wherein the bumps are made of aluminum, gold, copper, or an alloy containing at least one of these.
ことを特徴とする、特許請求の範囲（１）項又は（２）
項に記載の半導体装置用配線基板。(3) Claim (1) or (2) characterized in that the height of the bump is 10 μm to 100 μm.
The wiring board for a semiconductor device as described in 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30332886A JPS63155735A (en) | 1986-12-19 | 1986-12-19 | Wiring substrate for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30332886A JPS63155735A (en) | 1986-12-19 | 1986-12-19 | Wiring substrate for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63155735A true JPS63155735A (en) | 1988-06-28 |
Family
ID=17919651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30332886A Pending JPS63155735A (en) | 1986-12-19 | 1986-12-19 | Wiring substrate for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63155735A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7930086B2 (en) | 2004-01-30 | 2011-04-19 | Toyota Jidosha Kabushiki Kaisha | Shifting apparatus and shifting control method thereof |
-
1986
- 1986-12-19 JP JP30332886A patent/JPS63155735A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7930086B2 (en) | 2004-01-30 | 2011-04-19 | Toyota Jidosha Kabushiki Kaisha | Shifting apparatus and shifting control method thereof |
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