JPH0621304A - Manufacture of lead frame and semiconductor device - Google Patents

Manufacture of lead frame and semiconductor device

Info

Publication number
JPH0621304A
JPH0621304A JP17788592A JP17788592A JPH0621304A JP H0621304 A JPH0621304 A JP H0621304A JP 17788592 A JP17788592 A JP 17788592A JP 17788592 A JP17788592 A JP 17788592A JP H0621304 A JPH0621304 A JP H0621304A
Authority
JP
Japan
Prior art keywords
inner lead
lead
wire
resin
die pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17788592A
Other languages
Japanese (ja)
Inventor
Hirohisa Nakayama
浩久 中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP17788592A priority Critical patent/JPH0621304A/en
Publication of JPH0621304A publication Critical patent/JPH0621304A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To heighten close adhesiveness between an inner lead and resin while preventing generation of defectives such as a movement of a lead and a break of a wire by providing the half-etching part near a wire stitch bond of an inner lead. CONSTITUTION:A lead frame is constituted of an almost square die pad 1 loading an integrated circuit chip 5 and an inner lead 3 arranged in the periphery of said die pad 1 while having its one end facing the die pad 1. Until now, the vicinity of a wire stitch bond of the inner lead 3 was flat and tight adhesion between the inner lead 3 and resin was bad. However, tight adhesion between the inner lead 3 and resin can be heightened by providing a half-etching part 2 near the stitch bond so as to seal the inner lead 3 with resin and simultaneously therewith a movement of the lead 3 and a break of a wire ca be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は樹脂封止型の半導体装置
の外部リード付け組立に使用されるリードフレーム、特
にリードフレームのハーフエッチングの形状に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame used for external lead assembly of a resin-sealed semiconductor device, and more particularly to a half-etched shape of the lead frame.

【０００２】[0002]

【従来の技術】従来のリードフレームを用いた半導体装
置は図４に示すように導電性ワイヤ６によりリードフレ
ームのインナーリード３のワイヤステッチボンド（内部
リード端子においてのセカンドボンディング点）と集積
回路チップ５のパッド部とを接続するワイヤボンディン
グ工程は半導体装置の組立工程の１つである。リードフ
レームのインナーリード３の表面粗さは部材である４２
ＡｌｌｏｙやＣｕの素材としての表面粗さのままであっ
た。2. Description of the Related Art As shown in FIG. 4, a conventional semiconductor device using a lead frame has a wire stitch bond (second bonding point at an internal lead terminal) of an inner lead 3 of the lead frame and an integrated circuit chip by a conductive wire 6. The wire bonding process for connecting to the pad portion 5 is one of the semiconductor device assembling processes. The surface roughness of the inner lead 3 of the lead frame is a member 42
The surface roughness as a material of Alloy and Cu remained as it was.

【０００３】[0003]

【発明が解決しようとする課題】しかし、前述の従来の
技術を用いた方法では、図４に示すようにリードフレー
ムのインナーリード３部平面が平坦であるためにインナ
ーリード３を樹脂で封止したとき、インナーリード３と
樹脂との密着性が悪くなりパッケージのハンダ時にパッ
ケージクラックが発生した。そのため樹脂が図４に示し
たように矢印７の方向に熱収縮されたとき、インナーリ
ード３は相対方向（矢印８の）に動き、インナーリード
３が移動したり、インナーリード３先端にボンディング
されたワイヤ６が切れるなどという問題が生じた。した
がって以上の課題を克服するためのリードフレームを提
供するところにある。However, in the method using the above-described conventional technique, the inner lead 3 is sealed with resin because the plane of the inner lead 3 portion of the lead frame is flat as shown in FIG. At that time, the adhesion between the inner lead 3 and the resin was deteriorated, and a package crack was generated when the package was soldered. Therefore, when the resin is thermally shrunk in the direction of arrow 7 as shown in FIG. 4, the inner lead 3 moves in the relative direction (in the direction of arrow 8), and the inner lead 3 moves or is bonded to the tip of the inner lead 3. There was a problem that the wire 6 was broken. Therefore, it is intended to provide a lead frame for overcoming the above problems.

【０００４】[0004]

【課題を解決するための手段】本発明のリードフレーム
は、集積回路チップを搭載する略四角形のダイパッドの
集縁に配置され、一端をダイパッドに向けたインナーリ
ードによって構成されるリードフレームにおいて、前記
インナーリードステッチボンド近傍にハーフエッチング
を設けることを特徴とする。A lead frame according to the present invention is a lead frame which is arranged at a gathering edge of a substantially square die pad on which an integrated circuit chip is mounted and which is constituted by an inner lead whose one end faces the die pad. It is characterized in that half etching is provided near the inner lead stitch bond.

【０００５】[0005]

【実施例】以下、本発明の実施例を図１により説明す
る。図１は、本発明の実施例を示すダイパッド部およ
び、インナーリード先端部の断面図である。集積回路チ
ップ５を搭載するための略四角形のダイパッド１は、そ
の四隅においてダイパッド吊りリードによって支持され
ている。インナーリード３は集積回路チップ５上のパッ
ドとインナーリード３先端をワイヤ６でボンディングす
ることによってチップ５への信号の入出力を行なってい
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a sectional view of a die pad portion and an inner lead tip portion showing an embodiment of the present invention. The substantially square die pad 1 for mounting the integrated circuit chip 5 is supported by the die pad suspension leads at its four corners. The inner lead 3 inputs and outputs a signal to the chip 5 by bonding a pad on the integrated circuit chip 5 and the tip of the inner lead 3 with a wire 6.

【０００６】インナーリード３のワイヤステッチボンド
近傍には横に細長いハーフエッチング部２が設けられて
いる。An elongated half-etched portion 2 is provided laterally in the vicinity of the wire stitch bond of the inner lead 3.

【０００７】図２もまた本発明の他の実施例を示す平面
図である。FIG. 2 is also a plan view showing another embodiment of the present invention.

【０００８】図２にあるのはインナーリード３のワイヤ
ステッチボンド近傍に設けられた、縦に細長いハーフエ
ッチング部４である。FIG. 2 shows a vertically elongated half-etched portion 4 provided near the wire stitch bond of the inner lead 3.

【０００９】本発明ではハーフエッチングは同形状のも
のと、インナーリード先端からの距離も等しいもので説
明したがこれは異形状でインナーリード先端からの距離
も異なっていても良い。In the present invention, half etching has been described as having the same shape and the same distance from the tip of the inner lead, but this may have different shapes and different distances from the tip of the inner lead.

【００１０】前記に示した、図１、図２にあるハーフエ
ッチング部２、４はリードフレームの表面に設けたもの
を示した図である。The half-etched portions 2 and 4 shown in FIGS. 1 and 2 shown above are provided on the surface of the lead frame.

【００１１】図３は本発明の他の実施例を示すダイパッ
ド部およびインナーリード先端部の断面図である。FIG. 3 is a cross-sectional view of a die pad portion and an inner lead tip portion showing another embodiment of the present invention.

【００１２】図３（ａ）はインナーリード３のワイヤス
テッチボンド近傍の裏面にハーフエッチング部９を設け
たものである。FIG. 3A shows a half-etched portion 9 provided on the back surface of the inner lead 3 near the wire stitch bond.

【００１３】図３（ｂ）はインナーリード３のワイヤス
テッチボンド近傍の両面にハーフエッチング部１０を設
けたものである。FIG. 3B shows the half-etched portions 10 provided on both surfaces of the inner lead 3 in the vicinity of the wire stitch bond.

【００１４】図３（ｃ）はインナーリード３のワイヤス
テッチボンド近傍の表面、もしくは裏面、あるいは両面
に複数のハーフエッチング部１１を設けたものである。FIG. 3C shows the inner lead 3 provided with a plurality of half-etched portions 11 on the front surface, the back surface, or both surfaces in the vicinity of the wire stitch bond.

【００１５】今まで、インナーリードのワイヤステッチ
ボンド近傍が平坦であるためにインナーリードと樹脂と
の密着性が悪くなっていた。しかし本発明は、前記に示
したハーフエッチング部を設けることによりインナーリ
ードを樹脂で封止した時インナーリードと樹脂との密着
性を高めることができた。Up to now, since the vicinity of the wire stitch bond of the inner lead is flat, the adhesion between the inner lead and the resin has deteriorated. However, in the present invention, by providing the half-etched portion shown above, the adhesion between the inner lead and the resin can be improved when the inner lead is sealed with the resin.

【００１６】[0016]

【発明の効果】以上述べたように、本発明において、イ
ンナーリードのワイヤステッチボンド近傍にハーフエッ
チング部を設けることによりインナーリードと樹脂との
密着性を高めることができ、それと同時に、リードの移
動、ワイヤ切れといった不良発生を防止するという優れ
た効果を有する。As described above, in the present invention, by providing the half-etched portion in the vicinity of the wire stitch bond of the inner lead, the adhesion between the inner lead and the resin can be enhanced, and at the same time, the movement of the lead is moved. It has an excellent effect of preventing the occurrence of defects such as wire breakage.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を示す断面図。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図２】本発明の他の実施例を示す平面図。FIG. 2 is a plan view showing another embodiment of the present invention.

【図３】（ａ）本発明の他の実施例を示す断面図。 （ｂ）本発明の他の実施例を示す断面図。 （ｃ）本発明の他の実施例を示す断面図。FIG. 3A is a sectional view showing another embodiment of the present invention. (B) A sectional view showing another embodiment of the present invention. (C) A sectional view showing another embodiment of the present invention.

【図４】従来の技術を示す断面図。FIG. 4 is a sectional view showing a conventional technique.

【符号の説明】[Explanation of symbols]

１ ・・・ダイパッド部 ２、４・・・ハーフエッチング部 ３ ・・・インナーリード先端部 ５ ・・・集積回路チップ ６ ・・・ワイヤ ７ ・・・インナーリードの収縮方向 ８ ・・・樹脂の収縮方向 ９ ・・・ハーフエッチング部 １０ ・・・ハーフエッチング部 １１ ・・・ハーフエッチング部 1 ・ ・ ・ Die pad part 2, 4 ・ ・ ・ Half etching part 3 ・ ・ ・ Inner lead tip part 5 ・ ・ ・ Integrated circuit chip 6 ・ ・ ・ Wire 7 ・ ・ ・ Inner lead contraction direction 8 ・ ・ ・ Resin Shrinkage direction 9 ・ ・ ・ Half etching part 10 ・ ・ ・ Half etching part 11 ・ ・ ・ Half etching part

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 集積回路チップを搭載する略四角形のダ
イパッドと、前記ダイパッドの集縁に配置され、一端を
ダイパッドに向けたインナーリードによって構成される
リードフレームにおいて、前記インナーリードのステッ
チボンド近傍にハーフエッチングを設けたことを特徴と
するリードフレーム。1. A lead frame constituted by a substantially rectangular die pad on which an integrated circuit chip is mounted and an inner lead disposed at a gathering edge of the die pad and having one end facing the die pad, in the vicinity of a stitch bond of the inner lead. Lead frame characterized by half etching. 【請求項２】 請求項１記載のリードフレームを用いた
ことを特徴とする半導体装置の製造方法。2. A method of manufacturing a semiconductor device, wherein the lead frame according to claim 1 is used.
JP17788592A 1992-07-06 1992-07-06 Manufacture of lead frame and semiconductor device Pending JPH0621304A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17788592A JPH0621304A (en) 1992-07-06 1992-07-06 Manufacture of lead frame and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17788592A JPH0621304A (en) 1992-07-06 1992-07-06 Manufacture of lead frame and semiconductor device

Publications (1)

Publication Number Publication Date
JPH0621304A true JPH0621304A (en) 1994-01-28

Family

ID=16038763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17788592A Pending JPH0621304A (en) 1992-07-06 1992-07-06 Manufacture of lead frame and semiconductor device

Country Status (1)

Country Link
JP (1) JPH0621304A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5955778A (en) * 1996-10-08 1999-09-21 Nec Corporation Lead frame with notched lead ends
US6861735B2 (en) 1997-06-27 2005-03-01 Matsushita Electric Industrial Co., Ltd. Resin molded type semiconductor device and a method of manufacturing the same
US6900524B1 (en) 1997-06-27 2005-05-31 Matsushita Electric Industrial Co., Ltd. Resin molded semiconductor device on a lead frame and method of manufacturing the same
JP2013016819A (en) * 2004-12-16 2013-01-24 Avago Technologies Ecbu Ip (Singapore) Pte Ltd Packaged electronic device and manufacturing method of the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5955778A (en) * 1996-10-08 1999-09-21 Nec Corporation Lead frame with notched lead ends
US6861735B2 (en) 1997-06-27 2005-03-01 Matsushita Electric Industrial Co., Ltd. Resin molded type semiconductor device and a method of manufacturing the same
US6900524B1 (en) 1997-06-27 2005-05-31 Matsushita Electric Industrial Co., Ltd. Resin molded semiconductor device on a lead frame and method of manufacturing the same
US7538416B2 (en) 1997-06-27 2009-05-26 Panasonic Corporation Resin molded type semiconductor device and a method of manufacturing the same
JP2013016819A (en) * 2004-12-16 2013-01-24 Avago Technologies Ecbu Ip (Singapore) Pte Ltd Packaged electronic device and manufacturing method of the same

Similar Documents

Publication Publication Date Title
JPH08222681A (en) Resin sealed semiconductor device
US6396129B1 (en) Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package
JP2001015668A (en) Resin-sealed semiconductor package
EP0710982A2 (en) Personalized area leadframe coining or half etching for reduced mechanical stress at device edge
JPH0621304A (en) Manufacture of lead frame and semiconductor device
JP2002359338A (en) Lead frame, and semiconductor device using it, and its manufacturing method
KR100373891B1 (en) Semiconductor device and method of its fabrication
JPH0621305A (en) Semiconductor device
JP2001177007A (en) Semiconductor device and manufacturing method thereof
JP2589520B2 (en) Method for manufacturing resin-encapsulated semiconductor device
JP2795069B2 (en) Semiconductor device
JPH02278857A (en) Resin-sealed type semiconductor device
JPS61241954A (en) Semiconductor device
JP3192238B2 (en) Method of assembling semiconductor device
JPH0366150A (en) Semiconductor integrated circuit device
JPH11330343A (en) Resin-sealed semiconductor device
JPH05211250A (en) Resin-sealed type semiconductor device
KR100244254B1 (en) Lead frame and semiconductor package with such lead frame
JPH04267545A (en) Plastic molded type semiconductor device
JPS60136344A (en) Semiconductor device
KR100460072B1 (en) Semiconductor Package
KR200331874Y1 (en) Multi-pin Package of Semiconductor
JPH1126643A (en) Semiconductor device
JPH0498861A (en) Resin sealed type semiconductor device
JPH05291345A (en) Semiconductor device