JPS63141346A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63141346A JPS63141346A JP28673786A JP28673786A JPS63141346A JP S63141346 A JPS63141346 A JP S63141346A JP 28673786 A JP28673786 A JP 28673786A JP 28673786 A JP28673786 A JP 28673786A JP S63141346 A JPS63141346 A JP S63141346A
- Authority
- JP
- Japan
- Prior art keywords
- oxidation
- resistant film
- film
- grooves
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 230000003647 oxidation Effects 0.000 claims abstract description 50
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 12
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 241000293849 Cordylanthus Species 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000005468 ion implantation Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009271 trench method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に素子分離
領域を有する半導体装置における、該素子分離領域の形
成方法の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming an isolation region in a semiconductor device having an isolation region.
本発明は、素子分離領域を有する半導体装置の製造方法
において、半導体基板上に第１の耐酸化膜を選択的に形
成し、これをマスクにして選択的に半導体基板をエツチ
ングして溝を形成した後、該溝内と第１の耐酸化膜上を
第２の耐酸化膜で覆い、該第２の耐酸化膜を異方性エツ
チングして溝側壁部に残し、少なくとも溝内に半導体層
を形成してこれを酸化した後、第１の耐酸化膜を除去し
て平坦化することにより、基板表面と素子分離領域表面
との段差が小さく、かつ寸法変換差の少ない素子分離領
域を形成することができるようにしたものである。The present invention is a method for manufacturing a semiconductor device having an element isolation region, in which a first oxidation-resistant film is selectively formed on a semiconductor substrate, and the semiconductor substrate is selectively etched using this as a mask to form a groove. After that, the inside of the trench and the top of the first oxidation-resistant film are covered with a second oxidation-resistant film, and the second oxidation-resistant film is anisotropically etched to remain on the sidewalls of the trench, and at least a semiconductor layer is formed in the trench. After forming and oxidizing this, the first oxidation-resistant film is removed and planarized to form an element isolation region with a small step difference between the substrate surface and the element isolation region surface and a small dimensional conversion difference. It was made so that it could be done.
従来の半導体装置の製造方法、なかでも素子分Ｍ ｆｉ
ｉ域の形成方法として、種々の方法が提案されており、
例えばＬＯＣＯＳ法、変形ＬＯＣＯＳ法、Ｐ、Ｐ、Ｌ（
Ｐｏｌｙ Ｐａｄ ＬＯＣＯＳ）法、Ｓｔをエツチング
するトレンチ法、ボックス法、ＳＷＡＭ方法などが行わ
れている。Conventional semiconductor device manufacturing methods, especially element component M fi
Various methods have been proposed as methods for forming the i-region.
For example, LOCOS method, modified LOCOS method, P, P, L (
The methods used include the Poly Pad LOCOS method, the trench method for etching St, the box method, and the SWAM method.
上記した通常のＬＯＣＯＳ法による場合、素子分離領域
とする熱酸化膜が成長して両端が鳥のくちばし状に基板
に食い込む、いわゆるバーズビーブが生じて寸法変換差
が太き（なり（酸化膜の厚さとバーズビーブの長さが略
同じ）、１μ以下のデザインルールによる超ＬＳＩの場
合には適用できないという問題点がある。変形ＬＯＣＯ
Ｓ法、Ｐ、Ｐ、Ｌ （ＰｏｌｙＰａｄ ＬＯＣＯＳ）法
ではシリコン基板表面と素子分離領域表面との間に段差
ができるため、その上に微細配線加工を行うことが難し
いという問題点がある。When using the above-mentioned normal LOCOS method, the thermal oxide film used as the element isolation region grows and both ends dig into the substrate in the shape of a bird's beak, creating a so-called bird's beak, resulting in a large dimensional conversion difference (the thickness of the oxide film). The problem is that it cannot be applied to a VLSI with a design rule of 1μ or less.Modified LOCO
In the S method and the P, P, L (PolyPad LOCOS) method, a step is formed between the surface of the silicon substrate and the surface of the element isolation region, so there is a problem in that it is difficult to process fine wiring thereon.
また上述したトレンチ法、ボックス法、ＳＷＡＭ法など
によれば、工程が複雑になり、Ｓｉと分＃領域とのエツ
ジでは結晶欠陥が発生してリーク電流が発生し易くなる
という問題点もある。Further, according to the above-mentioned trench method, box method, SWAM method, etc., the process becomes complicated, and there are also problems in that crystal defects are generated at the edges of Si and the minute regions, and leakage current is likely to occur.
そこで本発明の目的は、上記問題点を解決することので
きる半導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above problems.
上記問題点を解決するため、本発明は以下の方法をとる
。すなわち本発明においては、第１図（ａ）〜（ｈｌに
例示する如く、素子分離領域６を有する半導体装置の製
造方法において、半導体基板１上に選択的に第１の耐酸
化膜２を形成する工程と、該第１の耐酸化膜２をマスク
にして選択的に上記半導体基板１をエツチングして溝３
を形成する工程と、該溝３内と上記第１の耐酸化膜２上
を覆って第２の耐酸化膜４を形成する工程と、該第２の
耐酸化Ｍ４を異方性エツチングし、上記溝３側壁部に第
２の耐酸化膜４を残す工程と、少なくとも上記：＄３内
に半導体層５を形成する工程と、該半導体層５を酸化す
る工程と、上記第１の耐酸化膜２を除去して平坦化する
工程とを備えるようにし、かつ上記第１の耐酸化膜２除
去部に半導体素子を形成する方法をとる。In order to solve the above problems, the present invention takes the following method. That is, in the present invention, as illustrated in FIGS. 1A to 1H, in a method for manufacturing a semiconductor device having an element isolation region 6, a first oxidation-resistant film 2 is selectively formed on a semiconductor substrate 1. and selectively etching the semiconductor substrate 1 using the first oxidation-resistant film 2 as a mask to form grooves 3.
a step of forming a second oxidation-resistant film 4 covering the inside of the groove 3 and the first oxidation-resistant film 2; and anisotropic etching of the second oxidation-resistant film M4. a step of leaving a second oxidation-resistant film 4 on the side wall of the trench 3; a step of forming a semiconductor layer 5 within at least the above $3; a step of oxidizing the semiconductor layer 5; and a step of oxidizing the semiconductor layer 5; This method includes a step of removing and planarizing the film 2, and forms a semiconductor element in the portion where the first oxidation-resistant film 2 is removed.
以下、本発明の半導体装置の製造方法をさらに詳しく説
明する。Hereinafter, the method for manufacturing a semiconductor device of the present invention will be explained in more detail.
上記の第１の耐酸化膜２及び第２の耐酸化膜４の形成に
おいては、酸化膜として例えばＳｉ＋Ｎａなどを好まし
く用いることができ、これは例えばＣＶＤを使って形成
することができる。In forming the first oxidation-resistant film 2 and the second oxidation-resistant film 4, for example, Si+Na can be preferably used as the oxide film, and this can be formed using, for example, CVD.
上記の異方性エツチングによって溝３側壁部に第２の耐
酸化膜４を残す工程は、平坦な部分と段差部の膜厚の差
を利用して段差部にエツチング残りを生じさせる、いわ
ゆるサイドウオール技法を使って行うことができる。The process of leaving the second oxidation-resistant film 4 on the side walls of the groove 3 by the above-mentioned anisotropic etching is a so-called side etching process in which an etching residue is left on the step part by utilizing the difference in film thickness between the flat part and the step part. This can be done using the wall technique.
上記の半導体層５は、半導体基板ｌと同一の材料を主成
分とするものが好ましく、例えば半導体基板ｌにシリコ
ンを使った場合、半導体層５にはポリシリコンなどが好
ましく使える。そして半導体層５の形成は、）ｌｃｆｆ
＋ ＳｉＨ４系のガスを使用して６００〜９００℃の
低温で選択的にシリコン（Ｓｉ）を気相成長させること
により行うことができる。The semiconductor layer 5 described above preferably has the same material as the semiconductor substrate 1 as its main component. For example, if silicon is used for the semiconductor substrate 1, polysilicon or the like can preferably be used for the semiconductor layer 5. The formation of the semiconductor layer 5 is as follows: )lcff
+ This can be carried out by selectively growing silicon (Si) in a vapor phase using a SiH4-based gas at a low temperature of 600 to 900°C.
なお本明細書中における寸法変換差とは、形成したい領
域の寸法と実際に形成される領域の寸法との偏差をいう
。Note that the dimension conversion difference in this specification refers to the deviation between the dimension of the region to be formed and the dimension of the region to be actually formed.
上記したように、本発明は選択的に形成した第１の耐酸
化膜２をマスクとして溝３を選択的に形成し、該溝３内
に第２の耐酸化膜４を形成してこれを異方性エツチング
し、溝３の側壁部に第２の耐酸化膜４を残した後、溝３
内に形成した半導体層５を酸化して素子分１ｆｔＭ 領
域６とするため、素子分離領域６の両端の耐酸化膜４が
半導体層５の酸化時のマスクの役割をはたし、所望の素
子分離領域の寸法との変換差を小さくできる。As described above, the present invention involves selectively forming the grooves 3 using the selectively formed first oxidation-resistant film 2 as a mask, and forming the second oxidation-resistant film 4 in the grooves 3. After performing anisotropic etching and leaving the second oxidation-resistant film 4 on the sidewalls of the trench 3,
Since the semiconductor layer 5 formed in the semiconductor layer 5 is oxidized to form a 1 ftM region 6 for the device, the oxidation-resistant film 4 at both ends of the device isolation region 6 serves as a mask when the semiconductor layer 5 is oxidized, and the desired device is formed. The conversion difference with the dimensions of the separation region can be reduced.
そして最後に、表面に残った第１の耐酸化膜２を除去し
て平坦化することにより、該除去部分にさらに半導体素
子を形成することが可能になる。Finally, by removing and planarizing the first oxidation-resistant film 2 remaining on the surface, it becomes possible to further form a semiconductor element in the removed portion.
以下、本発明の半導体装置の製造方法を第１図を参照し
ながら詳細に説明する。なお当然のことであるが、以下
の実施例は本発明の一例を示すもので、本発明はこの例
にのみ限定されない。Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be explained in detail with reference to FIG. It should be noted that, as a matter of course, the following example shows an example of the present invention, and the present invention is not limited only to this example.
第１図（ａｌ〜（ｈ）は本実施例の工程を示す断面図で
ある。FIGS. 1A to 1H are cross-sectional views showing the steps of this embodiment.
本実施例は、Ｐ型のシリコン基板に素子分離領域を形成
する場合に、本発明を適用したものである。In this embodiment, the present invention is applied when forming an element isolation region on a P-type silicon substrate.
第１図（ａ）に示す如く、Ｐ型シリコン半導体基板（以
下適宜シリコン基板とも称する）１の表面を熱酸化して
、厚さ約３００人の酸化膜７を形成する。As shown in FIG. 1(a), the surface of a P-type silicon semiconductor substrate (hereinafter also referred to as a silicon substrate) 1 is thermally oxidized to form an oxide film 7 having a thickness of approximately 300 nm.
この酸化膜７は、通常のＬＯＣＯＳ法と比べてエツジ部
分のストレスが小さいので薄くてよい。酸化膜７上にＣ
ＶＤ （化学気相成長）法を使って５ｉＪ４を厚さ約５
００人堆積させて第１の耐酸化膜２を形成する。次いで
第１の耐酸化膜２上に形成すべきし、第１図（ａ）の状
態とする。This oxide film 7 may be thin because the stress at the edge portion is smaller than that in the normal LOCOS method. C on the oxide film 7
Using VD (chemical vapor deposition) method, 5iJ4 was deposited to a thickness of approximately 5
The first oxidation-resistant film 2 is formed by depositing 0.000 people. Next, it should be formed on the first oxidation-resistant film 2, resulting in the state shown in FIG. 1(a).
次いで第１図（ｂ）のように第１の耐酸化膜２と酸化膜
７を除去して、窓開けする。Next, as shown in FIG. 1(b), the first oxidation-resistant film 2 and the oxide film 7 are removed to form a window.
次に第１図（Ｃ）に示す如く、シリコン基板１を第１の
耐酸化膜２をマスクとしてＲＩＥにより約０．４μエツ
チングして溝３を形成後、さらに第１の耐酸化膜２をマ
スクとしてシリコン基板１と同じ導電型の例えばボロン
（Ｂつをシリコン基板１にイオン注入することによりチ
ャンネルストップ領域８を形成する。この際のイオン注
入は、通常のＬＯＣＯＳ法と比べて低エネルギーかつ低
ドース量で良い。Next, as shown in FIG. 1(C), the silicon substrate 1 is etched by about 0.4μ by RIE using the first oxidation-resistant film 2 as a mask to form a groove 3, and then the first oxidation-resistant film 2 is etched. The channel stop region 8 is formed by implanting ions of the same conductivity type as the silicon substrate 1, such as boron (B), into the silicon substrate 1 as a mask.The ion implantation at this time uses lower energy and Good in low doses.
次に第１図（ｄ）に示す露出したシリコン基板１の部分
を熱酸化して、約３００人のＳｉｎｇ膜１０膜形０する
。Next, the exposed portion of the silicon substrate 1 shown in FIG. 1(d) is thermally oxidized to form about 300 Sing films.
第１図（ｅ）に示す如く、溝３内と第１の耐酸化膜２上
をＳｉ３Ｎ４を使ってＣＶＤにより第２の耐酸化膜４を
形成し、ｌ？ＩＥなどで第２の耐酸化膜４を異方性エツ
チングする。As shown in FIG. 1(e), a second oxidation resistant film 4 is formed inside the trench 3 and on the first oxidation resistant film 2 by CVD using Si3N4, The second oxidation-resistant film 4 is anisotropically etched using IE or the like.
これにより、第１図（ｆ）に示す如く、エツチングされ
る方向にＳｉ３Ｎ４が厚く付いている溝３の側壁部に第
２の耐酸化膜４が残る（いわゆるサイドウオール技法）
。As a result, as shown in FIG. 1(f), a second oxidation-resistant film 4 remains on the side wall of the groove 3 where Si3N4 is thickly deposited in the direction of etching (so-called sidewall technique).
.
次に第１図（幻に示す如（、ＨＣｊｉ ＋ＳｉＨ４系の
混合ガスを使用して６００〜９００℃の低温でＳｉを気
相成長させることにより、露出した溝３内に選択的に厚
さ約１５００人の半導体Ｎ５を形成する。この半導体層
５のＳｉは、単結晶であることが好ましいが、多結晶ま
たは非晶質であっても良い。上記半導体層５ （Ｓｔ）
を水蒸気雰囲気中などで約６０００人（矢印の方向に点
線あたりまで成長）の熱酸化膜成長を行い、単結晶Ｓｉ
膜を全てＳｉ０ｇ膜にする。Next, as shown in FIG. 1,500 semiconductors N5 are formed.Si of this semiconductor layer 5 is preferably single crystal, but may be polycrystalline or amorphous.Semiconductor layer 5 (St)
A thermal oxide film of approximately 6,000 layers (grown in the direction of the arrow up to the dotted line) was grown in a steam atmosphere, etc., and single crystal Si was grown.
All the films are Si0g films.
この熱酸化膜成長の際、従来であれば熱酸化膜が横方向
にも成長して基板に食い込むため、寸法変換差が大きく
なっていたが、本実施例では素子分離領域６の両端の第
２の耐酸化膜４が半導体層５の酸化時のマスクの役割を
果たすため、寸法変換差を小さくすることができる。During this thermal oxide film growth, in the conventional case, the thermal oxide film also grows laterally and bites into the substrate, resulting in a large dimensional conversion difference, but in this embodiment, the Since the oxidation-resistant film 4 of No. 2 serves as a mask during oxidation of the semiconductor layer 5, the difference in dimension conversion can be reduced.
次にシリコン基板１上の第１の耐酸化膜２及び酸化膜７
を希フッ酸や塩酸、あるいはリン酸（Ｈ３ＰＯ，等）な
どを使ってウェットエツチングし、除去し、表面を平坦
化したのが第１図（ｈ）である。Next, the first oxidation-resistant film 2 and the oxide film 7 on the silicon substrate 1 are formed.
The surface was flattened by wet etching using dilute hydrofluoric acid, hydrochloric acid, or phosphoric acid (H3PO, etc.), and the surface was flattened, as shown in FIG. 1(h).
この平坦化された除去部分は凹凸がないため、その上に
半導体素子（図示しない）などを信頼性良く形成するこ
とができる。Since this flattened removed portion has no irregularities, a semiconductor element (not shown) or the like can be formed thereon with high reliability.
上記したように、本発明の半導体装置の製造方法によっ
て、素子分離領域を形成した場合、基板の横方向へ食い
込むバーズビークの発生が殆どなく、寸法変換差を小さ
くすることができる。このため例えば１μ以下のデザイ
ンルールによる超ＬＳＩの製造にも、本発明は有効に適
用することができる。As described above, when an element isolation region is formed by the method of manufacturing a semiconductor device of the present invention, there is almost no occurrence of bird's beaks that dig into the lateral direction of the substrate, and dimensional conversion differences can be reduced. Therefore, the present invention can be effectively applied to the manufacture of VLSIs using a design rule of 1 μm or less, for example.
また平坦化工程によって素子分離領域上には凹凸がない
ようにでき、その上にさらに半導体素子を形成すること
ができる。Moreover, the planarization process makes it possible to eliminate unevenness on the element isolation region, and further semiconductor elements can be formed thereon.
更に、素子分離領域のエツジ部分は、従来はこのエツジ
部分にリーク電流が発生し易かったが、本発明により得
られるものはストレスが木質的に加わりにくい構造であ
るため、リーク電流を小さく抑えることができる。Furthermore, in the past, leakage current was likely to occur at the edge portion of the element isolation region, but the structure obtained by the present invention is such that stress is not easily applied to the edge portion, so leakage current can be suppressed to a small level. I can do it.
またチャンネルストップ領域において、熱酸化 （’Ｃ
Ｊ）の際の不純物の再分布が少なくなるため、従来と比
較してイオン注入量を減少することができ、不純物拡散
領域の拡がりを少なくすることができる。Also, in the channel stop region, thermal oxidation ('C
Since the redistribution of impurities during step J) is reduced, the amount of ion implantation can be reduced compared to the conventional method, and the spread of the impurity diffusion region can be reduced.
このイオン注入量の減少は、本発明をＭＯＳ ＬＳＩに
適用した場合、ソース、ドレイン領域とチャンネルスト
ップ領域間の接合容量が小さくなるため高速化が図れる
。 （９）When the present invention is applied to a MOS LSI, this reduction in the amount of ion implantation reduces the junction capacitance between the source and drain regions and the channel stop region, thereby increasing the speed. (9)
第１図（ａ）〜（ｈｌは本発明の一実施例を説明する工
程断面図である。FIGS. 1A to 1H are process sectional views illustrating an embodiment of the present invention.
Claims (1)
と、 該第１の耐酸化膜をマスクにして選択的に上記半導体基
板をエッチングして溝を形成する工程と、該溝内と上記
第１の耐酸化膜上を覆って第２の耐酸化膜を形成する工
程と、 該第２の耐酸化膜を異方性エッチングし、上記溝側壁部
に第２の耐酸化膜を残す工程と、少なくとも上記溝内に
半導体層を形成する工程と、 該半導体層を酸化する工程と、 上記第１の耐酸化膜を除去して平坦化する工程とを備え
ると共に、 上記第１の耐酸化膜除去部に半導体素子を形成すること
を特徴とする半導体装置の製造方法。[Claims] A method for manufacturing a semiconductor device having an element isolation region, comprising: selectively forming a first oxidation-resistant film on a semiconductor substrate; and selectively forming a first oxidation-resistant film using the first oxidation-resistant film as a mask. forming a groove by etching the semiconductor substrate; forming a second oxidation-resistant film covering the inside of the groove and over the first oxidation-resistant film; a step of anisotropically etching to leave a second oxidation-resistant film on the trench sidewalls; a step of forming at least a semiconductor layer within the trench; a step of oxidizing the semiconductor layer; and a step of oxidizing the semiconductor layer; A method for manufacturing a semiconductor device, comprising: removing and planarizing a film, and forming a semiconductor element in the first oxidation-resistant film removed portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28673786A JPS63141346A (en) | 1986-12-03 | 1986-12-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28673786A JPS63141346A (en) | 1986-12-03 | 1986-12-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63141346A true JPS63141346A (en) | 1988-06-13 |
Family
ID=17708368
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28673786A Pending JPS63141346A (en) | 1986-12-03 | 1986-12-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63141346A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5457067A (en) * | 1993-10-14 | 1995-10-10 | Goldstar Electron Co., Ltd. | Process for formation of an isolating layer for a semiconductor device |
| US5681776A (en) * | 1994-03-15 | 1997-10-28 | National Semiconductor Corporation | Planar selective field oxide isolation process using SEG/ELO |
| US5972776A (en) * | 1995-12-22 | 1999-10-26 | Stmicroelectronics, Inc. | Method of forming a planar isolation structure in an integrated circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5432984A (en) * | 1977-08-19 | 1979-03-10 | Hitachi Ltd | Integrated circuit device |
| JPS5893287A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS60171737A (en) * | 1984-02-17 | 1985-09-05 | Hitachi Ltd | Manufacture of semiconductor device |
-
1986
- 1986-12-03 JP JP28673786A patent/JPS63141346A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5432984A (en) * | 1977-08-19 | 1979-03-10 | Hitachi Ltd | Integrated circuit device |
| JPS5893287A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS60171737A (en) * | 1984-02-17 | 1985-09-05 | Hitachi Ltd | Manufacture of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5457067A (en) * | 1993-10-14 | 1995-10-10 | Goldstar Electron Co., Ltd. | Process for formation of an isolating layer for a semiconductor device |
| US5681776A (en) * | 1994-03-15 | 1997-10-28 | National Semiconductor Corporation | Planar selective field oxide isolation process using SEG/ELO |
| US5972776A (en) * | 1995-12-22 | 1999-10-26 | Stmicroelectronics, Inc. | Method of forming a planar isolation structure in an integrated circuit |
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