JPS63136694A - Multilayer interconnection board - Google Patents
Multilayer interconnection boardInfo
- Publication number
- JPS63136694A JPS63136694A JP28200686A JP28200686A JPS63136694A JP S63136694 A JPS63136694 A JP S63136694A JP 28200686 A JP28200686 A JP 28200686A JP 28200686 A JP28200686 A JP 28200686A JP S63136694 A JPS63136694 A JP S63136694A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- signal
- ground
- layer
- wirings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 description 34
- 230000000694 effects Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、多層配線基板に係わシ、特にその配線構造に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer wiring board, and particularly to its wiring structure.
従来、この種の多層配線基板の導体層は、第２図に示す
ように互いに直交する方向に配線が形成されている２つ
の信号配線層２３ｍ 、 ２３ｂが、上下に隣接され、
さらにこの２つの信号配線層２ｋ ＋ ２３ｂの上下に
グランド層２２ａ ＊ ２２ｂが隣接される構造となっ
ていた。なお、２１は各層間を電気的に絶縁する層間絶
縁層である。Conventionally, as shown in FIG. 2, the conductor layer of this type of multilayer wiring board has two signal wiring layers 23m and 23b, in which wiring is formed in directions orthogonal to each other, which are vertically adjacent to each other.
Furthermore, the structure was such that ground layers 22a*22b were adjacent to each other above and below these two signal wiring layers 2k+23b. Note that 21 is an interlayer insulating layer that electrically insulates each layer.
前述した従来の多層配線基板は、信号配線層２３ａ ｅ
２３ｂの上下部にグランド層２２１ ｅ ２２ｂを隣
接配置する構成では、同−場内で隣接する信号配線層２
３ａ 、 ２３ｂ間のスペースが小さくなると、信号伝
播にともなうクロストークノイズが大きくなシ、正常な
信号伝播が困難になるという問題があった。The conventional multilayer wiring board described above has signal wiring layers 23a e
In the configuration in which the ground layers 221e and 22b are arranged adjacently above and below the ground layer 23b, the signal wiring layer 2 adjacent to each other in the same field
When the space between 3a and 23b becomes smaller, there is a problem in that crosstalk noise accompanying signal propagation becomes large and normal signal propagation becomes difficult.
これは、グランド層２２ａ ＊ ２２ｂが信号配線層２
３ｍ、２３ｂの上下に位置しているため、信号配線層２
３ａ ｅ ２３ｂが同一層内で比較的長い距離にわたっ
て隣接している場合、そのクロストークノイズをおさえ
る効果が低いことに起因している。This means that the ground layer 22a * 22b is the signal wiring layer 2.
Since it is located above and below 3m and 23b, the signal wiring layer 2
This is because when 3a e 23b are adjacent to each other over a relatively long distance in the same layer, the effect of suppressing crosstalk noise is low.
本発明は前述した従来の問題に鑑みてなされたもので、
その目的は、信号配線間のクロストークノイズを軽減さ
せた多層配線基板を提供することを目的としている。The present invention was made in view of the above-mentioned conventional problems, and
The purpose is to provide a multilayer wiring board in which crosstalk noise between signal wirings is reduced.
本発明の多層配線基板は、信号配線層とグランド層とを
分けずに同一層内に形成したもので、具体的には、信号
配線とグランド配線とを同一層内において互いに隣接配
置する構造としたものである。The multilayer wiring board of the present invention has a signal wiring layer and a ground layer formed in the same layer without separating them, and specifically, has a structure in which the signal wiring and the ground wiring are arranged adjacent to each other in the same layer. This is what I did.
本発明においては、同一層内に信号配線とグランド配線
とを交互に隣接して配置されるので、信号配線間のクロ
ストークノイズが小さくなる。In the present invention, since the signal wiring and the ground wiring are arranged adjacent to each other alternately in the same layer, crosstalk noise between the signal wirings is reduced.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す多層配線基板の部分切
欠斜視図である。同図において、層間絶縁層１１の間に
は、グランド配ａ１２ａおよび信号層＊ｔＳａからなる
導体層が形成されておシ、ここでは導体層は、２層のみ
が図示され他は省略されているが、４８号配線１３ｍの
両隣シには、かならずグランド配線１２ｍが形成され、
信号層５１ｓａとグランド配線１２＆とが交互に配置さ
れている。また、これらのグランド配線１２ｍおよび信
号配線１３＆の上廖には絶縁層１１を介してグランド配
線１２ｂおよび信号配線１３ｂが形成されておシ、その
配線パターンの向きはグランド配線１２ａ、信号配線１
３ａと直交している。また、グランド配線１２ｂおよび
信号配線１３ｂも交互に配置されておシ、信号配線同志
が同一層内で隣接することはない。さらに２つの信号配
線層１３ｍと信号配線層１３ｂとは図示されないが、適
当なピアホールで互いに電気的に・接続され、グランド
配線１２＆とグランド配線１２ｂも同様に図示しない複
数のピアホールを介して電気的に接続されてネットワー
ク構造をなして形成されている。なお、信号配線１３ｍ
、 １３ｂの線幅は、約３０μｍで膜厚は２０μｍで
ある。グランド配線１２ａ 、 １２ｂの線幅は、約２
０７ｊｍで膜厚は２０μｍである。グランド配線１２＆
と信号配線１３ａとの間の距離は約１５／１ｍである。FIG. 1 is a partially cutaway perspective view of a multilayer wiring board showing an embodiment of the present invention. In the figure, a conductor layer consisting of a ground wiring a12a and a signal layer *tSa is formed between the interlayer insulating layers 11. Here, only two conductor layers are shown and the others are omitted. However, ground wiring 12m is always formed on both sides of No. 48 wiring 13m,
Signal layers 51sa and ground wiring 12& are alternately arranged. Furthermore, ground wiring 12b and signal wiring 13b are formed on the upper wall of these ground wiring 12m and signal wiring 13& through insulating layer 11, and the orientation of the wiring pattern is that of ground wiring 12a and signal wiring 1.
It is perpendicular to 3a. Furthermore, the ground wirings 12b and the signal wirings 13b are also arranged alternately, and the signal wirings are not adjacent to each other in the same layer. Furthermore, although not shown, the two signal wiring layers 13m and 13b are electrically connected to each other through appropriate peer holes, and the ground wiring 12& and the ground wiring 12b are similarly electrically connected to each other through a plurality of peer holes (not shown). are connected to form a network structure. In addition, signal wiring 13m
, 13b has a line width of about 30 μm and a film thickness of 20 μm. The line width of the ground wirings 12a and 12b is approximately 2
07jm and the film thickness is 20 μm. Ground wiring 12&
The distance between the signal line 13a and the signal line 13a is approximately 15/1 m.
グランド配線１２ｂと信号配線１３ｂとの間の距離も同
様に約１５μｍである。また、絶縁層１１の材質は、ポ
リイミド樹脂もしくはテフロン系の樹脂であシ、厚さは
一層あたシ２０〜５０７７ｍである。また、信号層ｍ１
３ｍ 、 １３ｂおよびグランド配線１２ｍ 、 １２
ｂの材料は、金、銅、アルミニウムなどが用いられる。Similarly, the distance between the ground wiring 12b and the signal wiring 13b is about 15 μm. The material of the insulating layer 11 is polyimide resin or Teflon resin, and the thickness is 20 to 5077 m per layer. In addition, the signal layer m1
3m, 13b and ground wiring 12m, 12
As the material b, gold, copper, aluminum, etc. are used.
以上説明したように本発明は、同一層内において信号配
線の両隣シにグランド配線を形成し、１６号配線とグラ
ンド配線とを交互に配置することによシ、信号配線間の
クロストークノイズを少なくすることができるという極
めて優れた効果が得られる。As explained above, the present invention forms ground wiring on both sides of the signal wiring in the same layer, and alternately arranges the No. 16 wiring and the ground wiring, thereby reducing crosstalk noise between the signal wiring. An extremely excellent effect can be obtained in that it can be reduced.
第１図は本発明の一実施例を示す多層配線基板の部分切
欠斜視図、第２図は従来の多層配線基板の断面図である
。
１１．２１−−−−絶縁層、１２ａ ＊ １１ｂ ・＠
昏・グランド配線、１３ａ ｔ １３ｂ・拳拳・信号
配線、２２ａ ｔ ２２ｂ ６ ＠ −−グランド層、
２３ａ ｓ ２３ｂ ＊ ＠・・信号層。FIG. 1 is a partially cutaway perspective view of a multilayer wiring board showing an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional multilayer wiring board. 11.21---Insulating layer, 12a * 11b ・@
Coma/ground wiring, 13a t 13b/fist/signal wiring, 22a t 22b 6 @ -- ground layer,
23a s 23b * @...Signal layer.
Claims (1)
板において、前記信号配線とグランド配線とを同一層内
で交互に隣接して配置することを特徴とした多層配線基
板。1. A multilayer wiring board having a plurality of signal wirings and ground wirings, wherein the signal wirings and the ground wirings are alternately arranged adjacent to each other within the same layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28200686A JPS63136694A (en) | 1986-11-28 | 1986-11-28 | Multilayer interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28200686A JPS63136694A (en) | 1986-11-28 | 1986-11-28 | Multilayer interconnection board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63136694A true JPS63136694A (en) | 1988-06-08 |
Family
ID=17646912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28200686A Pending JPS63136694A (en) | 1986-11-28 | 1986-11-28 | Multilayer interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63136694A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0225156U (en) * | 1988-08-05 | 1990-02-19 | ||
| JPH0261052U (en) * | 1988-10-28 | 1990-05-07 | ||
| JP2008153542A (en) * | 2006-12-19 | 2008-07-03 | Shinko Electric Ind Co Ltd | Multilayer wiring board |
-
1986
- 1986-11-28 JP JP28200686A patent/JPS63136694A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0225156U (en) * | 1988-08-05 | 1990-02-19 | ||
| JPH0261052U (en) * | 1988-10-28 | 1990-05-07 | ||
| JP2008153542A (en) * | 2006-12-19 | 2008-07-03 | Shinko Electric Ind Co Ltd | Multilayer wiring board |
| US8076588B2 (en) | 2006-12-19 | 2011-12-13 | Shinko Electric Industries Co., Ltd. | Multilayer wiring board |
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