JPS6313352B2 - - Google Patents

Info

Publication number
JPS6313352B2
JPS6313352B2 JP16538379A JP16538379A JPS6313352B2 JP S6313352 B2 JPS6313352 B2 JP S6313352B2 JP 16538379 A JP16538379 A JP 16538379A JP 16538379 A JP16538379 A JP 16538379A JP S6313352 B2 JPS6313352 B2 JP S6313352B2
Authority
JP
Japan
Prior art keywords
electrode
source
metal electrode
region
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16538379A
Other languages
Japanese (ja)
Other versions
JPS5688362A (en
Inventor
Akio Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP16538379A priority Critical patent/JPS5688362A/en
Publication of JPS5688362A publication Critical patent/JPS5688362A/en
Publication of JPS6313352B2 publication Critical patent/JPS6313352B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 この発明は、二重拡散により半導体基板にベー
ス領域とソース領域を自己整合的に形成して得ら
れる電力用縦型MOSトランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power vertical MOS transistor obtained by forming a base region and a source region in a semiconductor substrate in a self-aligned manner by double diffusion.

この種の縦型MOSトランジスタを大電力化す
る場合、ゲート金属電極およびソース金属電極の
抵抗を小さくするためにその面積を大きくとる必
要がある。このときゲート領域長を長くしてトラ
ンジスタのオン抵抗を下げようとすると、チツプ
サイズが非常に大きいものになつてしまう。そこ
で、チツプの有効利用を図るためにソース金属電
極下で複数に分割されたソース領域を設けてゲー
ト領域長をかせぎ、このソース金属電極下の絶縁
膜中に例えば多結晶シリコンからなる埋込みゲー
ト電極を設けることが考えられている。しかし、
多結晶シリコンからなる埋込み電極は金属電極に
比べて抵抗が大きいため、特にチツプサイズの大
きい大電力用ではその影響が大きく、高速スイツ
チング動作の妨げとなる。 When increasing the power of this type of vertical MOS transistor, it is necessary to increase the area of the gate metal electrode and source metal electrode in order to reduce their resistance. At this time, if an attempt is made to reduce the on-resistance of the transistor by increasing the length of the gate region, the chip size will become extremely large. Therefore, in order to effectively utilize the chip, a source region divided into a plurality of parts is provided under the source metal electrode to increase the gate region length, and a buried gate electrode made of, for example, polycrystalline silicon is formed in the insulating film under the source metal electrode. It is being considered to establish a but,
Since buried electrodes made of polycrystalline silicon have a higher resistance than metal electrodes, this has a large effect, especially in high-power applications with large chips, and hinders high-speed switching operations.

この発明は上記の点に鑑み、チツプの有効利用
と低いオン抵抗を実現し、且つ高速スイツチング
動作を可能とした電力用縦型MOSトランジスタ
を提供することを目的とする。 In view of the above points, it is an object of the present invention to provide a vertical MOS transistor for power use that realizes effective chip utilization, low on-resistance, and high-speed switching operation.

この発明による電力用縦型MOSトランジスタ
は、ソース電極下で複数個に分割されたソース領
域を有し、ソース電極下の絶縁膜中に埋め込まれ
た半導体ゲート電極を有する基本構造において、
半導体ゲート電極に重ねてその低抵抗化のために
部分的にゲート金属電極を配設し、且つそのゲー
ト金属電極が配設された領域下にも複数のソース
領域を形成してなることを特徴とする。 The power vertical MOS transistor according to the present invention has a basic structure including a source region divided into a plurality of parts under a source electrode, and a semiconductor gate electrode embedded in an insulating film under the source electrode.
It is characterized in that a gate metal electrode is partially disposed over the semiconductor gate electrode to lower its resistance, and a plurality of source regions are also formed under the region where the gate metal electrode is disposed. shall be.

この発明の一実施例の平面図を第１図に、その
Ａ−A′断面図を第２図に示す。図中、１はn+型
Si基板であり、その上にドレイン領域となるn-型
層２が設けられ、このn-型層２に二重拡散によ
つてｐ型ベース領域３，３1，３2，…とn+型ソー
ス領域４，４1，４2，…が自己整合的に形成され
ている。そして基板表面にはシリコン酸化膜５を
介して不純物がドープされた多結晶シリコン膜か
らなる埋込みゲート電極６が配設されている。こ
の埋込みゲート電極６にはソース領域４からの電
極取出しのための孔があけられており、埋込みゲ
ート電極６上に更にシリコン酸化膜７を介して、
各ソース領域４にコンタクトするソース金属電極
８および埋込みゲート電極６にコンタクトするゲ
ート金属電極９が配設されている。図から明らか
なようにこの構造では、複数のソース領域が島状
に配列形成され、その各ソース領域周辺にチヤネ
ル領域を形成することにより、チヤネル領域幅を
十分に稼いでいることが基本である。これによ
り、低いオン抵抗が得られる。ところが素子が大
面積になると、多結晶シリコン膜からなる埋込み
ゲート電極６だけではゲート抵抗が大きくなる。
このため、この埋込みゲート電極６に部分的に重
なるゲート金属電極９を配設することにより、ゲ
ート抵抗を小さくしている。そしてこの場合、ゲ
ート金属電極９の領域下にも複数のソース領域を
形成することによつて、素子チツプ面積の有効利
用とより低いオン抵抗を実現している。 A plan view of one embodiment of the present invention is shown in FIG. 1, and a sectional view taken along line A-A' is shown in FIG. In the figure, 1 is n + type
It is a Si substrate, on which an n - type layer 2 which becomes a drain region is provided, and p type base regions 3, 3 1 , 3 2 , ... and n + Type source regions 4, 4 1 , 4 2 , . . . are formed in a self-aligned manner. A buried gate electrode 6 made of a polycrystalline silicon film doped with impurities is provided on the surface of the substrate via a silicon oxide film 5. A hole is made in this buried gate electrode 6 for taking out the electrode from the source region 4, and a silicon oxide film 7 is further placed on the buried gate electrode 6.
A source metal electrode 8 in contact with each source region 4 and a gate metal electrode 9 in contact with the buried gate electrode 6 are provided. As is clear from the figure, the basic principle of this structure is that multiple source regions are arranged in an island shape, and a channel region is formed around each source region to obtain a sufficient width of the channel region. . This results in low on-resistance. However, when the area of the device becomes large, the gate resistance increases with only the buried gate electrode 6 made of a polycrystalline silicon film.
Therefore, gate resistance is reduced by providing a gate metal electrode 9 that partially overlaps this buried gate electrode 6. In this case, by forming a plurality of source regions also under the region of the gate metal electrode 9, effective use of the device chip area and lower on-resistance are realized.

この実施例の効果を、より具体的に図面を用い
て説明する。第３図は、この実施例の素子を第１
図より広い範囲で見た平面図であり、第４図はこ
れに対応する比較例の平面図である。第１図は、
第３図の一点鎖線で囲んだ領域Ａにほぼ対応す
る。素子面積が大きくなると、多結晶シリコン膜
からなる埋込みゲート電極の抵抗が大きくなるた
めに、第３図、第４図に示すように埋込みゲート
電極に重ねてゲート金属電極９を張り巡らすこと
が望ましい。このゲート金属電極９下には常識的
には第４図に示すようにソース領域は設けられな
い。ゲート金属電極９の下には埋込みゲート電極
があり、ゲート電極をマスクとしてソース領域を
拡散形成する通常の工程ではここにソース領域を
形成することができず、またソース領域を設けて
もソース電極をコンタクトさせなければ意味がな
いからである。そしてこの第４図のような構成で
ゲート金属電極９が長く張り巡らされると、その
下にはチヤネルが形成されないのでチツプの有効
面積が少なくなる。これに対してこの実施例で
は、第３図に示すようにゲート金属電極９下の埋
込みゲート電極下にも複数のソース領域を配置す
る。これにより、ゲート金属電極９下の領域をよ
り有効に利用して低いオン抵抗を得ることができ
るのである。この場合、従来のゲート電極をマス
クとする単純な二重拡散法では、埋込みゲート電
極下にソース領域を形成することはできない。従
つて工程的には、後に説明するように従来の二重
拡散法に若干の変更が必要である。またゲート金
属電極９下のソース領域にもソース電極８をコン
タクトさせることが必要である。このためこの部
分のソース領域は、例えば第３図に示すように細
長いゲート金属電極９を幅方向に横切るようなパ
ターンとし、第２図に示したようにゲート金属電
極９の外でソース電極８をゲート金属電極９下の
ソース領域にコンタクトさせているのである。 The effects of this embodiment will be explained in more detail with reference to the drawings. FIG. 3 shows the device of this example in the first
This is a plan view of a wider area than the figure, and FIG. 4 is a plan view of a comparative example corresponding to this. Figure 1 shows
This area approximately corresponds to the area A surrounded by the dashed line in FIG. As the device area increases, the resistance of the buried gate electrode made of a polycrystalline silicon film increases, so it is desirable to extend the gate metal electrode 9 overlapping the buried gate electrode as shown in FIGS. 3 and 4. . Under common sense, no source region is provided under this gate metal electrode 9, as shown in FIG. There is a buried gate electrode under the gate metal electrode 9, and a source region cannot be formed here in the normal process of diffusion forming a source region using the gate electrode as a mask, and even if a source region is provided, the source electrode This is because there is no point in contacting the If the gate metal electrode 9 is extended for a long time in the structure shown in FIG. 4, no channel will be formed under it, and the effective area of the chip will be reduced. On the other hand, in this embodiment, a plurality of source regions are also arranged under the buried gate electrode under the gate metal electrode 9, as shown in FIG. Thereby, the region under the gate metal electrode 9 can be used more effectively to obtain low on-resistance. In this case, the source region cannot be formed under the buried gate electrode by a simple double diffusion method using the conventional gate electrode as a mask. Therefore, in terms of process, it is necessary to make some changes to the conventional double diffusion method, as will be explained later. It is also necessary to bring the source electrode 8 into contact with the source region under the gate metal electrode 9. For this reason, the source region in this part is formed into a pattern that crosses the elongated gate metal electrode 9 in the width direction as shown in FIG. is brought into contact with the source region under the gate metal electrode 9.

この構造を得るための製造工程を説明すると、
まずn+型Si基板１にn-型層２をエピタキシヤル
成長させ、その表面に熱酸化によりシリコン酸化
膜５を形成する。そしてこの酸化膜５のソース領
域となるべき個所に孔あけを行い、ｐ型不純物を
拡散し、続いてｎ型不純物を拡散させて、ベース
領域３、ソース領域４を形成する。その後、全面
を酸化し、不純物をドープした多結晶シリコン膜
をCVD法により堆積して埋込みゲート電極６を
形成する。そして全面につけた埋込みゲート電極
６のうち、後につけるソース金属電極とソース領
域４とのコンタクトをとるべき部分を選択的にエ
ツチングした後、全面にCVD法によりシリコン
酸化膜７を堆積する。そして最後にコンタクトホ
ールをあけ、Al膜の蒸着、パターニングの工程
を経て、ソース領域４にコンタクトするソース金
属電極８、埋込みゲート電極６にコンタクトする
ゲート金属電極９を形成して完成する。 To explain the manufacturing process to obtain this structure,
First, an n - type layer 2 is epitaxially grown on an n + type Si substrate 1, and a silicon oxide film 5 is formed on its surface by thermal oxidation. Then, a hole is formed in a portion of this oxide film 5 that is to become a source region, and a p-type impurity is diffused, and then an n-type impurity is diffused to form a base region 3 and a source region 4. Thereafter, the entire surface is oxidized and a polycrystalline silicon film doped with impurities is deposited by CVD to form a buried gate electrode 6. After selectively etching the portions of the buried gate electrode 6 formed on the entire surface where the source metal electrode to be added later and the source region 4 should be in contact, a silicon oxide film 7 is deposited on the entire surface by CVD. Finally, a contact hole is opened, and a source metal electrode 8 in contact with the source region 4 and a gate metal electrode 9 in contact with the buried gate electrode 6 are formed through the steps of vapor deposition and patterning of an Al film to complete the process.

このような構成とすれば、ゲート金属電極およ
びソース金属電極のそれぞれの下に複数のソース
領域を設けているから、チツプは有効に利用さ
れ、またゲート領域長が長くなつてオン抵抗が小
さくなる。しかも、ゲート電極は抵抗の高い多結
晶シリコンからなる埋込み電極だけでなく金属電
極を併用しているため、高速のスイツチング動作
が可能である。 With this configuration, a plurality of source regions are provided under each of the gate metal electrode and source metal electrode, so the chip can be used effectively, and the gate region length is increased, reducing the on-resistance. . Moreover, since the gate electrode uses not only a buried electrode made of polycrystalline silicon with high resistance but also a metal electrode, high-speed switching operation is possible.

なお、この発明は上記実施例に限られるもので
はなく、その趣旨を逸脱しない範囲で種々変形実
施できることができる。 Note that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the spirit thereof.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例の平面図、第２図
はそのＡ−A′断面図、第３図は実施例の素子を
より広い範囲で見た平面図、第４図は第３図に対
応させて示す比較例の平面図である。 １……n+型Si基板、２……n-型層（ドレイン
領域）、３，３1，３2，…，……ｐ型ベース領域、
４，４1，４2，…，……n+型ソース領域、５……
シリコン酸化膜、６……埋込みゲート電極、７…
…シリコン酸化膜、８……ソース金属電極、９…
…ゲート金属電極。 FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line A-A', FIG. 3 is a plan view showing the device of the embodiment in a wider area, and FIG. FIG. 3 is a plan view of a comparative example shown in correspondence with the figure. 1... n + type Si substrate, 2... n - type layer (drain region), 3, 3 1 , 3 2 ,...,... p type base region,
4, 4 1 , 4 2 ,...,...n + type source region, 5...
Silicon oxide film, 6... buried gate electrode, 7...
...Silicon oxide film, 8...Source metal electrode, 9...
...Gate metal electrode.

Claims (1)

【特許請求の範囲】[Claims] １ ドレイン領域となる第１導電型半導体層と、
この半導体層表面に島状をなして複数個配列形成
された第２導電型のベース領域と、これら各ベー
ス領域内に自己整合的に形成された第１導電型の
ソース領域と、これらソース領域を取囲む領域に
絶縁膜を介して配設された半導体ゲート電極と、
このゲート電極上に絶縁膜を介して積層され、前
記各ソース領域に同時にコンタクトするソース電
極とを有する電力用縦型MOSトランジスタにお
いて、前記半導体ゲート電極上に部分的に重ねて
ゲート金属電極が形成され、このゲート金属電極
領域下に複数のソース領域を配列形成してなるこ
とを特徴とする電力用縦型MOSトランジスタ。1 a first conductivity type semiconductor layer serving as a drain region;
A plurality of base regions of the second conductivity type formed in an array in the form of islands on the surface of the semiconductor layer, source regions of the first conductivity type formed in a self-aligned manner within each of these base regions, and these source regions. a semiconductor gate electrode disposed via an insulating film in a region surrounding the
In a power vertical MOS transistor having a source electrode laminated on the gate electrode via an insulating film and simultaneously in contact with each of the source regions, a gate metal electrode is formed partially overlapping the semiconductor gate electrode. A power vertical MOS transistor characterized in that a plurality of source regions are arranged and formed under the gate metal electrode region.
JP16538379A 1979-12-19 1979-12-19 Vertical type power mos transistor Granted JPS5688362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16538379A JPS5688362A (en) 1979-12-19 1979-12-19 Vertical type power mos transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16538379A JPS5688362A (en) 1979-12-19 1979-12-19 Vertical type power mos transistor

Publications (2)

Publication Number Publication Date
JPS5688362A JPS5688362A (en) 1981-07-17
JPS6313352B2 true JPS6313352B2 (en) 1988-03-25

Family

ID=15811336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16538379A Granted JPS5688362A (en) 1979-12-19 1979-12-19 Vertical type power mos transistor

Country Status (1)

Country Link
JP (1) JPS5688362A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4631564A (en) * 1984-10-23 1986-12-23 Rca Corporation Gate shield structure for power MOS device
US4801986A (en) * 1987-04-03 1989-01-31 General Electric Company Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method
JPH0834312B2 (en) * 1988-12-06 1996-03-29 富士電機株式会社 Vertical field effect transistor
JP3150443B2 (en) * 1992-09-10 2001-03-26 株式会社東芝 Semiconductor device

Also Published As

Publication number Publication date
JPS5688362A (en) 1981-07-17

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