JPS63128739U - - Google Patents
Info
- Publication number
- JPS63128739U JPS63128739U JP2151187U JP2151187U JPS63128739U JP S63128739 U JPS63128739 U JP S63128739U JP 2151187 U JP2151187 U JP 2151187U JP 2151187 U JP2151187 U JP 2151187U JP S63128739 U JPS63128739 U JP S63128739U
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- integrated circuit
- circuit device
- ceramic substrate
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Description
第１図は本考案の一実施例の断面図、第２図は
第１図の半田付部品近傍の拡大平面図、第３図及
び第４図は従来の混成集積回路装置を説明するた
めの断面図である。
１……レジスト樹脂、２……半田付部品、３…
…ペレツト保護樹脂、４……外装樹脂、５……セ
ラミツク基板、６……リード、７……抵抗、８…
…半田付ランド、９……ケース。
FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is an enlarged plan view of the vicinity of the soldered parts in FIG. 1, and FIGS. 3 and 4 are diagrams for explaining a conventional hybrid integrated circuit device. FIG. 1...Resist resin, 2...Soldering parts, 3...
... Pellet protection resin, 4 ... Exterior resin, 5 ... Ceramic substrate, 6 ... Lead, 7 ... Resistor, 8 ...
...Soldering land, 9...Case.
Claims (1)
受動素子及び能動素子を搭載してなる混成集積回
路装置において、前記印刷配線はレジスト樹脂に
より覆われていることを特徴とする混成集積回路
装置。 1. A hybrid integrated circuit device comprising passive elements and active elements mounted on a ceramic substrate having printed wiring formed on its surface, wherein the printed wiring is covered with a resist resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2151187U JPS63128739U (en) | 1987-02-16 | 1987-02-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2151187U JPS63128739U (en) | 1987-02-16 | 1987-02-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63128739U true JPS63128739U (en) | 1988-08-23 |
Family
ID=30818026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2151187U Pending JPS63128739U (en) | 1987-02-16 | 1987-02-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63128739U (en) |
-
1987
- 1987-02-16 JP JP2151187U patent/JPS63128739U/ja active Pending