JPS63122295A - Multilayer ceramic board with built-in electronic component - Google Patents
Multilayer ceramic board with built-in electronic componentInfo
- Publication number
- JPS63122295A JPS63122295A JP61269238A JP26923886A JPS63122295A JP S63122295 A JPS63122295 A JP S63122295A JP 61269238 A JP61269238 A JP 61269238A JP 26923886 A JP26923886 A JP 26923886A JP S63122295 A JPS63122295 A JP S63122295A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- multilayer ceramic
- electronic component
- multilayer
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims description 50
- 239000000758 substrate Substances 0.000 claims description 45
- 239000003990 capacitor Substances 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 18
- 229910052802 copper Inorganic materials 0.000 claims description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 11
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052763 palladium Inorganic materials 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 3
- 239000012298 atmosphere Substances 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000003985 ceramic capacitor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 238000002788 crimping Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- DJOYTAUERRJRAT-UHFFFAOYSA-N 2-(n-methyl-4-nitroanilino)acetonitrile Chemical compound N#CCN(C)C1=CC=C([N+]([O-])=O)C=C1 DJOYTAUERRJRAT-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- NEIHULKJZQTQKJ-UHFFFAOYSA-N [Cu].[Ag] Chemical compound [Cu].[Ag] NEIHULKJZQTQKJ-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- VTHAZHHBZCRMKA-UHFFFAOYSA-N boranylidynelanthanum Chemical compound [La]#B VTHAZHHBZCRMKA-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- QAVFANVPBSEGTQ-UHFFFAOYSA-N boron;yttrium Chemical compound [Y]#B QAVFANVPBSEGTQ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、多層セラミック基板内に、例えばコンデン
サ、抵抗器、コイル等のチップ形電子部品を内蔵した電
子部品内蔵多層セラミック基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer ceramic substrate with built-in electronic components, in which chip-type electronic components such as capacitors, resistors, coils, etc. are built into the multilayer ceramic substrate.
電子回路をより高密度化、多機能化する等のために、電
子部品を内蔵した多層基板が要望されている。In order to make electronic circuits more dense and multifunctional, there is a demand for multilayer substrates with built-in electronic components.
そのような多層基板の１つに、グリーンシート各層に誘
電体ペースト、絶縁体ペースト、導電ペースト等を厚膜
技術で印刷後、各層を圧着して焼成することによりり、
Ｃ，Ｒ回路等を構成したものがある。しかしこのような
多層基板においては、■圧着・焼成過程でペーストの変
形が起こるため、抵抗値や静電容量等のり、Ｃ，Ｒの特
性を計算通りにすることが困難であること、■使用可能
な誘電体ペーストの誘電率が小さくて大容量コンデンサ
の形成が困難であること、■絶縁体ペーストの比抵抗を
幅広く選択することが困難であること、■印刷積層を繰
り返すに従って印刷部の平面性が非常に悪くなって積層
数を増やすことが困難であること、等の種々の問題があ
る。On one such multilayer board, dielectric paste, insulator paste, conductive paste, etc. are printed on each layer of a green sheet using thick film technology, and then each layer is crimped and fired.
There are some that are configured with C, R circuits, etc. However, in such multilayer boards, ■Due to deformation of the paste during the crimping and firing process, it is difficult to adjust the resistance value, capacitance, etc., and C and R characteristics as calculated. The dielectric constant of possible dielectric pastes is small, making it difficult to form large-capacity capacitors, ■ It is difficult to select a wide range of specific resistances for insulating pastes, and ■ The flatness of the printed part increases as printing layers are repeated. There are various problems such as the fact that the properties are very poor and it is difficult to increase the number of laminated layers.
一方、゛従来の多層基板の他の例として、いわゆる抵抗
・容量付多層基板がある（例えば「エレクトロニク・セ
ラミクスＪ’８５ ５月号 頁６８〜゛６９参照）、こ
れは、セラミックベースの表面にコンデンサ、抵抗器等
を厚膜技術で多層に印刷形成したものである。しかしこ
のような多層基板においても、■印刷パターンの位置ず
れによる特性のばらつき、■コンデンサ容量の制約、■
平面性の悪化、等の上述した多層基板とほぼ同様の問題
がある。On the other hand, as another example of conventional multilayer substrates, there is a so-called multilayer substrate with resistance and capacitance (for example, see "Electronic Ceramics J'85 May issue, pages 68 to 69"), which has a ceramic-based surface. capacitors, resistors, etc. are printed in multiple layers using thick-film technology. However, even with such a multilayer board, there are problems such as: (1) variation in characteristics due to misalignment of the printed pattern, (2) limitations on capacitor capacity, (2)
There are almost the same problems as the above-mentioned multilayer substrate, such as deterioration of planarity.
従ってこの発明は、上述のような問題点を解消すること
ができる電子部品内蔵多層セラミック基板を提供するこ
とを目的とする。Therefore, an object of the present invention is to provide a multilayer ceramic substrate with built-in electronic components that can solve the above-mentioned problems.
この発明の電子部品内蔵多層セラミック基板は、凹部ま
たは貫通孔を有するセラミック基板を含む複数枚のセラ
ミック基板が積層されて成る多層セラミック基板と、多
層セラミック基板内であって前記凹部または貫通孔で形
成される空間内に収納されていて外部取出し電極として
銅を用いたチップ形電子部品と、多層セラミック基板の
層間または前記貫通孔内に設けられていて前記チップ形
電子部品を配線している銅を用いた導体とを備えること
を特徴とする。A multilayer ceramic substrate with built-in electronic components of the present invention includes a multilayer ceramic substrate formed by laminating a plurality of ceramic substrates including a ceramic substrate having a recess or a through hole, and a multilayer ceramic substrate formed in the multilayer ceramic substrate by the recess or the through hole. A chip-shaped electronic component that is housed in a space where copper is used as an external lead-out electrode, and a copper that is provided between the layers of the multilayer ceramic substrate or in the through hole and that wires the chip-shaped electronic component. It is characterized by comprising a conductor used.
チップ形電子部品の外部取出し電極に銅、及び配線用の
導体に銅を用いる理由は以下の通りである。即ち、従来
から用いられている銀をチップ形電子部品の外部取出し
電極とし、導体に銅を用いた場合、例えば導体の焼付な
どの熱処理中に、銀と銅との接触部分で共晶反応を起し
、溶融温度が著しく低下するために接触部分の銀−銅合
金が流れ出し、チップ形電子部品と導体間の接触不良を
もたらす、これに対し、銅をチップ形電子部品の外部取
出し電極とし、導体に銅を用いた場合には、同じ金属で
あるために熱処理を施しても接触部分での金属の溶融に
よる接触不良を起さないからである。The reasons why copper is used for the external lead-out electrodes of chip-type electronic components and for the conductors for wiring are as follows. In other words, when conventionally used silver is used as the external electrode of a chip-type electronic component and copper is used as the conductor, a eutectic reaction occurs at the contact area between the silver and copper during heat treatment such as baking of the conductor. The silver-copper alloy in the contact area flows out due to the melting temperature dropping significantly, resulting in poor contact between the chip-shaped electronic component and the conductor. This is because when copper is used as the conductor, since they are the same metal, even if heat treatment is performed, poor contact due to melting of the metal at the contact portion will not occur.
さらに、パラジウムあるいはニッケルをチップ形電子部
品の内部電極として用いると、パラジウムあるいはニッ
ケルと銅とは全域固溶型の合金となるため、外部取出し
電極の銅との接触部分で溶融温度の低下が起らず、熱処
理を施しても接触不良を起さない。Furthermore, when palladium or nickel is used as the internal electrode of a chip-type electronic component, palladium or nickel and copper form a solid solution alloy throughout the area, so the melting temperature decreases at the part of the external electrode that contacts the copper. Therefore, contact failure does not occur even after heat treatment.
第１図はこの発明の一実施例に係る電子部品内蔵多層セ
ラミック基板を示す概略断面図であり、第２図はその等
価回路図であ机貫通孔７をそれぞれ有するセラミック基
板２１〜２５と貫通孔を有さないセラミック基板２６と
が積層されて多層セラミック基板２が形成されており、
当該多層セラミック基板２内であって各セラミック基板
の貫通孔７の組み合わせで形成される空間内に、チップ
形の受動素子等の電子部品、例えば積層タイプのコンデ
ンサ３．４及び抵抗器５が収納されている。そして当該
コンデンサ３．４及び抵抗器５は、多層セラミック基板
２の層間や貫通孔７内に設けられた導体６で適宜配線さ
れて第２図に示すような回路を構成している。この場合
、各電子部品を収納する空間を、貫通孔７の代わりに各
セラミック基板２１〜２６に適宜設けた凹部で形成する
ようにしても良い。FIG. 1 is a schematic cross-sectional view showing a multilayer ceramic substrate with built-in electronic components according to an embodiment of the present invention, and FIG. A multilayer ceramic substrate 2 is formed by laminating a ceramic substrate 26 having no holes,
Electronic components such as chip-shaped passive elements, such as multilayer capacitors 3.4 and resistors 5, are housed within the multilayer ceramic substrate 2 in a space formed by a combination of the through holes 7 of each ceramic substrate. has been done. The capacitor 3.4 and the resistor 5 are appropriately wired with conductors 6 provided between the layers of the multilayer ceramic substrate 2 or in the through hole 7, thereby forming a circuit as shown in FIG. In this case, the space for accommodating each electronic component may be formed by a recess appropriately provided in each of the ceramic substrates 21 to 26 instead of the through hole 7.
上述のような電子部品内蔵多層セラミック基板の製法の
一例を第３図を参照して説明する。還元雰囲気中で低温
焼結可能なセラミックのグリーンシート２１Ｇ〜２６Ｇ
の内のグリーンシート２１Ｇ〜２５Ｇのそれぞれに、図
示のように収納するコンデンサ３．４、抵抗器５の形状
・寸法およびそれらの配線パターンに応じた位置に大小
の貫通孔７を予め幾つか空けておき、そして非還元性の
コンデンサ３．４及び非還元性の抵抗器５を予めチップ
部品として完成させておいたものを、前記貫通孔７によ
って形成される空間内に挿入し、また銅から成る導電ペ
ースト６Ｐを各グリーンシート２１Ｇ〜２６Ｇの貫通孔
７の部分や層間の所定の箇所に付与した後、各グリーン
シート２１Ｇ〜２６Ｇを圧着し、そして還元雰囲気中に
おいて低温焼成すると、第１図に示した電子部品内蔵多
層セラミック基板が得られる。尚、第３図中の３１．４
１．５１は、それぞれ、チップ形の積層コンデンサ３．
４及び抵抗器５の銅から成る外部取出し電極であり、５
２はセラミック基板の表面に付与された抵抗パターンで
ある。また積層コンデンサ３．４の内部電極（図示省略
）には、パラジウム電極あるいはニッケル電極を用いて
いる。An example of a method for manufacturing a multilayer ceramic substrate with built-in electronic components as described above will be explained with reference to FIG. Ceramic green sheets 21G to 26G that can be sintered at low temperatures in a reducing atmosphere
In each of the green sheets 21G to 25G, several large and small through holes 7 are made in advance at positions corresponding to the shapes and dimensions of the capacitors 3.4 and resistors 5 to be stored and their wiring patterns as shown in the figure. Then, a non-reducing capacitor 3.4 and a non-reducing resistor 5, which have been completed as chip components, are inserted into the space formed by the through hole 7, and made of copper. After applying the conductive paste 6P to the through holes 7 of each of the green sheets 21G to 26G and predetermined locations between the layers, each of the green sheets 21G to 26G is compressed and fired at a low temperature in a reducing atmosphere, resulting in the appearance of FIG. A multilayer ceramic substrate with a built-in electronic component shown in FIG. In addition, 31.4 in Figure 3
1.51 are chip-type multilayer capacitors 3.
4 and an external lead-out electrode made of copper from the resistor 5;
2 is a resistance pattern provided on the surface of the ceramic substrate. Moreover, a palladium electrode or a nickel electrode is used for the internal electrode (not shown) of the multilayer capacitor 3.4.
この場合、上記グリーンシート２１Ｇ〜２６Ｇ等のグリ
ーンシートとしては、例えば、「エレクトロニク・セラ
ミクスＪ’８５ ３月号 頁１８〜１９に開示されてい
るような、Ａ１□０１、ＣａＯｌＳｉｎｇ 、Ｍｇ０ｓ
Ｂｔｕｓと微量添加物から成るセラミック粉末とバイ
ンダーとを混合してドクターブレード法によってシート
状にされたようなものが利用できる。そのようなグリー
ンシートは、例えば窒素等の還元雰囲気中で焼成しても
特性劣化が無く、しかも例えば９００〜１０００℃程度
の比較的低温で焼成することができる。In this case, green sheets such as the green sheets 21G to 26G may be, for example, A1□01, CaOlsing, Mg0s as disclosed in "Electronic Ceramics J'85 March issue, pages 18 to 19.
A sheet made by mixing ceramic powder consisting of Btus and trace additives with a binder and forming it into a sheet by a doctor blade method can be used. Such a green sheet does not deteriorate in characteristics even when fired in a reducing atmosphere such as nitrogen, and can be fired at a relatively low temperature of, for example, about 900 to 1000°C.
また上記コンデンサ３．４等のコンデンサとし゛ては、
例えば、■特公昭５６−４６６４１号公報、■特公昭５
７−４２５８８号公報、■特公昭５７−４９５１５号公
報に開示されているようなチタン酸バリウム系の非還元
性誘電体セラミック組成物、あるいは■特公昭５７−３
７０８１号公報、■特公昭５７−３９００１号公報に開
示されているようなジルコン酸カルシウムを主体とする
非還元性誘電体セラミック組成物を用いた例えば積層タ
イプのセラミックコンデンサが利用できる。そのような
セラミック積層コンデンサの製法の一例が上記■〜■の
公報中に開示されている。このようなコンデンサを用い
れば、グリーンシート中に収納して還元雰囲気中で焼成
しても特性劣化を生じることがない。In addition, as for capacitors such as capacitors 3 and 4 above,
For example, ■Special Publication No. 56-46641, ■Special Publication No. 5
Barium titanate-based non-reducible dielectric ceramic compositions as disclosed in Japanese Patent Publication No. 7-42588, ■ Japanese Patent Publication No. 57-49515, or ■ Japanese Patent Publication No. 57-3
For example, a laminated type ceramic capacitor using a non-reducible dielectric ceramic composition mainly composed of calcium zirconate as disclosed in Japanese Patent Publication No. 7081 and Japanese Patent Publication No. 57-39001 can be used. An example of a method for manufacturing such a ceramic multilayer capacitor is disclosed in the above-mentioned publications ① to ②. If such a capacitor is used, there will be no characteristic deterioration even if it is housed in a green sheet and fired in a reducing atmosphere.
上記抵抗器５等の抵抗器としては、例えば、特開昭５５
−２７７００号公報、特開昭５５−２９１９９号公報に
開示されているようなランタンホウ素、イツトリウムホ
ウ素等の抵抗物質と非還元性ガラスとから成る非還元性
抵抗組成物を、例えばセラミック基板上に付与して還元
雰囲気中で焼成した抵抗器が利用できる。このような抵
抗器を用いれば、グリーンシート中に収納して還元雰囲
気中で焼成しても特性劣化を生じることがない。As a resistor such as the above-mentioned resistor 5, for example, JP-A-55
A non-reducing resistance composition comprising a resistance material such as lanthanum boron or yttrium boron and non-reducing glass as disclosed in Japanese Patent Laid-open No. 55-29199 and Japanese Patent Application Laid-Open No. 55-29199 is coated on a ceramic substrate, for example. It is possible to use a resistor that has been applied with a oxidation agent and fired in a reducing atmosphere. If such a resistor is used, characteristics will not deteriorate even if it is housed in a green sheet and fired in a reducing atmosphere.
より具体例を示すと、厚さ２００μｍのＳｉｎｇ、Ａ
ｈｏ ８、ＢａＯ％ Ｂ ｚｏ’２及びバインダーより
成る低温焼結セラミックグリーンシートに、第３図に示
すように貫通孔を開け、ＢａＴｉＯ３を主成分とする非
還元性積層セラミックコンデンサ及びＬａ５Ｂｔを主成
分とする非還元性抵抗器を貫通孔に挿入し、またＣｕ系
導電ペーストをスクリーン印刷法で所定パターンに印刷
した後、グリーンシートを圧着し、窒素雰囲気中９５０
℃で焼成して第１図に示すような電子部品内蔵多層セラ
ミック基板を得た。そして焼成後の容量、抵抗をＬＣＲ
メータで測定したところ、設計値通りの値が得られた。To give a more specific example, Sing, A with a thickness of 200 μm
As shown in Fig. 3, through holes were made in a low temperature sintered ceramic green sheet consisting of 8, BaO% B zo'2 and a binder, and a non-reducible multilayer ceramic capacitor mainly composed of BaTiO3 and La5Bt as the main component were prepared. After inserting a non-reducing resistor into the through-hole and printing a Cu-based conductive paste in a predetermined pattern using screen printing, a green sheet was pressed and heated at 950°C in a nitrogen atmosphere.
C. to obtain a multilayer ceramic substrate with built-in electronic components as shown in FIG. Then, LCR the capacitance and resistance after firing.
When measured with a meter, the values were obtained as designed.
尚、以上においてはコンデンサ、抵抗器等にパラジウム
内部電極あるいはニッケル内部電極を用いた積層構造の
チップ部品を用いた例を説明したが、この発明はそれに
限定されるものではなく、例えば内部電極を持たず、銅
の外部取出し電極のみを用いた積層構造以外のチップ部
品によって前□ 述−したような構造の電子部品内蔵多
層セラミック基板を構成しても良い。さらに、外部取出
し電極なしのチップ部品に銅より成る導電ペーストを外
部取出し電極として塗布後、セラミックグリーンシート
の貫通孔に挿入しても良い。また、パラジウム内部電極
あるいはニッケル内部電極、胴外部電極及び銅導体には
、それぞれの特性を損なわない範囲で白金、銀、ニッケ
ル、パラジウム等の他の金属を添加しても良い。In the above, examples have been explained in which chip components with a laminated structure using palladium internal electrodes or nickel internal electrodes are used in capacitors, resistors, etc., but the present invention is not limited thereto. A multilayer ceramic substrate with a built-in electronic component having the structure as described above may be constructed using chip components other than a laminated structure using only external copper electrodes. Furthermore, a conductive paste made of copper may be applied as an external electrode to a chip component without an external electrode, and then inserted into the through hole of the ceramic green sheet. Further, other metals such as platinum, silver, nickel, palladium, etc. may be added to the palladium internal electrode or nickel internal electrode, the shell external electrode, and the copper conductor to the extent that their respective characteristics are not impaired.
また、第１図等に示した電子部品内蔵多層セラミック基
板はあくまでも一例であって、この発明がそのような構
造のものに限定されないことは勿論である。Further, the multilayer ceramic substrate with built-in electronic components shown in FIG. 1 and the like is merely an example, and it goes without saying that the present invention is not limited to such a structure.
以上のようにこの発明は、チップ形電子部品を多層セラ
ミック基板内の空間に収納した構造であるため、次のよ
うな利点がある。■従来のように圧着・焼成過程で電子
部品の特性のばらつきが起きることはなく、設計値通り
の特性の電子部品を３次元的に内蔵した多層セラミック
基板が得られる。■コンデンサとしても、チップ形積層
セラミックコンデンサを使用することができるので、大
きな静電容量のものが内蔵可能である。■電子部品は多
層セラミック基板内に形成された空間内に収納されてい
るため、多層基板の平面性を何等悪化させることはなく
、従って積層数の大きな積層基板が容易に得られる。■
電子部品は多層セラミック基板内に実装されているため
、耐湿性等の耐環境性が良く、従って信顛性の高い製品
が得られる。また、チップ形電子部品の外部取出し電極
および配線用の導体のいずれにも銅を用いているため、
熱処理を施しても両者の接触部分での金属の溶融による
接触不良を起すこともない。As described above, since the present invention has a structure in which a chip-shaped electronic component is housed in a space within a multilayer ceramic substrate, it has the following advantages. ■Unlike conventional methods, variations in the characteristics of electronic components do not occur during the crimping and firing process, and a multilayer ceramic substrate containing three-dimensional electronic components with characteristics as designed can be obtained. ■Since a chip-type multilayer ceramic capacitor can be used as a capacitor, it is possible to incorporate a large capacitance. (2) Since the electronic components are housed in the space formed within the multilayer ceramic substrate, the flatness of the multilayer substrate is not deteriorated in any way, and therefore a multilayer substrate with a large number of layers can be easily obtained. ■
Since the electronic components are mounted within the multilayer ceramic substrate, they have good environmental resistance such as moisture resistance, and therefore a highly reliable product can be obtained. In addition, since copper is used for both the external lead-out electrodes and wiring conductors of chip-type electronic components,
Even if heat treatment is performed, contact failure due to melting of the metal at the contact portion between the two will not occur.
第１図はこの発明の一実施例に係る電子部品内蔵多層セ
ラミック基板を示す概略断面図であり、第２図はその等
価回路図である。第３図は、第１図の電子部品内蔵多層
セラミック基板の組み立て前の状態を示す概略断面図で
ある。
２・・・多層セラミック基板、２１〜２６・・・セラミ
ック基板、２１Ｇ〜２６Ｇ・・・グリーンシート、３．
４・・・コンデンサ、５・・・抵抗器、６・・・導体、
７・・・貫通孔。FIG. 1 is a schematic sectional view showing a multilayer ceramic substrate with built-in electronic components according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. FIG. 3 is a schematic cross-sectional view showing the electronic component-embedded multilayer ceramic substrate of FIG. 1 before assembly. 2... Multilayer ceramic substrate, 21-26... Ceramic substrate, 21G-26G... Green sheet, 3.
4... Capacitor, 5... Resistor, 6... Conductor,
7...Through hole.
Claims (3)
複数枚のセラミック基板が積層されて成る多層セラミッ
ク基板と、 多層セラミック基板内であって前記凹部または貫通孔で
形成される空間内に収納されていて外部取出し電極とし
て銅を用いたチップ形電子部品と、多層セラミック基板
の層間または前記貫通孔内に設けられていて前記チップ
形電子部品を配線している銅を用いた導体とを備えるこ
とを特徴とする電子部品内蔵多層セラミック基板。(1) A multilayer ceramic substrate formed by laminating a plurality of ceramic substrates including a ceramic substrate having a recess or a through hole; A chip-shaped electronic component using copper as an external lead-out electrode, and a conductor made of copper that is provided between the layers of the multilayer ceramic substrate or in the through hole and wiring the chip-shaped electronic component. Multilayer ceramic substrate with built-in electronic components.
ウム、外部取出し電極として銅を用いた積層コンデンサ
を含む特許請求の範囲第１項記載の電子部品内蔵多層セ
ラミック基板。(2) The electronic component-embedded multilayer ceramic substrate according to claim 1, wherein the chip-type electronic component includes a multilayer capacitor using palladium as an internal electrode and copper as an external electrode.
ル、外部取出し電極として銅を用いた積層コンデンサを
含む特許請求の範囲第１項記載の電子部品内蔵多層セラ
ミック基板。(3) The electronic component-embedded multilayer ceramic substrate according to claim 1, wherein the chip-shaped electronic component includes a multilayer capacitor using nickel as an internal electrode and copper as an external electrode.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61269238A JPS63122295A (en) | 1986-11-12 | 1986-11-12 | Multilayer ceramic board with built-in electronic component |
| GB8725867A GB2197540B (en) | 1986-11-12 | 1987-11-04 | A circuit structure. |
| DE19873738343 DE3738343A1 (en) | 1986-11-12 | 1987-11-11 | CIRCUIT SUBSTRATE |
| US07/119,674 US4800459A (en) | 1986-11-12 | 1987-11-12 | Circuit substrate having ceramic multilayer structure containing chip-like electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61269238A JPS63122295A (en) | 1986-11-12 | 1986-11-12 | Multilayer ceramic board with built-in electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63122295A true JPS63122295A (en) | 1988-05-26 |
Family
ID=17469580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61269238A Pending JPS63122295A (en) | 1986-11-12 | 1986-11-12 | Multilayer ceramic board with built-in electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63122295A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001345560A (en) * | 2000-02-09 | 2001-12-14 | Ngk Spark Plug Co Ltd | Wiring board, and its manufacturing method, and electronic component |
| JP2002204045A (en) * | 2000-01-31 | 2002-07-19 | Ngk Spark Plug Co Ltd | Method for manufacturing circuit board |
| JP2004527908A (en) * | 2001-03-23 | 2004-09-09 | インテル コーポレイション | Integrated circuit package with capacitor |
| JP2005521231A (en) * | 2001-06-26 | 2005-07-14 | インテル・コーポレーション | Electronic assembly having vertically connected capacitors and method of manufacturing the same |
| JP2009081167A (en) * | 2007-09-25 | 2009-04-16 | Fujitsu Ltd | Wiring board, manufacturing method of wiring board, and apparatus with wiring board |
| US8802998B2 (en) | 2007-09-10 | 2014-08-12 | Murata Manufacturing Co., Ltd. | Ceramic multilayer substrate and method for producing the same |
| WO2016035482A1 (en) * | 2014-09-03 | 2016-03-10 | 株式会社村田製作所 | Ceramic electronic component and method for producing same |
-
1986
- 1986-11-12 JP JP61269238A patent/JPS63122295A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002204045A (en) * | 2000-01-31 | 2002-07-19 | Ngk Spark Plug Co Ltd | Method for manufacturing circuit board |
| JP2001345560A (en) * | 2000-02-09 | 2001-12-14 | Ngk Spark Plug Co Ltd | Wiring board, and its manufacturing method, and electronic component |
| JP4685251B2 (en) * | 2000-02-09 | 2011-05-18 | 日本特殊陶業株式会社 | Wiring board manufacturing method |
| JP2004527908A (en) * | 2001-03-23 | 2004-09-09 | インテル コーポレイション | Integrated circuit package with capacitor |
| JP2005521231A (en) * | 2001-06-26 | 2005-07-14 | インテル・コーポレーション | Electronic assembly having vertically connected capacitors and method of manufacturing the same |
| US8802998B2 (en) | 2007-09-10 | 2014-08-12 | Murata Manufacturing Co., Ltd. | Ceramic multilayer substrate and method for producing the same |
| JP2009081167A (en) * | 2007-09-25 | 2009-04-16 | Fujitsu Ltd | Wiring board, manufacturing method of wiring board, and apparatus with wiring board |
| WO2016035482A1 (en) * | 2014-09-03 | 2016-03-10 | 株式会社村田製作所 | Ceramic electronic component and method for producing same |
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