JPS631112A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS631112A JPS631112A JP61143325A JP14332586A JPS631112A JP S631112 A JPS631112 A JP S631112A JP 61143325 A JP61143325 A JP 61143325A JP 14332586 A JP14332586 A JP 14332586A JP S631112 A JPS631112 A JP S631112A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- driver
- receiver
- internal bus
- inverse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002457 bidirectional effect Effects 0.000 claims 1
- 230000007257 malfunction Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Small-Scale Networks (AREA)
- Information Transfer Systems (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
この発明は、ＬＳＩの範堵に属する集積回路装置に関し
、特に、外部バスと内部バスとを結合するインターフェ
イス部分の改良に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an integrated circuit device belonging to the LSI category, and more particularly to an improvement in an interface portion that connects an external bus and an internal bus.
従来の技術
集積回路装置（以下ＬＳＩと称する）におけるバスイン
ターフェイスとしては、第２図に示す構成が代表的であ
る。As a bus interface in a conventional technology integrated circuit device (hereinafter referred to as LSI), the configuration shown in FIG. 2 is typical.
第２図において、１はＬＳＩのチップを指し、２は外部
の４ピツトデータバス（外部バス）、３はチップ１の内
部回路（例えばレジスタ群）につながる４ビツトデータ
バス（内部バス）である。In Figure 2, 1 refers to an LSI chip, 2 is an external 4-bit data bus (external bus), and 3 is a 4-bit data bus (internal bus) that connects to the internal circuits of chip 1 (for example, a group of registers). be.
外部バス２と内部バス３とを結合するイノターフェイス
として、ドライバ／レシーバ回路部４が設けられている
。この回路部４における１ピット分の構成を第３図に示
している。同図のように、外部バス２と内部バス３とを
それぞれ逆向きに接続する１対のトライステートゲート
ＧｄとＧｒとを備えている。ゲートＧｄはドライバで、
入力イネーブル（ＩＥ）信号がＨレベルになると動作し
、内部バス３の論理信号を外部バス２に導出する。ゲー
トＧｒはし／−バで、出力イネーブル（ＯＥ）信号がＨ
レベルになると動作し、外部バス２の論理信号を内部バ
ス３に導入する。A driver/receiver circuit section 4 is provided as an interface that connects the external bus 2 and the internal bus 3. The configuration of one pit in this circuit section 4 is shown in FIG. As shown in the figure, a pair of tristate gates Gd and Gr are provided which connect an external bus 2 and an internal bus 3 in opposite directions. Gate Gd is a driver,
It operates when the input enable (IE) signal becomes H level, and outputs the logic signal on the internal bus 3 to the external bus 2. The output enable (OE) signal is high at the gate Gr/-bar.
When it reaches the level, it operates and introduces the logic signal of the external bus 2 to the internal bus 3.
ドライバ／レシーバ回路部４の制御部は次のようになっ
ている。このチップ１に対して外部から、チップセレク
ト（Ｃ８）信号が端子５に、リード／ライト（、Ｒ／Ｗ
）信号が端子６にそれぞれ印加される。The control section of the driver/receiver circuit section 4 is as follows. A chip select (C8) signal is sent from the outside to this chip 1 to terminal 5 for read/write (, R/W
) signals are applied to terminals 6, respectively.
外部から本チップ１を選択するときＣ８信号がＬレベル
になる。またその状態で、本チップ１に外部からデータ
信号を与えるときＲ／Ｗ信号がＬレベルになり、本チッ
プ１から外部へデータ信号を取り出すときＲ／Ｗ信号が
Ｈレベルになる。Ｒ／Ｗ信号は、インバータ７で反転さ
れて、上記工Ｅ信号端子８に印加される。When this chip 1 is selected externally, the C8 signal becomes L level. In this state, when a data signal is applied to the chip 1 from the outside, the R/W signal goes to L level, and when the data signal is taken out from the chip 1 to the outside, the R/W signal goes to H level. The R/W signal is inverted by an inverter 7 and applied to the E signal terminal 8.
Ｃ８信号をインバータ９で反転した信号と、Ｒ／Ｗ信号
との論理積がアンドゲート１０でとられ、その出力が上
記ＯＥ信号端子１１に印加される。An AND gate 10 performs a logical product of the C8 signal inverted by an inverter 9 and the R/W signal, and its output is applied to the OE signal terminal 11.
つまり、Ｃ８信号がＬレベル（選択状態）になっていて
、Ｒ／Ｗ信号がＬレベルだと、ＩＥ倍信号Ｈレベルにな
り、ドライバ／レシーバ回路部４はレシーバとして動作
し、外部バス２の信号が内部バス３に導入される。また
ｃｓ倍信号Ｌレベルの状態で、Ｒ／Ｗ信号がＨレベルだ
と、ＯＥ倍信号Ｈレベルになシ、ドライバ／レシーバ回
路部４はドライバとして動作し、内部バス３の信号が外
部バス２に導出される。In other words, when the C8 signal is at L level (selected state) and the R/W signal is at L level, the IE double signal becomes H level, driver/receiver circuit section 4 operates as a receiver, and external bus 2 A signal is introduced onto the internal bus 3. Furthermore, if the R/W signal is at H level while the cs multiplied signal is at L level, the OE multiplied signal is not at H level, the driver/receiver circuit section 4 operates as a driver, and the internal bus 3 signal is transferred to the external bus 2. is derived.
発明が解決しようとする問題点
第２図の従来の構成において、ｃｓ倍信号Ｈレベル（非
選択状態）であって、Ｒ／Ｗ信号がＨレベルのときは、
ＩＥ倍信号○Ｅ倍信号両方ともＬレベルになり、ドライ
バ／レシーバ回路４はドライバモードでもし７−バモー
ドでもないフローティング状態になる。つまシ、第３図
のゲートＧｄ、Ｇｒの出力論理は定まらず、高インピー
ダンス状態になる。Problems to be Solved by the Invention In the conventional configuration shown in FIG. 2, when the cs multiplied signal is at H level (non-selected state) and the R/W signal is at H level,
Both the IE times signal and the E times signal go to the L level, and the driver/receiver circuit 4 enters a floating state that is neither in the driver mode nor in the 7-bar mode. However, the output logic of the gates Gd and Gr in FIG. 3 is not determined and becomes a high impedance state.
このフローティング状態においては、ちょっとした電磁
的な影響で内部バス３にノイズかの沙やすく、回路の誤
動作を引き起すという問題があった。In this floating state, there is a problem in that a slight electromagnetic influence can easily generate noise on the internal bus 3, causing circuit malfunction.
ＬＳＩではなく、個別素子を用いて第２図のような回路
を構成する場合、上記の問題は、内部バス３側にプルア
ップ抵抗を接続し、ゲー）Ｏｒの出力がフローティング
状態になっても、プルアップ抵抗を通して内部バス３を
ドライブして論理を確定させる、という技術で対処する
ことができる。When configuring a circuit like the one shown in Figure 2 using individual elements instead of LSI, the above problem can be solved even if a pull-up resistor is connected to the internal bus 3 side and the output of the gate (or) is in a floating state. This problem can be solved by a technique of driving the internal bus 3 through a pull-up resistor to determine the logic.
しかし、この技術をＬＳＩの内部回路にそのまま適用す
るのは問題が多い。特にＣＭＯ８−ＬＳＩの場合は、上
記のプルアップ抵抗を必要な精度で作り込むのは非常に
困難である。However, there are many problems in directly applying this technology to the internal circuits of LSIs. Particularly in the case of CMO8-LSI, it is extremely difficult to manufacture the above-mentioned pull-up resistor with the necessary precision.
この発明は上述した従来の問題点に鑑みなされたもので
、その目的は、チップセレクト信号が非選択状態になっ
てもドライバ／レシーバ回路部がフローティング状態に
ならないようにしたノイズに強い集積回路装置を提供す
ることにある。This invention was made in view of the above-mentioned conventional problems, and its purpose is to provide a noise-resistant integrated circuit device that prevents the driver/receiver circuit section from becoming floating even when the chip select signal becomes non-selected. Our goal is to provide the following.
問題点を解決するだめの手段
そこでこの発明では、上記ドライバ／レシーバ回路部の
制御回路部に、チップセレクト信号が非選択状態のとき
ドライバ／レシーバ回路部をレシーバとして動作させる
制御機能を持たせた。Means to Solve the Problem Therefore, in the present invention, the control circuit section of the driver/receiver circuit section is provided with a control function for operating the driver/receiver circuit section as a receiver when the chip select signal is in a non-selected state. .
作用
上記チップセレクト信号が非選択状態のときでも、上記
ドライバ／レシーバ回路１はレンーハトして動作し、内
部バスは外部バスの信号に従ってドライブされ、フロー
ティング状態にはならない。Operation Even when the chip select signal is in the non-selected state, the driver/receiver circuit 1 operates normally, the internal bus is driven according to the external bus signal, and the circuit does not go into a floating state.
実施例
第１図はこの発明の一実施例の構成を示しており、第２
図の従来構成と共通する部分には同じ符号をつけである
。Embodiment FIG. 1 shows the configuration of an embodiment of the present invention, and FIG.
Portions common to the conventional configuration in the figure are given the same reference numerals.
第１図の構成において、第２図と異なるのは次の点であ
る。オアゲート１２を設け、インバータ７で反転したＲ
／Ｗ信号をＩＥ信号端子８に印加するだけでなく、Ｃ８
信号もオアゲート１２を介してＩＥ信号端子８に印加す
る構成とした。その他の構成は第２図と同じである。勿
論、ドライバ／レシーバ回路部４の構成は第３図のよう
になっている。The configuration shown in FIG. 1 differs from that shown in FIG. 2 in the following points. An OR gate 12 is provided, and R is inverted by an inverter 7.
In addition to applying the /W signal to IE signal terminal 8, C8
The configuration is such that a signal is also applied to the IE signal terminal 8 via the OR gate 12. Other configurations are the same as in FIG. 2. Of course, the configuration of the driver/receiver circuit section 4 is as shown in FIG.
Ｃ８信号がＬレベル（選択状態）のときの動作は従来と
同じでちる。つまりドライバ／レシーバ回路部・１は、
Ｒ／Ｗ信号がＬレベルのときレシーバとして動作し、Ｒ
／Ｗ信号がＨレベルのときドライバとして動作する。The operation when the C8 signal is at L level (selected state) is the same as the conventional one. In other words, the driver/receiver circuit section 1 is
When the R/W signal is at L level, it operates as a receiver, and the R
Operates as a driver when the /W signal is at H level.
Ｃ８信号がＨレベル（非選択状態）のとき、■Ｅ倍信号
Ｈレベルとなり、ドライバ／レシーバ回路部４はレシー
バとして動作し、外部バス２の論理信号が内部バス３に
導入される。つまり、第３図のゲートＧｒによって内部
バス３がドライブされる。これによって前述したフロー
ティング状態の発生が回避され、内部バス３は論理の確
定した状態に保たれる。When the C8 signal is at H level (non-selected state), the E times signal becomes H level, driver/receiver circuit section 4 operates as a receiver, and the logic signal of external bus 2 is introduced into internal bus 3. That is, the internal bus 3 is driven by the gate Gr shown in FIG. As a result, the above-described floating state is avoided, and the internal bus 3 is maintained in a logically determined state.
発明の効果
以上詳細に説明したように、この発明に係る集積回路装
置にあっては、外部バスと内部バスとを結ぶドライバ／
レシーバ回路部が、チップセレクト信号が非選択状態の
ときにレシーバとして動作し、内部バスをドライブして
その論理を確定しているので、従来のようなフローティ
ング状態はなくなり、内部バスをノイズに強い状態に保
つことができ、ノイズによる誤動作の発生を防止する面
で顕著な効果を奏する。Effects of the Invention As explained in detail above, the integrated circuit device according to the present invention has a driver/driver that connects an external bus and an internal bus.
The receiver circuit operates as a receiver when the chip select signal is in the non-selected state and drives the internal bus to determine its logic, eliminating the conventional floating state and making the internal bus more resistant to noise. This has a remarkable effect in preventing malfunctions caused by noise.
第１図は本発明の一実施例による集積回路装置の要部構
成図、第２図は従来の集積回路装置の要部構成図、第３
図はドライバ／レシーバ回路図の１ビット分の詳細回路
図である。
１・・・ＬＳＩチップ、２・・・外部バス、３・・・内
部バス、４・・・ドライバ／レシーバ回路部、Ｃ８・・
・チップセレクト信号、Ｒ／Ｗ・・・リード／ライト信
号、ＩＥ・・・入力イネーブル信号、ＯＥ・・・出力イ
ネーブル信号
代理人の氏名 弁理士 中 尾 敏 男 ほか１名Ｍ
ｌ 図
第 ２ 図FIG. 1 is a block diagram of main parts of an integrated circuit device according to an embodiment of the present invention, FIG. 2 is a block diagram of main parts of a conventional integrated circuit device, and FIG.
The figure is a detailed circuit diagram for one bit of the driver/receiver circuit diagram. 1...LSI chip, 2...External bus, 3...Internal bus, 4...Driver/receiver circuit section, C8...
・Chip select signal, R/W...read/write signal, IE...input enable signal, OE...output enable signal Name of agent: Patent attorney Toshio Nakao and one other person M
Figure 2
Claims (1)
トライステートゲートからなり、内部バスの論理信号を
外部バスに導出するドライバ、および外部バスの論理信
号を内部バスに導入するレシーバとして動作するドライ
バ／レシーバ回路部をチップ内に有するとともに、チッ
プセレクト信号が選択状態のときリード／ライト信部の
論理に応じて上記ドライバ／レシーバ回路部をドライバ
またはレシーバとして動作させ、チップセレクト信号が
非選択状態のときは上記ドライバ／レシーバ回路部をレ
シーバとして動作させる制御回路部をチップ内に有する
ことを特徴とする集積回路装置。A driver/receiver that serves as an interface between the external bus and the internal bus, consisting of bidirectional tristate gates, and operates as a driver that derives logic signals from the internal bus to the external bus, and a receiver that introduces logic signals from the external bus to the internal bus. The circuit section is included in the chip, and when the chip select signal is in the selected state, the driver/receiver circuit section operates as a driver or receiver according to the logic of the read/write signal section, and when the chip select signal is in the non-selected state, the driver/receiver circuit section is operated as a driver or receiver. An integrated circuit device comprising, in a chip, a control circuit section that causes the driver/receiver circuit section to operate as a receiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61143325A JPH084222B2 (en) | 1986-06-19 | 1986-06-19 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61143325A JPH084222B2 (en) | 1986-06-19 | 1986-06-19 | Integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS631112A true JPS631112A (en) | 1988-01-06 |
| JPH084222B2 JPH084222B2 (en) | 1996-01-17 |
Family
ID=15336162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61143325A Expired - Lifetime JPH084222B2 (en) | 1986-06-19 | 1986-06-19 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH084222B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4653858B2 (en) * | 2008-11-19 | 2011-03-16 | 新日本製鐵株式会社 | Refractory insulation walls and building structures |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59106022A (en) * | 1982-12-10 | 1984-06-19 | Fujitsu Ltd | Bus connecting system |
| JPS60252799A (en) * | 1984-05-24 | 1985-12-13 | ジェイエスアール株式会社 | Paper coating composition |
-
1986
- 1986-06-19 JP JP61143325A patent/JPH084222B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59106022A (en) * | 1982-12-10 | 1984-06-19 | Fujitsu Ltd | Bus connecting system |
| JPS60252799A (en) * | 1984-05-24 | 1985-12-13 | ジェイエスアール株式会社 | Paper coating composition |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4653858B2 (en) * | 2008-11-19 | 2011-03-16 | 新日本製鐵株式会社 | Refractory insulation walls and building structures |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH084222B2 (en) | 1996-01-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |