JPS6280345U - - Google Patents

Info

Publication number
JPS6280345U
JPS6280345U JP1985172124U JP17212485U JPS6280345U JP S6280345 U JPS6280345 U JP S6280345U JP 1985172124 U JP1985172124 U JP 1985172124U JP 17212485 U JP17212485 U JP 17212485U JP S6280345 U JPS6280345 U JP S6280345U
Authority
JP
Japan
Prior art keywords
chip
circuit
bonding pads
utility
registration request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985172124U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985172124U priority Critical patent/JPS6280345U/ja
Publication of JPS6280345U publication Critical patent/JPS6280345U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のチツプにおけるボ
ンデイングパツドのレイアウト図、第2図は従来
のチツプにおけるボンデイングパツドのレイアウ
ト図。
FIG. 1 is a layout diagram of bonding pads in a chip according to an embodiment of the present invention, and FIG. 2 is a layout diagram of bonding pads in a conventional chip.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] チツプ上に形成される回路に固有の拡散領域又
はフイールド酸化領域を有する集積回路装置にお
いて、前記チツプ上に前記回路に接続されないボ
ンデイングパツドが配置されていることを特徴と
する集積回路装置。
An integrated circuit device having a diffusion region or a field oxide region specific to a circuit formed on a chip, characterized in that bonding pads not connected to the circuit are arranged on the chip.
JP1985172124U 1985-11-07 1985-11-07 Pending JPS6280345U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985172124U JPS6280345U (en) 1985-11-07 1985-11-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985172124U JPS6280345U (en) 1985-11-07 1985-11-07

Publications (1)

Publication Number Publication Date
JPS6280345U true JPS6280345U (en) 1987-05-22

Family

ID=31108384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985172124U Pending JPS6280345U (en) 1985-11-07 1985-11-07

Country Status (1)

Country Link
JP (1) JPS6280345U (en)

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