JPH01104029U - - Google Patents

Info

Publication number
JPH01104029U
JPH01104029U JP1987197262U JP19726287U JPH01104029U JP H01104029 U JPH01104029 U JP H01104029U JP 1987197262 U JP1987197262 U JP 1987197262U JP 19726287 U JP19726287 U JP 19726287U JP H01104029 U JPH01104029 U JP H01104029U
Authority
JP
Japan
Prior art keywords
semiconductor device
pad
silicon substrate
gap
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987197262U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987197262U priority Critical patent/JPH01104029U/ja
Publication of JPH01104029U publication Critical patent/JPH01104029U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案に係る半導体装置の第１の実施
例を示す図、第２図は本考案に係る半導体装置の
第２の実施例を示す図、第３図は本考案に係る半
導体装置の第３の実施例を示す図、第４図は従来
の半導体装置を示す図である。 １……シリコン基板、１０，２０，３０……パ
ツド、１１，２１，３１……金属膜、１２，２２
，３２……空隙部。 FIG. 1 is a diagram showing a first embodiment of a semiconductor device according to the present invention, FIG. 2 is a diagram showing a second embodiment of a semiconductor device according to the present invention, and FIG. 3 is a diagram showing a semiconductor device according to the present invention. FIG. 4 is a diagram showing a conventional semiconductor device. 1... Silicon substrate, 10, 20, 30... Pad, 11, 21, 31... Metal film, 12, 22
, 32...Void portion.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] シリコン基板上に形成した回路群と外部回路と
を電気的に接続するパツドに空隙を形成したこと
を特徴とする半導体装置。 A semiconductor device characterized in that a gap is formed in a pad that electrically connects a circuit group formed on a silicon substrate and an external circuit.
JP1987197262U 1987-12-28 1987-12-28 Pending JPH01104029U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987197262U JPH01104029U (en) 1987-12-28 1987-12-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987197262U JPH01104029U (en) 1987-12-28 1987-12-28

Publications (1)

Publication Number Publication Date
JPH01104029U true JPH01104029U (en) 1989-07-13

Family

ID=31487825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987197262U Pending JPH01104029U (en) 1987-12-28 1987-12-28

Country Status (1)

Country Link
JP (1) JPH01104029U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010225654A (en) * 2009-03-19 2010-10-07 Toyota Central R&D Labs Inc Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010225654A (en) * 2009-03-19 2010-10-07 Toyota Central R&D Labs Inc Semiconductor device

Similar Documents

Publication Publication Date Title
JPH01104029U (en)
JPH02102727U (en)
JPS6037239U (en) semiconductor wafer
JPS62122359U (en)
JPS6384941U (en)
JPS6310551U (en)
JPS62152448U (en)
JPS6364035U (en)
JPS63195757U (en)
JPH0173935U (en)
JPS636734U (en)
JPS633145U (en)
JPH01143127U (en)
JPS6359336U (en)
JPH0186246U (en)
JPH0415840U (en)
JPH0446542U (en)
JPH01130535U (en)
JPS6134733U (en) semiconductor wafer
JPS6255351U (en)
JPS5954931U (en) semiconductor integrated circuit
JPS6448027U (en)
JPS5829851U (en) semiconductor element
JPH0176046U (en)
JPS61203561U (en)