JPS6279536A - Test conducting system for information processor - Google Patents

Test conducting system for information processor

Info

Publication number
JPS6279536A
JPS6279536A JP60221383A JP22138385A JPS6279536A JP S6279536 A JPS6279536 A JP S6279536A JP 60221383 A JP60221383 A JP 60221383A JP 22138385 A JP22138385 A JP 22138385A JP S6279536 A JPS6279536 A JP S6279536A
Authority
JP
Japan
Prior art keywords
test
main memory
operating system
memory
securing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60221383A
Other languages
Japanese (ja)
Inventor
Shigezo Mikoyama
三箇山　茂三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60221383A priority Critical patent/JPS6279536A/en
Publication of JPS6279536A publication Critical patent/JPS6279536A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simplify the main memory control of an operating system by securing a test main memory area as a main memory area for a normal one execution part. CONSTITUTION:Receiving a test memory securing request, the operating system activates a memory securing program and allocates the main memory area used by the memory securing program. The operating system transmits a test memory securing completion report including a main memory address allocated to a test auxiliary job to a test controller 14 through a test control interface 15, and causes the memory securing program in an execution pending state. The test controller 14 writes a test program and data in the main memory area allocated to the memory securing program through a test control interface 17, sets a test a test main memory area to an arithmetic processor 12 through a test control interface 16 and conducts a test on the arithmetic processor 12. Thus the main memory control can be simplified.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は情報処理装置に関し、特に演算処理装置の試験
実行方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a test execution method for an arithmetic processing device.

〔従来の技術〕[Conventional technology]

従来、この種の試験実行方式は、オペレーティングシス
テムが主記憶装置の一部を論理的に切離すことにより試
験用主記憶領域を確保していた。Conventionally, in this type of test execution method, the operating system secures a main storage area for testing by logically separating a part of the main storage device.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の試験実行方式は、主記憶の部分切離しを
行うので、オペレーティングシステムの主記憶管理が複
雑になるという欠点がある。The conventional test execution method described above has the disadvantage that the main memory management of the operating system becomes complicated because the main memory is partially separated.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の試験実行方式は、主記憶装置と２台以上の演算
処理装置と演算処理装置の試験を制御する試験制御装置
とを含む構成で、主記憶装置上でオペレーティングシス
テムが動作し、試験制御装置トオペレーティングシステ
ムとの通信手段を有し、主記憶装置の一部分を使用して
１台の演算処理装置の試験を行５情報処理システノ・に
おいて、試験制御装置からの通信手段を介しての試験の
ためのメモリ確保を要求する通知に対してオペレ−ティ
ングシステムが１つの実行部としてメモリ確保プログラ
ムを起動し、メモリ確保プログラムが試験で使用する主
記憶領域を確保することを特徴とする。The test execution method of the present invention has a configuration including a main storage device, two or more arithmetic processing units, and a test control device that controls the testing of the arithmetic processing units. Testing of one arithmetic processing unit using a part of the main memory, with means of communication with the operating system of the equipment, in an information processing system, through the means of communication from the test control device. The operating system activates a memory reservation program as one execution unit in response to a notification requesting memory reservation for the test, and the memory reservation program secures the main storage area to be used in the test.

このように、試験用主記憶領域を通常の１つの実行部用
の主記憶領域として確保することにより、オペレーティ
ングシステムの主記憶管理が単純になる。In this way, main memory management of the operating system is simplified by securing the test main memory area as a main memory area for one normal execution unit.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の試験実行方式が適用された情報処理シ
ステムの一実施例の構成を示す図である。FIG. 1 is a diagram showing the configuration of an embodiment of an information processing system to which the test execution method of the present invention is applied.

この情報処理システムは、演算処理装置１１と、演算処
理装置１２と、主記憶装置１８と、試験制御装置１４と
、演算処理装置１１と試験制御装置１４を接続する試験
制御インタフェース１５と、演算処理装置１２と試験制
御装置１４を接続する試験制御インタフェース１６と、
主記憶装置１Ｂと試験制卸装置１４を接続する試験制御
インタフェースＣ１７を含む構成である。This information processing system includes an arithmetic processing device 11, an arithmetic processing device 12, a main storage device 18, a test control device 14, a test control interface 15 that connects the arithmetic processing device 11 and the test control device 14, and an arithmetic processing device. a test control interface 16 that connects the device 12 and the test control device 14;
The configuration includes a test control interface C17 that connects the main storage device 1B and the test control device 14.

主記憶装置ｌＢ上で動作するオペレーティングシステム
（図示していない）と試験制御装置１４とは、試験制御
インタフェース１５または１６を介して通信を行うこと
が可能となっている。The operating system (not shown) operating on the main storage device IB and the test control device 14 can communicate via the test control interface 15 or 16.

次Ｋ、本実施例の動作を演算処理装置１２の試験を行う
場合について説明する。Next, the operation of this embodiment will be described for the case where the arithmetic processing unit 12 is tested.

試験制御装置１４は、試験制御インタフェース１５を介
してオペレーティングシステムに対し試験用メモリ確保
要求を送る。オペレーティングシステムは、試験用メモ
リ確保要求を受けとるとメモリ確保プログラムを起動し
、メモリ確保プログラムで使用する主記憶領域の割り当
てを通常の実行部と同様に行う。The test control device 14 sends a test memory reservation request to the operating system via the test control interface 15. When the operating system receives a test memory reservation request, it starts a memory reservation program and allocates the main storage area used by the memory reservation program in the same way as a normal execution unit.

主記憶領域の割り当てが完了すると、オペレーティング
システムは試験制卸装置１４に対して、試験補助用ジョ
ブに割り当てた主記憶アドレスを含んだ試験用メモリ確
保完了通知を試験制御インタフェース１５を介して送信
し、メモリ確保プログラムを実行保留状態に置く。試験
制御装置１４は、試験用メモリ確保完了通知を受けとる
と、試験用プログラムとデータをメモリ確保プログラム
に割り当てられた主記憶領域に試験制御インタフェース
１７を介して書込み、試験用主記憶領域を演算処理装置
１２に試験制御インタフェース１６を介して設定し、試
験開始を指示することにより演算処理装置１２の試験を
行う。When the allocation of the main memory area is completed, the operating system sends a test memory reservation completion notification including the main memory address allocated to the test support job to the test control device 14 via the test control interface 15. , places the memory allocation program in execution pending state. Upon receiving the test memory reservation completion notification, the test control device 14 writes the test program and data to the main storage area allocated to the memory reservation program via the test control interface 17, and performs arithmetic processing on the test main storage area. The arithmetic processing device 12 is tested by setting the device 12 via the test control interface 16 and instructing the device 12 to start the test.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、試験用主記憶領域を通常
の１つの実行部用の主記憶領域として確保することによ
り、オペレーティングシステムの主記憶管理を単純にで
きる効果がある。As described above, the present invention has the effect of simplifying the main memory management of the operating system by securing the main memory area for testing as the main memory area for one normal execution unit.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の試験実行方式が適用された情報処理シ
ステムの一実施例の構成図である。 １１・・・・・・演算処理装置。 １２・・・・・・演算処理装置。 １８・・・・・・主記憶装置。 １４・・・・・・試験制御装置。 １５・・・・・・試験制御インタフェース。 １６・・・・・・Ｅ験制御インタフェース。 １７・・・・・・試験制御インタフェース。FIG. 1 is a block diagram of an embodiment of an information processing system to which the test execution method of the present invention is applied. 11... Arithmetic processing unit. 12... Arithmetic processing unit. 18... Main storage device. 14...Test control device. 15...Test control interface. 16...E test control interface. 17...Test control interface.

Claims (1)

【特許請求の範囲】[Claims] 主記憶装置と２台以上の演算処理装置と前記演算処理装
置の試験を制御する試験制御装置とを含む構成で、前記
主記憶装置上でオペレーティングシステムが動作し、前
記試験制御装置と前記オペレーティングシステムとの通
信手段を有し、前記主記憶装置の一部分を使用して１台
の前記演算処理装置の試験を行う情報処理システムにお
いて、前記試験制御装置からの前記通信手段を介しての
試験のためのメモリ確保を要求する通知に対して前記オ
ペレーティングシステムが１つの実行部としてメモリ確
保プログラムを起動し、前記メモリ確保プログラムが試
験で使用する主記憶領域を確保することを特徴とする情
報処理装置の試験実行方式。The configuration includes a main storage device, two or more arithmetic processing units, and a test control device that controls testing of the arithmetic processing devices, and an operating system runs on the main storage device, and the test control device and the operating system in an information processing system that tests one arithmetic processing unit using a part of the main storage device, the information processing system having a means of communication with In response to a notification requesting memory reservation, the operating system activates a memory reservation program as one execution unit, and the memory reservation program secures a main storage area to be used in a test. Test execution method.
JP60221383A 1985-10-03 1985-10-03 Test conducting system for information processor Pending JPS6279536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60221383A JPS6279536A (en) 1985-10-03 1985-10-03 Test conducting system for information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60221383A JPS6279536A (en) 1985-10-03 1985-10-03 Test conducting system for information processor

Publications (1)

Publication Number Publication Date
JPS6279536A true JPS6279536A (en) 1987-04-11

Family

ID=16765915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60221383A Pending JPS6279536A (en) 1985-10-03 1985-10-03 Test conducting system for information processor

Country Status (1)

Country Link
JP (1) JPS6279536A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7297323B2 (en) 2001-09-25 2007-11-20 Kabushiki Kaisha Toshiba Method and apparatus for manufacturing fine particles

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7297323B2 (en) 2001-09-25 2007-11-20 Kabushiki Kaisha Toshiba Method and apparatus for manufacturing fine particles
US7678326B2 (en) 2001-09-25 2010-03-16 Kabushiki Kaisha Toshiba Method and apparatus for manufacturing fine particles

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