JPS6015155B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS6015155B2 JPS6015155B2 JP53165813A JP16581378A JPS6015155B2 JP S6015155 B2 JPS6015155 B2 JP S6015155B2 JP 53165813 A JP53165813 A JP 53165813A JP 16581378 A JP16581378 A JP 16581378A JP S6015155 B2 JPS6015155 B2 JP S6015155B2
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- semiconductor substrate
- semiconductor
- mask
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000013078 crystal Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Recrystallisation Techniques (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
本発明は、立体的多層構造を有する半導体装置の製造方
法に関する。
近年、単結晶半導体基板に絶縁物である単結晶アルミナ
（山２０３サファイア）、単結晶マグネシァ・スピネル
（Ｍ奴Ａｌ２０３）を気相ェピタキシャル成長させ、そ
の上に単結晶半導体層を不純物成長させる技術が開発さ
れている（要すれば特顔昭５０−１３１６１１号参照）
。
この技術を応用すると新しい構造の半導体装置を製造し
たり、その製造プロセスを簡単化することができる。本
発明は、単結晶半導体基板に単結晶絶縁層、単結晶半導
体層を順次ェピタキシャル成長させた半導体ウェハを利
用し、立体的な多層構造を有する半導体装置を簡単に得
ることができるようにするものであり、以下これを詳細
に説明する。本発明は、単結晶半導体基板に或る種のＭ
ＩＳトランジスタ、例えばｎチャンネル・トランジスタ
を形成し、単結晶絶縁層で隔てられた半導体層には前記
半導体基板にそのままでは形成できないような異種のＭ
ＩＳトランジスタ、例えばｐチャネル・トランジスタを
形成することが基本になっている。次に、第１図乃至第
８図を参照しつつ、一実施例である相補型ＭＩＳ電界効
果半導体装置（Ｃ・ＭＩＳ）を製造する場合について説
明する。
第１図参照｛１１ ｐ型シリコン半導体基板１にＡＩ２
０３或いはＭｇＯＮ２０３などの単結晶絶縁層２を気相
ェピタキシャル成長させ、その上にｎ型シリコン半導体
層３をェピタキシャル成長させ、更に、例えば熱酸化法
で形成したフィールド用二酸化シリコン絶縁膜４を形成
した半導体ゥェハを用意する。
第２図参照
（２｝ 通常のフオト・リングラフィ技術を適用して絶
縁膜４のパターニングを行ない素子形成領域部分に閉口
４Ａを形成する。
｛３ー 通常のフオト・リングラフィ技術を適用して半
導体層３のパターニングを行ない閉口３Ａを形成する。
尚、この際のエッチング液としては、例えばフッ酸＋硝
酸、もしくは、アルカリ溶液を使用して良い。第３図参
照
【４｝ 半導体層３をマスクして絶縁層２のエッチング
を行ない関口３Ａを完成させる。
尚、このときのエッチング液としては温度１５０〜２５
０The present invention relates to a method for manufacturing a semiconductor device having a three-dimensional multilayer structure. In recent years, technology has been developed to vapor-phase epitaxially grow insulators such as single crystal alumina (Yama 203 Sapphire) and single crystal magnesia spinel (M-Al203) on a single crystal semiconductor substrate, and to grow a single crystal semiconductor layer on top of this using impurity growth. has been developed.
. By applying this technology, it is possible to manufacture semiconductor devices with new structures and simplify the manufacturing process. The present invention makes it possible to easily obtain a semiconductor device having a three-dimensional multilayer structure by using a semiconductor wafer in which a single crystal insulating layer and a single crystal semiconductor layer are sequentially epitaxially grown on a single crystal semiconductor substrate. This will be explained in detail below. The present invention provides a single crystal semiconductor substrate with a certain type of M.
An IS transistor, for example, an n-channel transistor is formed, and a semiconductor layer separated by a single crystal insulating layer contains a different type of M that cannot be directly formed on the semiconductor substrate.
The basis is to form IS transistors, for example p-channel transistors. Next, with reference to FIGS. 1 to 8, a case of manufacturing a complementary MIS field effect semiconductor device (C-MIS), which is an embodiment, will be described. See Figure 1 {11 AI2 on p-type silicon semiconductor substrate 1
A single crystal insulating layer 2 such as 03 or MgON203 is grown epitaxially in the vapor phase, an n-type silicon semiconductor layer 3 is epitaxially grown thereon, and a field silicon dioxide insulating film 4 formed by, for example, a thermal oxidation method is further grown. Prepare the formed semiconductor wafer. Refer to Fig. 2 (2) Pattern the insulating film 4 by applying normal photo phosphorography technique to form a closed opening 4A in the element forming area. {3- By applying normal photo phosphorography technique The semiconductor layer 3 is patterned to form a closed opening 3A. At this time, as an etching solution, for example, hydrofluoric acid + nitric acid or an alkaline solution may be used. See FIG. 3 [4] The insulating layer 2 is etched using a mask to complete the Sekiguchi 3A.The etching solution used at this time is at a temperature of 150 to 25°C.
0
〔００〕の硫酸、硫酸及び燐酸の混液などを使用して
良い。第４図参照
‘５｝ 熱酸化法、スパッタリング法、化学気相成長法
など適宜の技法を選択して例えば厚さ３００〜１０００
〔Ａ〕の二酸化シリコン絶縁膜４′を形成する。
第５図参照
【６１ 例えば化学気相成長法を適用して多結晶シリコ
ン層５を成長させる。
第６図参照
｛７｝ 開〇３Ａ内を除く全域にフオト・レジスト膜６
を形成する。
‘８｝ 閉口３Ａ内に在る多結晶シリコン層５をパター
ニングしてシリコン・ゲート５０ｎを形成し、これをマ
スクとして絶縁膜４′のパターニングを行ないゲート絶
縁膜４Ｇｎを形成する。
‘９ー ｎ型不純物拡散を行なってソース領域７ｎ及び
ドレィン領域８ｎを形成する。尚、この場合はｎ型不純
物拡散をイオン注入に依って行なっているが、前記工程
のと本工程｛８ーとの間に於いてフオト・レジスト膜６
を例えば２０００〜５０００〔Ａ〕程度の二酸化シリコ
ン膜に鷹換えれば、通常の熱拡散も可能であり、これは
次の第７図に於けるフオト・レジスト膜１１についても
同様である。第７図参照
胤 開□３Ａをフオト・レジスト膜１１で覆い、フオト
・レジスト膜６を除去する。
（１１）通常のフオト・リングラフィ技術を適用して半
導体層３上の多結晶シリコン膜５をパターニングしてシ
リコン・ゲート５０Ｐを形成し、これをマスクにして絶
縁膜４′のパターニングを行ないゲート絶縁膜４ＧＰを
形成する。
（１２）ｐ型不純物拡散を行なってソース領域９ｐ及び
ドレィン領域１０ｐを形成する。
第８図参照
（１３）フオト．レジスト膜１ １を除去し、この後、
通常の技法に従って絶縁膜、電極、配線を形成すれば良
い。
尚、電極・配線を形成する場合、ｎチャネル・トランジ
スタ部分とｐチャネル・トランジスタ部分とを結ぶ配線
は段差を通過しなければならないが、その段差に掛る部
分を特に幅広に形成したり、ｎチャネル・トランジスタ
部分の絶縁膜を若干厚く形成して段差を小さくすること
が可能である。以上の説明で判るように、本発明の半導
体装置の製造方法に依れば、半導体基板上にェピタキシ
ャル成長させた単結晶絶縁層及び半導体層に選択的に開
□を形成し、その開口内に露出された前記半導体基板に
第１のＭＩＳトランジスタを形成し、前記半導体層には
前記半導体基板にそのままでは形成できない第２のＭＩ
Ｓトランジスタを形成するものであり、例えばＣ・ＭＩ
Ｓを製造する際、半導体基板にゥェハを作る必要がない
から装置の製造工程は簡単化され、しかも、得られた半
導体装置は、平面で見た場合、第１のＭＩＳトランジス
タと第２のＭＩＳトランジスタとが接して形成され、そ
の間に何等の余裕も必要としないから高集積化に有効で
ある。
半導体基板及び半導体層の不純物濃度は自由に選択する
ことができる。尚、前記実施例では半導体基板にｎチャ
ネル素子、半導体層にｐチャネル素子を形成したが、こ
れは逆であっても良く、また、形成する順序はどちらが
先であっても良いｏ[00] sulfuric acid, a mixture of sulfuric acid and phosphoric acid, etc. may be used. See Figure 4 '5} By selecting an appropriate technique such as a thermal oxidation method, a sputtering method, or a chemical vapor deposition method, a thickness of, for example, 300 to 1000
[A] A silicon dioxide insulating film 4' is formed. See FIG. 5 [61] Polycrystalline silicon layer 5 is grown by applying, for example, chemical vapor deposition. Refer to Fig. 6 {7} Photo resist film 6 is applied to the entire area except inside opening 3A.
form. '8} The polycrystalline silicon layer 5 present in the closed opening 3A is patterned to form a silicon gate 50n, and the insulating film 4' is patterned using this as a mask to form a gate insulating film 4Gn. '9- Diffusion of n-type impurities is performed to form source region 7n and drain region 8n. In this case, n-type impurity diffusion is performed by ion implantation, but between the above step and this step {8--, the photoresist film 6 is
For example, if the silicon dioxide film is replaced with a silicon dioxide film of about 2,000 to 5,000 [A], normal thermal diffusion is also possible, and the same applies to the photoresist film 11 shown in FIG. Refer to FIG. 7. The opening □3A is covered with a photoresist film 11, and the photoresist film 6 is removed. (11) Apply normal photolithography technology to pattern the polycrystalline silicon film 5 on the semiconductor layer 3 to form a silicon gate 50P, and use this as a mask to pattern the insulating film 4' to form the gate. An insulating film 4GP is formed. (12) Perform p-type impurity diffusion to form source region 9p and drain region 10p. See Figure 8 (13) Photo. After removing the resist film 11,
The insulating film, electrodes, and wiring may be formed using conventional techniques. When forming electrodes and wiring, the wiring that connects the n-channel transistor part and the p-channel transistor part must pass through a step, but the part that spans the step must be made especially wide, or the n-channel - It is possible to make the insulating film in the transistor part slightly thicker to reduce the step difference. As can be seen from the above explanation, according to the method for manufacturing a semiconductor device of the present invention, an opening □ is selectively formed in a single crystal insulating layer and a semiconductor layer epitaxially grown on a semiconductor substrate, and the inside of the opening □ is selectively formed. A first MIS transistor is formed on the semiconductor substrate exposed to
It forms an S transistor, for example, a C/MI
When manufacturing S, there is no need to create a wafer on the semiconductor substrate, which simplifies the manufacturing process of the device.Moreover, when viewed in plan, the resulting semiconductor device has a first MIS transistor and a second MIS transistor. Since it is formed in contact with the transistor and does not require any margin between them, it is effective for high integration. The impurity concentrations of the semiconductor substrate and semiconductor layer can be freely selected. In the above embodiments, an n-channel device is formed on the semiconductor substrate and a p-channel device is formed on the semiconductor layer, but this may be reversed, and the order in which they are formed may be formed first.
第１図乃至第８図は本発明一実施例を製造する場合の工
程説明図である。
図に於いて、１は基板、２は絶縁層、３は半導体層、４
は絶縁膜、４０ｎ，４Ｇｐはゲート絶縁膜、５Ｇｎ，５
Ｇｐはシリコン・ゲート、７ｎ，９ｐはソース領域、８
ｎ，１０ｐはドレィン領域である。
第１図
第２図
第３図
第４図
第５図
第６図
第７図
第８図FIGS. 1 to 8 are explanatory diagrams of steps in manufacturing an embodiment of the present invention. In the figure, 1 is a substrate, 2 is an insulating layer, 3 is a semiconductor layer, 4 is a
is an insulating film, 40n, 4Gp is a gate insulating film, 5Gn, 5
Gp is a silicon gate, 7n, 9p are source regions, 8
n and 10p are drain regions. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8
Claims (1)
絶縁層をエピタキシヤル成長させる工程、次いで、該単
結晶半導体層に開口を形成してから該単結晶半導体層を
マスクとして前記単結晶絶縁層を選択的に除去して前記
半導体基体の一部表面を露出する工程、次いで、該露出
された半導体基板上にゲート絶縁膜とゲート電極とを形
成した後該ゲート電極をマスクにして該半導体基板に不
純物を導入して第１のＭＩＳトランジスタを構成する不
純物領域を形成すること及び前記開口内にマスクを形成
してから前記単結晶半導体層上にゲート絶縁膜とゲート
電極とを形成した後該ゲート電極をマスクにして該単結
晶半導体層に不純物を導入して第２のＭＩＳトランジス
タを構成する不純物領域を形成することを任意の順に実
行する工程が含まれてなることを特徴とする半導体装置
の製造方法。1. A step of epitaxially growing a single crystal insulating layer on a single crystal insulating layer formed on a semiconductor substrate, then forming an opening in the single crystal semiconductor layer, and then growing the single crystal using the single crystal semiconductor layer as a mask. selectively removing the insulating layer to expose a part of the surface of the semiconductor substrate, then forming a gate insulating film and a gate electrode on the exposed semiconductor substrate, and then using the gate electrode as a mask to expose a part of the surface of the semiconductor substrate; Introducing impurities into a semiconductor substrate to form an impurity region constituting a first MIS transistor, forming a mask in the opening, and then forming a gate insulating film and a gate electrode on the single crystal semiconductor layer. The method is characterized by including a step of subsequently introducing impurities into the single crystal semiconductor layer using the gate electrode as a mask to form an impurity region constituting a second MIS transistor in any order. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53165813A JPS6015155B2 (en) | 1978-12-30 | 1978-12-30 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53165813A JPS6015155B2 (en) | 1978-12-30 | 1978-12-30 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55105361A JPS55105361A (en) | 1980-08-12 |
| JPS6015155B2 true JPS6015155B2 (en) | 1985-04-17 |
Family
ID=15819476
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53165813A Expired JPS6015155B2 (en) | 1978-12-30 | 1978-12-30 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6015155B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS577161A (en) * | 1980-06-16 | 1982-01-14 | Toshiba Corp | Mos semiconductor device |
| JPS5874083A (en) * | 1981-10-28 | 1983-05-04 | Seiko Instr & Electronics Ltd | Mis ic and manufacture thereof |
| JPS59111355A (en) * | 1982-12-17 | 1984-06-27 | Nippon Precision Saakitsutsu Kk | Semiconductor device |
| JPS6113662A (en) * | 1984-06-28 | 1986-01-21 | Nippon Telegr & Teleph Corp <Ntt> | Complementary type mis transistor device and manufacture thereof |
| JPS6239047A (en) * | 1985-08-13 | 1987-02-20 | Toppan Printing Co Ltd | Cmos integrated circuit device |
| JPS632372A (en) * | 1986-06-20 | 1988-01-07 | Nec Corp | Manufacture of complementary mos integrated circuit |
| JPH0534115Y2 (en) * | 1990-11-15 | 1993-08-30 | ||
| JP3405364B2 (en) * | 1993-03-08 | 2003-05-12 | セイコーインスツルメンツ株式会社 | Semiconductor device |
-
1978
- 1978-12-30 JP JP53165813A patent/JPS6015155B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55105361A (en) | 1980-08-12 |
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