JPS6260184A - Magnetic bubble device - Google Patents

Magnetic bubble device

Info

Publication number
JPS6260184A
JPS6260184A JP60200969A JP20096985A JPS6260184A JP S6260184 A JPS6260184 A JP S6260184A JP 60200969 A JP60200969 A JP 60200969A JP 20096985 A JP20096985 A JP 20096985A JP S6260184 A JPS6260184 A JP S6260184A
Authority
JP
Japan
Prior art keywords
connection
conductor
conductor pattern
magnetic bubble
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60200969A
Other languages
Japanese (ja)
Inventor
Toshiaki Suketa
助田 俊明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60200969A priority Critical patent/JPS6260184A/en
Publication of JPS6260184A publication Critical patent/JPS6260184A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To increase the capacity of a magnetic bubble device by laminating alternately plural conductor pattern layers and plural ceramic insulated layers and securing connection between the conductor pattern layers and securing connection between the conductor pattern layers via the conductor put into the hole drilled through the insulated layer for production of a chip mounting substrate. CONSTITUTION:A chip mounting substrate 7 contains plural conductor pattern layers 71 and ceramic insulated layers 72 laminated alternately. A window 22 where a magnetic bubble chip is attached is formed to the substrate 7 together with a groove 23 where a driving coil is wound. The layer 71 includes a terminal pattern 74 for connection with the connection terminal, a terminal pattern 75 for connection with a lead terminal set to a fixed base, a conductor pattern 76 for connection between both patterns 74 and 75, a conductor pattern 77 for connection among patterns 76, etc. Furthermore a conductor 73 set into a hole drilled through the layer 72 is used for connection in case the cubic cross is given to the congested conductor patterns via another conductor pattern or the connection is secured between the conductor patterns formed to different conductor pattern layers. Thus the capacity can be increased for a magnetic bubble device.

Description

【発明の詳細な説明】 〔概 要〕 磁気バブルデバイスの大容量化に伴ってチップと外部回
路を接続するためのリード端子や接続導体パターンの数
か増加する。一方磁気バプルデバイスに植設できるリー
ド端子の数や接続導体パターンの形成スペースには制約
がある。そこでチップ搭載基板を多層化することによっ
て増加した接続導体パターンを収納すると共に、リード
端子の共有化によって数の低減を図ったものである。
[Detailed Description of the Invention] [Summary] As the capacity of magnetic bubble devices increases, the number of lead terminals and connection conductor patterns for connecting chips and external circuits increases. On the other hand, there are restrictions on the number of lead terminals that can be implanted in a magnetic bubble device and the space for forming connection conductor patterns. Therefore, by making the chip mounting board multi-layered, an increased number of connection conductor patterns can be accommodated, and the number of connection conductor patterns can be reduced by sharing lead terminals.

〔産業上の利用分野〕[Industrial application field]

本発明は磁気バブルを制御して情報の記憶や転送を行う
磁気バブルデバイスに掛かり、特に大容量磁気バブルデ
バイスに通したチップ搭載基板の構成に関する。
The present invention relates to a magnetic bubble device that stores and transfers information by controlling magnetic bubbles, and particularly relates to the structure of a chip-mounted substrate that is passed through a large-capacity magnetic bubble device.

第3図は磁気バブルデバイスの構造を示す部分破断斜視
図、第4図は磁気バブルチップの構成を示す模式図であ
る。
FIG. 3 is a partially cutaway perspective view showing the structure of the magnetic bubble device, and FIG. 4 is a schematic diagram showing the structure of the magnetic bubble chip.

磁気バブルデバイスは第3図に示す如く磁気バブルチッ
プ1と、チップ搭載基板2とX軸方向/Y軸方向の駆動
用コイル3と、図示していない固定ベースに植設された
リード端子4と、バイアス磁界を印加するマグネット5
とシールド板6とで構成されている。
As shown in FIG. 3, the magnetic bubble device includes a magnetic bubble chip 1, a chip mounting board 2, a driving coil 3 in the X-axis direction/Y-axis direction, and a lead terminal 4 implanted in a fixed base (not shown). , a magnet 5 that applies a bias magnetic field
and a shield plate 6.

また磁気バブルチップ1には第4図の模式図に示す如(
、入力された情報を記憶する情報記憶領域と不良ループ
情報を記憶する不良データ記憶領域とが形成されている
In addition, the magnetic bubble chip 1 has a structure shown in the schematic diagram of FIG.
, an information storage area for storing input information and a defective data storage area for storing defective loop information are formed.

情報記憶領域には入力信号に基づいたバブルを発生させ
るジェネレータ11、ジェネレータ11に接続された書
込用メジャーライン12、情報を格納する多数個のマイ
ナーループ13、バブルを電気信号に変換するディテク
タ14に接続された続出用メジャーライン15、バブル
を書込用メジャーライン12からマイナーループ13に
転送するスワップゲート16、バブルをマイナーループ
13から続出用メジャーライン15に転送するレプリケ
ートゲート17等を臭えている。
The information storage area includes a generator 11 that generates bubbles based on input signals, a major writing line 12 connected to the generator 11, a large number of minor loops 13 that store information, and a detector 14 that converts bubbles into electrical signals. The major line 15 for continuous output connected to the main line 15, the swap gate 16 that transfers bubbles from the major line 12 for writing to the minor loop 13, the replicate gate 17 that transfers bubbles from the minor loop 13 to the major line 15 for continuous output, etc. There is.

一方不良データ記憶領域にも入力信号に基づいてバブル
を発生させるジェネレータ31、ジェネレータ31に接
続された書込用メジャーライン32、情報を格納するマ
イナーループ33、前記ディテクタ14に接続された続
出用メジャーライン35、バブルを書込用メジャーライ
ン32からマイナーループ33に転送するスワップゲー
ト36、パブ、ルをマイナーループ33から続出用メジ
ャーライン35に転送するレプリケートゲート37等を
具えている。
On the other hand, there is also a generator 31 that generates bubbles based on input signals in the defective data storage area, a major writing line 32 connected to the generator 31, a minor loop 33 that stores information, and a continuous output major connected to the detector 14. It includes a line 35, a swap gate 36 for transferring bubbles from the major line 32 for writing to the minor loop 33, and a replicate gate 37 for transferring bubbles from the minor loop 33 to the major line 35 for subsequent output.

上記磁気バブルチップ1においてジェネレータやディテ
クタ、スワップゲート、レプリケートゲートはそれぞれ
2 (11J以上の接続端子38を具えており、例えば
IMb相当の記憶容量を有する磁気バブルチップでは接
続端子38が20〜25個にもなる。
In the magnetic bubble chip 1, each of the generators, detectors, swap gates, and replicate gates has 2 (11 J or more) connection terminals 38. For example, a magnetic bubble chip with a storage capacity equivalent to IMb has 20 to 25 connection terminals 38. It also becomes.

更に記憶容量の大きい磁気バブルチップでは第4図の模
式図に示す規模の素子を1ブロツクとし、複数個の素子
を組合わせて所望の記憶容量を具えた磁気バブルチップ
を構成する。例えば4Mb相当の記憶容量を有するチッ
プの場合は、前述のIMb相当の記憶容量を有するチッ
プを4個並べて1個の磁気バブルチップを構成しており
接続端子の数は80〜100個にもなる。
Furthermore, in the case of a magnetic bubble chip with a large storage capacity, elements of the scale shown in the schematic diagram of FIG. 4 are used as one block, and a plurality of elements are combined to form a magnetic bubble chip with a desired storage capacity. For example, in the case of a chip with a storage capacity equivalent to 4Mb, four chips with a storage capacity equivalent to IMb described above are lined up to form one magnetic bubble chip, and the number of connection terminals is 80 to 100. .

しかし固定ベースに植設できるリード端子4の数に制約
があり、リード端子を共通化できる接続端子はチップ搭
載基板に設けた導体パターンで接続する等対策を講じる
必要がある。
However, there is a limit to the number of lead terminals 4 that can be implanted on the fixed base, and it is necessary to take measures such as connecting connection terminals that can share lead terminals with a conductor pattern provided on the chip mounting board.

〔従来の技術〕[Conventional technology]

第5図は従来のチップ搭載基板を示す斜視図である。 FIG. 5 is a perspective view showing a conventional chip mounting board.

従来の磁気バブルデバイスの記憶容量はIMb程度であ
り、第4図の模式図に示す規模の磁気バブルチップ1個
で構成されている。かかる磁気バブルデバイスでは磁気
バブルチップの接続端子の数は20〜25個であり、接
続端子とリード端子とを1:1で接続しても20〜25
の導体パターンとリード端子があればよい。したがって
チップ搭載基板2は図示の如(1枚のセラミックからな
る板21で構成され士おり、磁気バブルチップを装着す
る窓22と駆動用コイル3を巻回する溝23、およびそ
の片面もしくは両面に接続端子とリード端子とを接続す
る導体パターンが形成されている。
The storage capacity of a conventional magnetic bubble device is about IMb, and it is composed of one magnetic bubble chip of the size shown in the schematic diagram of FIG. In such a magnetic bubble device, the number of connection terminals of the magnetic bubble chip is 20 to 25, and even if the connection terminals and lead terminals are connected at a ratio of 1:1, the number of connection terminals is 20 to 25.
All you need is a conductor pattern and a lead terminal. Therefore, the chip mounting board 2 is composed of a single ceramic plate 21 as shown in the figure, and has a window 22 for mounting the magnetic bubble chip, a groove 23 for winding the drive coil 3, and one or both sides thereof. A conductor pattern is formed to connect the connection terminal and the lead terminal.

(発明が解決しようとする問題点〕 磁気バブルデバイスの大容量化に伴ってチップの接続端
子が増加し、チップの接続端子と外部回路を接続するた
めのリード端子や接続導体パターンの数が増加する。し
かもリード端子を共通化できる接続端子の間をチップ搭
載基板に設けた導体パターンで接続するには随所で導体
パターンを立体交叉させる必要がある。しかし従来のチ
ップ搭載基板では導体パターンの形成スペースに制約が
あって上記要求を十分に充たすことができないという問
題があった。
(Problem to be solved by the invention) As the capacity of magnetic bubble devices increases, the number of connection terminals on the chip increases, and the number of lead terminals and connection conductor patterns for connecting the connection terminals on the chip and external circuits increases. In addition, in order to connect connecting terminals that can share lead terminals using conductor patterns provided on the chip mounting board, it is necessary to intersect the conductor patterns three-dimensionally at various places.However, with conventional chip mounting boards, the formation of the conductor pattern is difficult. There was a problem in that space was limited and the above requirements could not be fully met.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

第1図は本発明になるチップ搭載基板の一実施例を示す
図で、第1図(alは層構成を示す斜視図、第1図(b
lは導体パターン間の接続を示す断面図である。
FIG. 1 is a diagram showing an embodiment of a chip mounting board according to the present invention, FIG. 1 (al is a perspective view showing the layer structure, FIG.
1 is a cross-sectional view showing connections between conductor patterns.

上記問題点は第1図に示す複数の導体パターン層71と
複数のセラミックからなる絶縁rf472を交互に積層
し、且つ絶縁層72を貢通ずる孔の内部に設けた導体7
3を介して、導体パターン層71間の電気的接続を行っ
てなる多層基板を、チップ搭載基板として用いてなる本
発明の磁気バブルデバイスによって解決される。
The above-mentioned problem arises when the conductor 7 shown in FIG.
This problem is solved by the magnetic bubble device of the present invention, which uses a multilayer substrate formed by electrically connecting the conductor pattern layers 71 through the conductor pattern layer 71 as the chip mounting substrate.

〔作用〕[Effect]

第1図において絶縁層72でそれぞれ絶縁された複数の
導体パターンN71と、絶縁層72を貫通する孔に設け
た導体73とで構成されたチップ搭載基板は、導体パタ
ーンの収納スペースが増大すると共に導体パターンの立
体交叉を可能にする。即ち磁気バブルデバイスの大容量
化によって増加した導体パターンを収納し、且つリード
端子を共通化できる接続端子はチップ搭載基板に設けた
導体パターンで接続する等、磁気バブルデバイスを大容
量化するための対策を講じることができる。
In FIG. 1, the chip mounting board is composed of a plurality of conductor patterns N71 each insulated by an insulating layer 72 and a conductor 73 provided in a hole penetrating the insulating layer 72. Enables three-dimensional crossover of conductor patterns. In other words, in order to increase the capacity of magnetic bubble devices, the number of conductor patterns that have increased due to the increase in capacity of magnetic bubble devices can be accommodated, and connection terminals that can share lead terminals can be connected using conductor patterns provided on the chip mounting board. Countermeasures can be taken.

〔実施例〕〔Example〕

以下添付図により本発明の実施例について説明する。な
お第2図は導体パターン層の構成例を示す平面図である
Embodiments of the present invention will be described below with reference to the accompanying drawings. Note that FIG. 2 is a plan view showing an example of the structure of the conductor pattern layer.

図においてチップ搭載基板7は複数の導体パターン層7
1と、複数のセラミックからなる絶縁層72を交互にH
imすることによって構成されており、磁気バブルチッ
プを装着する窓22と駆動用コイル3を巻回する溝23
が設けられている。
In the figure, a chip mounting board 7 has a plurality of conductor pattern layers 7.
1 and an insulating layer 72 made of a plurality of ceramics are alternately
im, and includes a window 22 for mounting the magnetic bubble chip and a groove 23 for winding the drive coil 3.
is provided.

導体パターン層71には第2図に示す如く磁気バブルチ
ップの接続端子と接続するための端子パターン74、固
定ベースに植設されたリード端子4と接続するための端
子パターン75、端子パターン74と端子パターン75
との間を接続する導体パターン76、複数個の導体パタ
ーン76の間を接続するための導体パターン77等が形
成されている。また図示していないが導体パターン層の
干渉を防止するためのシールド層や接地層も形成されて
いる。
As shown in FIG. 2, the conductive pattern layer 71 has a terminal pattern 74 for connecting to the connecting terminal of the magnetic bubble chip, a terminal pattern 75 for connecting to the lead terminal 4 implanted in the fixed base, and a terminal pattern 74. Terminal pattern 75
A conductor pattern 76 for connecting between the conductor patterns 76 and a conductor pattern 77 for connecting between the plurality of conductor patterns 76 and the like are formed. Although not shown, a shield layer and a ground layer are also formed to prevent interference with the conductor pattern layer.

更に輻轢した導体パターンを他の導体パターン層を利用
して立体交叉させる場合や、異なる導体パターン層に形
成された導体パターン間を接続する場合は、第1図(b
)に示す如く絶縁rf472を貫通する孔の内部に設け
た導体73を介して接続している。
Furthermore, when the overlapping conductor patterns are made to intersect three-dimensionally using another conductor pattern layer, or when connecting conductor patterns formed on different conductor pattern layers, the method shown in Fig. 1 (b)
), the connection is made via a conductor 73 provided inside a hole penetrating the insulating rf472.

チップ搭載基板7をかかる多層基板で構成するコトニよ
り、導体パターンの収納スペースを増大させると共に導
体パターンの立体交叉を可能にする。即ち磁気バブルデ
バイスの大容量化によって増加した導体パターンを収納
し、リード端子を共通化できる接続端子はチ・ノブ搭載
基板に設けた導体パターンで接続する等、磁気バブルデ
バイスを大容量化するための対策を講じ、例えば4Mb
相当の記憶容量を有する磁気バブルデバイスでリード端
子の数を36個まで減少させることができる。
By constructing the chip mounting board 7 from such a multilayer board, the storage space for the conductor patterns is increased and the conductor patterns can be intersected three-dimensionally. In other words, in order to increase the capacity of the magnetic bubble device, it is possible to accommodate the conductor pattern that has increased due to the increase in the capacity of the magnetic bubble device, and to connect the connection terminal that can share the lead terminal with the conductor pattern provided on the chip/knob mounting board. For example, 4Mb
The number of lead terminals can be reduced to 36 in a magnetic bubble device with significant storage capacity.

〔発明の効果〕〔Effect of the invention〕

、ヒ述の如(本発明によれば大容量磁気バブルデバイス
に適したチップ搭載基板を提供することができる。
, as mentioned above (according to the present invention, a chip mounting board suitable for a large capacity magnetic bubble device can be provided).

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明になるチップ搭載基板の一実施例を示す
図で、 第1図fatは層構成を示す斜視図、 第1図(b)は導体パターン間の接続を示す断面図、第
2図は導体パターン層の構成例を示す平面図、第3図は
磁気バブルデバイスの構造を示す部分破断斜視図、 第4図は磁気バブルチップの構成を示す模式図、第5図
は従来のチップ搭載基板を示す斜視図、である。図にお
いて 7はチップ搭載基板、 22はチップ装着窓、23はコ
イル巻回溝、  71は導体パターン層、72は絶縁層
、     73は導体、74.75は端子パターン、
76.77は導体パターン、をそれぞれ表す。
FIG. 1 is a diagram showing one embodiment of a chip mounting board according to the present invention, FIG. 1 (fat) is a perspective view showing the layer structure, FIG. Fig. 2 is a plan view showing an example of the structure of the conductor pattern layer, Fig. 3 is a partially cutaway perspective view showing the structure of a magnetic bubble device, Fig. 4 is a schematic diagram showing the structure of a magnetic bubble chip, and Fig. 5 is a conventional structure. FIG. 3 is a perspective view showing a chip mounting board. In the figure, 7 is a chip mounting board, 22 is a chip mounting window, 23 is a coil winding groove, 71 is a conductor pattern layer, 72 is an insulating layer, 73 is a conductor, 74.75 is a terminal pattern,
76 and 77 represent conductor patterns, respectively.

Claims (1)

【特許請求の範囲】 複数の導体パターン層(71)と複数のセラミックから
なる絶縁層(72)を交互に積層し、 且つ該絶縁層(72)を貫通する孔の内部に設けた導体
(73)を介して、該導体パターン層(71)間の電気
的接続を行ってなる多層基板を、 チップ搭載基板として用いてなることを特徴とする磁気
バブルデバイス。
[Claims] A plurality of conductor pattern layers (71) and a plurality of insulating layers (72) made of ceramic are alternately laminated, and a conductor (73) is provided inside a hole penetrating the insulating layer (72). 1. A magnetic bubble device characterized in that a multilayer substrate formed by electrically connecting the conductive pattern layers (71) through a chip mounting substrate is used as a chip mounting substrate.
JP60200969A 1985-09-11 1985-09-11 Magnetic bubble device Pending JPS6260184A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60200969A JPS6260184A (en) 1985-09-11 1985-09-11 Magnetic bubble device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60200969A JPS6260184A (en) 1985-09-11 1985-09-11 Magnetic bubble device

Publications (1)

Publication Number Publication Date
JPS6260184A true JPS6260184A (en) 1987-03-16

Family

ID=16433328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60200969A Pending JPS6260184A (en) 1985-09-11 1985-09-11 Magnetic bubble device

Country Status (1)

Country Link
JP (1) JPS6260184A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816552A (en) * 1981-07-22 1983-01-31 Fujitsu Ltd Package for semiconductor element
JPS60163294A (en) * 1984-02-03 1985-08-26 Nec Corp Substrate for mounting magnetic bubble memory chip

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816552A (en) * 1981-07-22 1983-01-31 Fujitsu Ltd Package for semiconductor element
JPS60163294A (en) * 1984-02-03 1985-08-26 Nec Corp Substrate for mounting magnetic bubble memory chip

Similar Documents

Publication Publication Date Title
US2907925A (en) Printed circuit techniques
CN1728918B (en) Circuitized substrate
US3746934A (en) Stack arrangement of semiconductor chips
US5036431A (en) Package for surface mounted components
JPS63249394A (en) Multilayer circuit board
JP3562568B2 (en) Multilayer wiring board
JP2513443B2 (en) Multilayer circuit board assembly
JPH09205283A (en) Semiconductor module and memory module
JPS6318697A (en) Multilayer interconnection board
JPS6260184A (en) Magnetic bubble device
US3157857A (en) Printed memory circuit
JPS5836512B2 (en) Multi-chip wiring with terminal surface arrangement for connecting semiconductor memory chips
JPH11251516A (en) Semiconductor module
JP3554885B2 (en) Wiring board
JPH06152137A (en) Multilayer printed circuit board structure
JPH01175296A (en) Multilayer printed circuit board device
JPH08241935A (en) Multilayer circuit board
JPH04373157A (en) Hybrid ic
JPS60127797A (en) Multilayer printed circuit board
JP2608915B2 (en) IC mounting equipment
JPH0526785Y2 (en)
JPS63136694A (en) Multilayer interconnection board
JPS634694A (en) Multilayer printed board
JP2664720B2 (en) IC mounting equipment
JPS609191A (en) Method of forming printed board pattern