JPS60163294A - Substrate for mounting magnetic bubble memory chip - Google Patents

Substrate for mounting magnetic bubble memory chip

Info

Publication number
JPS60163294A
JPS60163294A JP59017736A JP1773684A JPS60163294A JP S60163294 A JPS60163294 A JP S60163294A JP 59017736 A JP59017736 A JP 59017736A JP 1773684 A JP1773684 A JP 1773684A JP S60163294 A JPS60163294 A JP S60163294A
Authority
JP
Japan
Prior art keywords
magnetic bubble
wiring
bubble memory
memory chip
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59017736A
Other languages
Japanese (ja)
Inventor
Seiichi Suga
菅 誠一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59017736A priority Critical patent/JPS60163294A/en
Publication of JPS60163294A publication Critical patent/JPS60163294A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To reduce electrostatic induced noise and to improve sensing characteristics by forming an earthed wiring pattern between wiring patterns connected to a current loop type stretcher and wiring patterns connected to detectors. CONSTITUTION:The stretcher wiring patterns 6a, 6b and sense signal wiring patterns 8a-8c are connected to the current loop type stretcher 7 and the detectors 9a, 9b respectively through bonding wires. The earthed wiring pattern 11 is inserted between the patterns 6a, 6b and 8a-8c. Thus, almost all stray capacity between the patterns 6a, 6b and 8a-8b is closed between the patterns 6a, 6b and 11 and the stray capacity contributing to induction from the patterns 6a, 6b to 8a-8c is extremely reduced.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は磁気バブルセンス信号用配線バタンに誘導する
ノイズを減少させた磁気バブルメモリチ、プ搭載用基板
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a substrate for mounting a magnetic bubble memory chip that reduces noise induced in a wiring button for a magnetic bubble sense signal.

(従来技術) 磁気バブルメモリチップ搭載用基板は磁気バブルメモリ
デバイスの部品として使用されるものであシ、磁気バブ
ルメモリチップと外部回路を電気的に接続するために用
いられる。磁気バブルメモリデバイスはこの他に磁気バ
ブルメモリチップと、このチップに水平な回転磁界を供
給するコイル及び垂直なバイアス磁界を発生する磁石等
から構成されている。
(Prior Art) A magnetic bubble memory chip mounting board is used as a component of a magnetic bubble memory device, and is used to electrically connect the magnetic bubble memory chip and an external circuit. The magnetic bubble memory device also includes a magnetic bubble memory chip, a coil that supplies a horizontal rotating magnetic field to the chip, a magnet that generates a vertical bias magnetic field, and the like.

第1図は従来の磁気バブルメモリチップ搭載用基板の一
例を説明するための斜視図である。磁気バブルメモリチ
ップ搭載用基板1はセラミックなどでつくられた絶縁基
板で、この基板1のほぼ中央には凹状の溝(磁気バブル
メモリチップ搭載部2)ガ形成されている。磁気バブル
メモリチップは該塔載部2に配置され、ボンディングワ
イヤ5と基板lの表面および内部の配線バタン3とを介
して、基板lの端部に形成された端子4と電気的に接続
される。
FIG. 1 is a perspective view for explaining an example of a conventional magnetic bubble memory chip mounting board. The magnetic bubble memory chip mounting substrate 1 is an insulating substrate made of ceramic or the like, and a concave groove (magnetic bubble memory chip mounting portion 2) is formed approximately in the center of the substrate 1. The magnetic bubble memory chip is placed on the mounting part 2 and is electrically connected to a terminal 4 formed at the end of the substrate l via a bonding wire 5 and a wiring button 3 on the surface and inside of the substrate l. Ru.

第2図は第1図に示した磁気バブルメモリチ。Figure 2 shows the magnetic bubble memory chip shown in Figure 1.

プ搭載基板(チップ塔載済)の部分拡大図である。FIG. 2 is a partially enlarged view of a chip-mounted board (on which a chip is mounted).

第2図において、基板1上の配線バタン6a、6bハ磁
気バブルメモリチ、プの電流ループ型ストレ、チャフに
ボンディングワイヤ5によυ、接続している。また、配
線バタン8a、8b、8eは磁気バブルメモリチップ2
のディテクタ9a、9bに接続されている。なお、配線
バタン6aの破線部分は実線部分と異なった配線バタン
層にあシ、実線部分とはスルーホールを介して結線され
ている部分である。
In FIG. 2, the wiring tabs 6a and 6b on the substrate 1 are connected to the current loop type strain and chaff of the magnetic bubble memory chip by bonding wires 5. Further, the wiring buttons 8a, 8b, 8e are connected to the magnetic bubble memory chip 2.
are connected to detectors 9a and 9b. Note that the broken line portion of the wiring batten 6a is located in a different wiring batten layer from the solid line portion, and is connected to the solid line portion via a through hole.

しかし、第2図のような配線バタンであると、ストレッ
チャ用配線バタン6m、6bとセンス信号用配線バタン
8aと8Cの間に浮遊容量10m、10b。
However, with the wiring tabs as shown in FIG. 2, there are stray capacitances of 10 m, 10b between the stretcher wiring tabs 6m, 6b and the sense signal wiring tabs 8a, 8C.

10e、10dが存在する。このためストレッチャ用配
線バタン6m、6bとセンス信号用配−線バタン−8m
、8eの間に静電結合が生じ、ストレッチャ用配線バタ
ン6a、6bの電位変動に従って、センス信号用配線バ
タン8a、8・の電位が変動してしまう。この電位変動
はストレアチャフにストレッチ電流パルスを印加したと
きの電圧降下によって起こる。このストレッチ電流パル
スのタイミングが磁気バブルセンス信号の検出タイミン
グと一致していることと、センスアンプとして差動アン
プを使用しておシ、この誘導が差動的であることからセ
ンス特性が態化する欠点があった3゜(発明の目的) 本発明の目的はこのような従来の欠点を除去するため静
電誘導ノイズの少ない磁気バブルメモリ搭載用基板を提
供すること匝ある。
10e and 10d exist. For this purpose, stretcher wiring buttons 6m and 6b and sense signal wiring buttons 8m
, 8e, and the potential of the sense signal wiring buttons 8a, 8. fluctuates in accordance with the potential fluctuation of the stretcher wiring buttons 6a, 6b. This potential fluctuation is caused by a voltage drop when a stretching current pulse is applied to the strech chaff. The timing of this stretch current pulse coincides with the detection timing of the magnetic bubble sense signal, and since a differential amplifier is used as the sense amplifier, the sense characteristics are changed because this induction is differential. (Objective of the Invention) An object of the present invention is to provide a substrate for mounting a magnetic bubble memory with less electrostatic induction noise in order to eliminate such conventional drawbacks.

(発明の構成) 本発明によれば、電流ループ型ストレッチャで磁気バブ
ルを伸張し、前記磁気バブルを構出するディテクタを持
つ磁気バブルメモリチップを搭載する塔載部と該磁気バ
ブルメモリチップと外部回路を電気的に結線するための
配線バタンとを少なくとも有する磁気バブルメモリチッ
プ搭載用基板において、前記電流ループ型ストレ、チ々
に結線される前記配線バタンと前記ディテクタに結線さ
れる前記配線バタンの間に静電誘導ノイズ除去用の接地
配線バタンか設けられていることを特徴とする磁気バブ
ルメモリチャフ搭載用基板が得られる。
(Structure of the Invention) According to the present invention, there is provided a tower mounting part on which a magnetic bubble memory chip having a detector for stretching a magnetic bubble and configuring the magnetic bubble with a current loop type stretcher is mounted, and the magnetic bubble memory chip and an external part. In a magnetic bubble memory chip mounting board having at least wiring tabs for electrically connecting a circuit, the current loop type strain is formed between the wiring tabs that are connected to each other and the wiring tabs that are connected to the detector. A substrate for mounting a magnetic bubble memory chaff is obtained, which is characterized in that a ground wiring button for removing electrostatic induction noise is provided in between.

(実施例) 以下本発明について実施例を示す図面を参照して説明す
る。
(Example) The present invention will be described below with reference to drawings showing examples.

第3図はチャフが塔載された磁気バブルメモリチャフ搭
載用基板の一実施例を示す部分拡大図である。ストレッ
チャ用配線バタン6m、6bとセンス信号用配線バタン
8m、8b、8cは第2図と同様に電流ループ型ストレ
ッチャ7とディテクタ9m。
FIG. 3 is a partially enlarged view showing an embodiment of a magnetic bubble memory chaff mounting substrate on which a chaff is mounted. The stretcher wiring buttons 6m, 6b and the sense signal wiring buttons 8m, 8b, 8c are the current loop type stretcher 7 and the detector 9m as in FIG.

9bにそれぞれポンディングワイヤ5を介して接続され
ている。ただし、接地配線バタン11がストレッチャ用
配線バタン6m、6bとセンス信号用配線バタン8m、
8b、8cの間に挿入されている。
9b via bonding wires 5, respectively. However, the ground wiring button 11 is the stretcher wiring button 6m, 6b and the sense signal wiring button 8m,
It is inserted between 8b and 8c.

なお、接地配線パタン11の一点鎖線部分はストレッチ
ャ用配線バタン6mの点線部分が位置する層と実線の配
線バタン層の中間に位置している。
Note that the dot-dashed line portion of the ground wiring pattern 11 is located between the layer in which the dotted line portion of the stretcher wiring button 6m is located and the wiring button layer indicated by the solid line.

このように接地配線バタン11をストレッチャ用配線バ
タン6m、6bとセンス信号用配線バタン8m、8b、
8eの間に設置することで、第2図のストレッチャ用配
線バタン6m、6bと、センス信号用配線パp :/ 
g m 、 8 cの間の浮遊容jiloa、10b。
In this way, the ground wiring button 11 is connected to the stretcher wiring button 6m, 6b, the sense signal wiring button 8m, 8b,
By installing it between the stretcher wiring buttons 6m and 6b in Figure 2 and the sense signal wiring pad p:/
Floating volume between g m, 8 c jiloa, 10b.

10c、10dのほとんどはストレッチャ用配線バタン
6m、6bと接地配線バタン110間でクローズするの
で、ストレッチャ用配線バタン6m、6bからセンス信
号用配線バタン8m、8eへの誘導に寄与する浮遊容量
は非常に小さくできる。その結果、センス信号用配線バ
タン81! + 8 b H8cへの誘導ノイズは激減
した。
10c and 10d are mostly closed between the stretcher wiring tabs 6m and 6b and the ground wiring tab 110, so the stray capacitance that contributes to the induction from the stretcher wiring tabs 6m and 6b to the sense signal wiring tabs 8m and 8e is extremely small. It can be made smaller. As a result, the sense signal wiring button 81! + 8 b The induced noise to H8c was drastically reduced.

(発明の効果) 以上説明したように本発明によれば、従来の磁気バブル
メモリチップ搭載用基板の欠点を容易に解決でき、セン
ス特性が良く、信頼性の高い磁気バブルメモリチップ搭
載用基板が得られた。
(Effects of the Invention) As explained above, according to the present invention, the drawbacks of the conventional magnetic bubble memory chip mounting board can be easily solved, and a magnetic bubble memory chip mounting board with good sense characteristics and high reliability is provided. Obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の磁気バブルメモリチャフ搭載用基板の外
観斜視図、第2図は従来の磁気パブルメモリチ、ブ搭載
用基板の部分拡大図、第3図は本発明の一実施例を説明
するための図である。 1・・・磁気バブルメモリチ、ブ搭載用基板。 2・・・磁気バブルメモリチップ塔載部。 3・・・配線バタン、4・・・端子。 5・・・ボンディングワイヤ。 6a、6b・・・ストレッチャ用配線バタン。 7・・・ストレッチャ。 8a、8b、8c・・・センス信号用配線バタン。 9a、9b・・・ディテクタ。 10m、10b、10c、10d 浮遊接散。 11・・・接地用配線バタン。 第2図 第3図 手続補正書(自発) 60.4.24 許庁長宮 殿 事件の表示 昭和59年 特杵 願第017736号]
明の名称 磁気バブルメモリチップ搭載用基板車止をす
る者 事件との関係 出 願 人 東京都港区芝五丁目33番1号 (423) 日本電気株式会社 代表者 関本忠弘 (埋入 〒108 東京都港区芝/i丁[137番8号 住友三
l]ビル日本電気株式会社内 (6591) 弁理士 内 原 晋 電話 東京(03)456−3111(大代表)& 補
正の対象 明細書の発明の詳細な説明の欄 図面の簡単な説明の欄 6、補正の内容 (1)明細書第2頁第16〜17行目に「(磁気バブル
メモリチップ搭載部2)が〜」とあるのを[(磁気バブ
ルメモリチップ搭載部)が〜」と補正する。 (2)明細書第2頁第17〜18行目に「磁気バブルメ
モリチップは該搭載部2に〜」とあるのを「磁気バブル
メモリチップ2は前記搭載部に〜」と補正する。 (3)明細書第7頁第4行目に[2磁気バブルメモリチ
ップ搭載部、」とあるのを「2・・・磁気バブルメモリ
チップ、」と補正する。
Fig. 1 is an external perspective view of a conventional magnetic bubble memory chaff mounting board, Fig. 2 is a partially enlarged view of a conventional magnetic bubble memory chaff mounting board, and Fig. 3 is for explaining an embodiment of the present invention. This is a diagram. 1... Magnetic bubble memory chip, board for mounting. 2...Magnetic bubble memory chip tower mounting part. 3... Wiring button, 4... Terminal. 5...Bonding wire. 6a, 6b... Wiring buttons for stretcher. 7...Stretcher. 8a, 8b, 8c...Wiring buttons for sense signals. 9a, 9b...detector. 10m, 10b, 10c, 10d Floating scattering. 11... Grounding wiring button. Figure 2 Figure 3 Procedural Amendment (Voluntary) 60.4.24 Indication of the Office Commissioner's Palace Case 1981 Special Pestle Application No. 017736]
Name of Akira: Relationship with the incident involving a person who stopped a vehicle with a magnetic bubble memory chip mounting board Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) Representative of NEC Corporation: Tadahiro Sekimoto (embedded address: 108 Tokyo) Shiba/i-cho [137-8 Sumitomo 3L] Building, NEC Corporation (6591) Patent attorney Susumu Uchihara Telephone Tokyo (03) 456-3111 (main representative) & Invention of the specification subject to amendment Detailed explanation column Brief explanation of drawings column 6, contents of amendment (1) The statement "(Magnetic bubble memory chip mounting part 2) is..." on page 2, lines 16-17 of the specification. [(Magnetic bubble memory chip mounting portion) is...”. (2) On page 2, lines 17-18 of the specification, “The magnetic bubble memory chip is mounted on the mounting portion 2” is corrected to “Magnetic bubble memory chip mounting portion 2 is...”. Bubble memory chip 2 is placed in the mounting portion.” (3) In the fourth line of page 7 of the specification, “2 magnetic bubble memory chip mounting portion,” is replaced with “2...magnetic bubble memory.” "Chip," he corrected.

Claims (1)

【特許請求の範囲】[Claims] 電流ループ型ストレッチキで磁気バブルを伸張し、前記
磁気バブルを検出するディテクタを持つ磁気バブルメモ
リチップを搭載する塔載部と、該磁気バブルメモリチッ
プと外部回路を電気的に結線するための配線パタ/とを
有する磁気バブルメモリテップ搭載用基板において、前
記電流ループ型ストレッチャに結線される配線バタンと
前記ディテクタに結線される配線バタンの間に接地配線
バタンか設けられていることを特徴とする磁気バブルメ
モリチップ搭載用基板。
A tower mounting part on which a magnetic bubble memory chip is mounted, which extends a magnetic bubble using a current loop type stretch key and has a detector for detecting the magnetic bubble, and wiring for electrically connecting the magnetic bubble memory chip to an external circuit. In the substrate for mounting a magnetic bubble memory chip having a pattern, a ground wiring button is provided between the wiring button connected to the current loop type stretcher and the wiring button connected to the detector. Substrate for mounting magnetic bubble memory chips.
JP59017736A 1984-02-03 1984-02-03 Substrate for mounting magnetic bubble memory chip Pending JPS60163294A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59017736A JPS60163294A (en) 1984-02-03 1984-02-03 Substrate for mounting magnetic bubble memory chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59017736A JPS60163294A (en) 1984-02-03 1984-02-03 Substrate for mounting magnetic bubble memory chip

Publications (1)

Publication Number Publication Date
JPS60163294A true JPS60163294A (en) 1985-08-26

Family

ID=11952027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59017736A Pending JPS60163294A (en) 1984-02-03 1984-02-03 Substrate for mounting magnetic bubble memory chip

Country Status (1)

Country Link
JP (1) JPS60163294A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6260184A (en) * 1985-09-11 1987-03-16 Fujitsu Ltd Magnetic bubble device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6260184A (en) * 1985-09-11 1987-03-16 Fujitsu Ltd Magnetic bubble device

Similar Documents

Publication Publication Date Title
JPS6352781B2 (en)
US4534105A (en) Method for grounding a pellet support pad in an integrated circuit device
KR100487038B1 (en) Semiconductor device
US20040222487A1 (en) Semiconductor device having a shielding layer
WO1996029737A1 (en) A high density integrated circuit assembly combining leadframe leads with conductive traces
JPS60163294A (en) Substrate for mounting magnetic bubble memory chip
US6924537B2 (en) Semiconductor device including a potential drawing portion formed at a corner
JPH0547943A (en) Semiconductor integrated device
US6417560B1 (en) Semiconductor device
KR100285404B1 (en) Semiconductor devices
JPH05243472A (en) Semiconductor integrated circuit
JP2500310B2 (en) Semiconductor device
JPS629654A (en) Mounting package for ic device
JP2778235B2 (en) Semiconductor device
SE515180C2 (en) Device for electromagnetic compatibility (EMC) protection of hybrid components
JPS60165752A (en) Semiconductor integrated circuit
JPS5951748B2 (en) semiconductor equipment
JPH05145021A (en) Integrated circuit device
JPS61119061A (en) Semiconductor integrated circuit device
JPH07106524A (en) Semiconductor integrated circuit device
JP3302810B2 (en) Semiconductor device
JPS5819030A (en) Optical coupling semiconductor device
JPH05315626A (en) Semiconductor device
JPS63133652A (en) Structure and method for suppressing electric interference caused by capacitive coupling
JPH0712118B2 (en) How to prevent the generation of noise in electronic circuits