JPS6259479B2 - - Google Patents
Info
- Publication number
- JPS6259479B2 JPS6259479B2 JP2168479A JP2168479A JPS6259479B2 JP S6259479 B2 JPS6259479 B2 JP S6259479B2 JP 2168479 A JP2168479 A JP 2168479A JP 2168479 A JP2168479 A JP 2168479A JP S6259479 B2 JPS6259479 B2 JP S6259479B2
- Authority
- JP
- Japan
- Prior art keywords
- cut
- parallel lines
- wiring
- printed
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000919 ceramic Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 8
- 239000003292 glue Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000010304 firing Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 24
- 238000000034 method Methods 0.000 description 9
- 239000000843 powder Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 5
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- DOIRQSBPFJWKBE-UHFFFAOYSA-N dibutyl phthalate Chemical compound CCCCOC(=O)C1=CC=CC=C1C(=O)OCCCC DOIRQSBPFJWKBE-UHFFFAOYSA-N 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- OAYXUHPQHDHDDZ-UHFFFAOYSA-N 2-(2-butoxyethoxy)ethanol Chemical compound CCCCOCCOCCO OAYXUHPQHDHDDZ-UHFFFAOYSA-N 0.000 description 1
- ODINCKMPIJJUCX-UHFFFAOYSA-N Calcium oxide Chemical compound [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 description 1
- 239000001856 Ethyl cellulose Substances 0.000 description 1
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical compound CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 but in this case Substances 0.000 description 1
- 239000000292 calcium oxide Substances 0.000 description 1
- 235000012255 calcium oxide Nutrition 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920001249 ethyl cellulose Polymers 0.000 description 1
- 235000019325 ethyl cellulose Nutrition 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- 239000011812 mixed powder Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004014 plasticizer Substances 0.000 description 1
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
本発明は配線密度をあげた多層セラミツク基板
の製造法に係り、更に詳しくは、スルーホールを
設け金属粉末ペーストを充填して導通をとり、各
配線を印刷するよりも更に密度を高め工程を略簡
した高密度配線を有する多層セラミツク基板を容
易に製造する製造法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer ceramic substrate with increased wiring density. The present invention also relates to a manufacturing method for easily manufacturing a multilayer ceramic substrate having high-density wiring with increased density and simplified steps.
最近回路配線をもつセラミツク基板は表面層の
みならず、中間層にも回路配線をもつた多層セラ
ミツク基板が多く使用されるようになつてきた。 Recently, multilayer ceramic substrates having circuit wiring not only on the surface layer but also on the intermediate layer have come to be widely used.
このような多層配線セラミツク基板に於いては
各配線層間の導通をとることが必要となるが、こ
の場合未焼成セラミツク板に孔、所謂スルーホー
ルを明け、その孔に金属粉末、バインダー、有機
溶剤等を混合したペーストを充填することが行わ
れている。 In such a multilayer wiring ceramic board, it is necessary to establish conduction between each wiring layer, but in this case, holes, so-called through holes, are made in the unfired ceramic board, and metal powder, binder, and organic solvent are injected into the holes. Filling with a paste made of a mixture of
しかし今日では基板を小型化し配線密度をあげ
る方向に進んでおりそのために各スルーホールの
間隔寸法が極端に接近し、又スルーホール径を小
さくする必要にせまられている。 However, today, the trend is toward downsizing substrates and increasing wiring density, and as a result, the spacing between through holes has become extremely close, and it has become necessary to reduce the diameter of the through holes.
現在スルーホールを設け、金属粉末のペースト
をスクリーンマスクにて充填する技術では一般的
にスルーホール径が0.3mm以上必要であり、それ
以下であると金属粉末ペーストの圧入が困難であ
り、導通不良が発生する。又各スルーホールの間
隔寸法0.6mmはスルーホール径0.3mmを穿設するの
に必要な寸法であり、それ以下であると穿設が出
来難く、孔間にき裂やヒビの発生が起り、表面に
凸凹の起状が生じ、配線印刷が出来難くなる。こ
の様な欠点を解消するために各層の配線との導通
を形成するのにメタライズペーストによる平行な
印刷線を設け、それらを積層し接着して、次に印
刷線に対して直角に切断し、該切断面を主表面と
し、かつ印刷線切口部を導通口とする方法が同一
出願人により昭和54年２月２日に出願済である。 Current technology that creates through holes and fills them with metal powder paste using a screen mask generally requires a through hole diameter of 0.3 mm or more, and if it is smaller than that, it is difficult to press-fit the metal powder paste, resulting in poor conductivity. occurs. Also, the spacing between each through hole of 0.6 mm is the required dimension to drill a through hole with a diameter of 0.3 mm, and if it is less than that, it will be difficult to drill and cracks will occur between the holes. Unevenness occurs on the surface, making it difficult to print wiring. In order to solve this problem, parallel printed lines made of metallized paste are provided to form electrical continuity with the wiring in each layer, these are laminated and glued together, and then cut at right angles to the printed lines. The same applicant filed an application on February 2, 1974 for a method in which the cut surface is used as the main surface and the cut portion of the printed line is used as the through hole.
この方法により導通が形成されたものは次の工
程である各層の配線回路を印刷しなければならな
い。配線の密度を高め、積層にする枚数を増せば
増す程、配線回路を印刷する経費と手間が嵩むこ
とになり、また導通位置に対して配線回路の印刷
との位置合せが小さくなれば、なる程難かしく、
結線不良による断線等の支障を招来する。 If conduction is established using this method, the next step is to print wiring circuits for each layer. As the wiring density increases and the number of layers increases, the cost and effort to print the wiring circuit increases, and the smaller the alignment of the wiring circuit printed with the conduction position, the more Moderately difficult,
This may lead to problems such as disconnection due to poor wiring.
このような以上の欠点を解消するために導通を
とると同時に配線回路も共に印刷形成する方法を
採用したもので、各層の配線との導通をとつた多
層配線セラミツク基板の製造法に於いて、未焼成
セラミツク板にメタライズペーストによる縦の平
行線と該平行線に直線に交る横の平行線を印刷し
て設け、それらの印刷線が同一方向になるように
未焼成セラミツク板を積層し、接着して、次に横
の平行線上の中央部と平行線間の中央部から縦の
平行線に垂直に切断して、印刷線上の切断面を回
路配線とした主表面とし、切断両面の印刷線切口
部を導通口とし、これらと同様にして、積層する
２層目、３層目を製作し、それらを積層、接着し
て非酸化性雰囲気中で焼成することを特徴とする
高密度多層配線セラミツク基板の製造法を提供す
るものである。即ちより集積密度を高めると各層
の導通をとる経路も多くなり各層の配線回路も小
さい面積内に形成されるため直線的となる。本発
明はこのような点を考慮して製作されたものであ
り、図面により説明すると、第１図は従来方法に
てスルーホールを設け金属粉末ペーストを充填し
て導通を製作した斜視図であり、図中１は未焼成
セラミツクシート、２はスルーホールを設け金属
粉末ペーストを充填した導通口、３は位置を決め
るための孔である。 In order to eliminate the above-mentioned drawbacks, we have adopted a method of printing and forming the wiring circuit at the same time as establishing conduction.In the method of manufacturing a multilayer wiring ceramic substrate that establishes conduction with the wiring of each layer, Vertical parallel lines made of metallized paste and horizontal parallel lines that cross the parallel lines in a straight line are printed on green ceramic plates, and the green ceramic plates are stacked so that the printed lines are in the same direction. Glue and then cut perpendicularly to the vertical parallel line from the center on the horizontal parallel line and the center between the parallel lines, and use the cut surface on the printed line as the main surface of the circuit wiring, and print on both sides of the cut. A high-density multilayer, characterized in that the line cut portion is used as a conduction port, and the second and third layers to be laminated are manufactured in the same manner as these, and the layers are laminated, bonded, and fired in a non-oxidizing atmosphere. A method of manufacturing a wiring ceramic substrate is provided. That is, as the integration density is increased, the number of conductive paths between each layer increases, and the wiring circuits of each layer are formed within a small area, making them linear. The present invention has been manufactured with these points in mind, and will be explained with reference to the drawings. Fig. 1 is a perspective view of a through-hole formed using a conventional method and filled with metal powder paste to create continuity. , in the figure, 1 is an unfired ceramic sheet, 2 is a through-hole and is filled with a metal powder paste, and 3 is a hole for determining the position.
第２図Ａ，Ｂ，Ｃは本発明の製作工程を示す斜
視図であり、第２図Ａはシート１１に導通位置の
縦の平行線１５ｂと配線回路となる横の平行線１
５ａをメタライズペーストにより10枚に印刷し、
最上、下面に肉厚シート１４を配置した斜視図で
あり、第２図Ｂは第２図Ａを積層接着した斜視図
であり、第２図Ｃは第２図Ｂの線イ−イ′と線ロ
−ロ′とより切断して線イ−イ′よりの切断面を上
面にした斜視図であり、３層を積層した時上段に
位置するものである。 FIGS. 2A, B, and C are perspective views showing the manufacturing process of the present invention. FIG.
Print 5a on 10 sheets using metallized paste,
It is a perspective view of thick sheets 14 arranged on the top and bottom surfaces, FIG. 2B is a perspective view of FIG. 2A laminated and bonded, and FIG. It is a perspective view taken along the line RO-RO' and with the cut surface along the line E-I' facing upward, and is located at the upper stage when three layers are laminated.
第３図は第２図Ａ，Ｂ，Ｃと同じ方法にて製作
した斜視図で３層を積層した時、中段に位置する
ものである。第４図は導通のない配線印刷のみの
斜視図で３層を積層した時、下段に位置するもの
である。第５図は第２図Ｃと第３図、第４図を積
層接着した斜視図、第６図は第５図の両端面を切
断した斜視図、第７図は焼結してIC素子を塔載
した斜視図である。 FIG. 3 is a perspective view manufactured by the same method as FIGS. 2A, B, and C, and is located in the middle when three layers are laminated. FIG. 4 is a perspective view of only wiring printed without conduction, which is located at the bottom when three layers are laminated. Figure 5 is a perspective view of Figure 2C, Figures 3 and 4 stacked and bonded together, Figure 6 is a perspective view of Figure 5 with both end faces cut away, Figure 7 is an IC element formed by sintering. FIG.
以上の本発明の製造法では従来法で製作出来な
い導通孔径が0.3mm以下であり隣接する導通位置
との間隔寸法が0.6mm以下であつても確実に製作
出来るし、各層の配線回路印刷も同時に行うた
め、印刷に要する経費や手間が省略出来、印刷の
結線不良による断線等が皆無となる。また導通と
なる印刷線幅の最小寸法が0.1mmで各導通間隔の
最小寸法が0.2mmのような従来法では想像も出来
ない程、高密度な配線回路を形成することが本発
明の方法では容易に製作出来る。 The manufacturing method of the present invention described above can reliably produce conductive holes with a diameter of 0.3 mm or less, which cannot be manufactured using conventional methods, and even if the distance between adjacent conductive positions is 0.6 mm or less, and print circuits on each layer. Because they are performed simultaneously, the expense and effort required for printing can be omitted, and there is no disconnection due to poor printing connections. In addition, the method of the present invention allows the formation of a high-density wiring circuit that is unimaginable with conventional methods, such as the minimum width of printed lines for conduction of 0.1 mm and the minimum dimension of each conductive interval of 0.2 mm. Easy to manufacture.
以下実施例について説明する。 Examples will be described below.
実施例 １
平均粒径1.5μのアルミナ96重量部と同粒径の
マグネシヤ、カルシヤ、シリカ等の焼結助剤４重
量部からなる混合粉末100重量部に対して有機質
バインダーとしてポリビニルブチラール樹脂６重
量部と可塑剤のヂブチルフタレート（符号Ｄ、
Ｂ、Ｐ）４重量部を配合し、溶剤のメチルエチル
ケトン（符号Ｍ、Ｅ、Ｋ）を用いてスラリー化し
ドクターブレード法により厚さ0.5mmと1.0mmのグ
リーンシートを製作した。Example 1 6 parts by weight of polyvinyl butyral resin as an organic binder for 100 parts by weight of a mixed powder consisting of 96 parts by weight of alumina with an average particle size of 1.5μ and 4 parts by weight of a sintering aid such as magnesia, calcia, silica, etc. with the same particle size. part and plasticizer dibutyl phthalate (code D,
B, P) 4 parts by weight were blended and slurried using methyl ethyl ketone (signs M, E, K) as a solvent, and green sheets with thicknesses of 0.5 mm and 1.0 mm were produced by the doctor blade method.
このグリーンシートを同一の外形寸法に切断し
てシート１１を得、４隅に位置を決める孔１３を
設け、10枚を製作し、又別に1.0mmのグリーンシ
ートを同一外形寸法にて10枚を切断し、４隅に位
置を決める孔１３を設け、各５枚づつを積層、接
着して最上、最下シート１４とする。 This green sheet was cut into the same external dimensions to obtain the sheet 11, holes 13 were provided at the four corners to determine the position, and 10 sheets were manufactured.In addition, 10 sheets of 1.0 mm green sheets with the same external dimensions were manufactured. They are cut, holes 13 are made at the four corners to determine the position, and five sheets each are laminated and glued to form the top and bottom sheets 14.
次に厚さ0.5mmシート１１（シートの厚さが縦
方向の各導通間隔となる）の10枚の導通位置とな
る２本の縦の平行線１５ｂと、その縦の平行線の
１本に直角に交わり配線回路となる横の平行線１
５ａを1.0mmの等間隔に幅0.4mmで厚さ0.03mmのメ
タライズペーストによる印刷線をタングステン粉
末97重量％とアルミナ粉末３重量％の合計100重
量部（平均粒径１μ）にバインダーのエチルセル
ローズ５重量部と有機溶剤のブチルカルビトール
30重量部とを混合したペーストにてスクリーン印
刷する。以上の斜視図を第２図Ａに示す。 Next, two vertical parallel lines 15b that are the conductive positions of 10 sheets of 0.5 mm thick sheet 11 (the thickness of the sheet corresponds to each conductive interval in the vertical direction), and one of the vertical parallel lines. Horizontal parallel lines 1 that intersect at right angles and form a wiring circuit
Print lines of 5a with metallized paste of 0.4 mm width and 0.03 mm thickness at equal intervals of 1.0 mm are mixed with a total of 100 parts by weight (average particle size 1 μ) of 97% by weight of tungsten powder and 3% by weight of alumina powder and ethyl cellulose as a binder. 5 parts by weight and organic solvent butyl carbitol
Screen print using a paste mixed with 30 parts by weight. The above perspective view is shown in FIG. 2A.
次に最下層の積層した５mmシート１４上に印刷
線１５ｂを同一方向に位置決め孔を使用して10枚
を積層し、其の上に最上層の積層した５mmシート
１４を積層して接着装置にて接着する。その斜視
図を第２図Ｂに示す。 Next, the printed lines 15b are placed in the same direction on the 5 mm sheet 14 which is the laminated bottom layer, and 10 sheets are laminated using the positioning holes, and the 5 mm sheet 14 which is the laminated top layer is laminated on top of the printed line 15b, and then the laminated 5 mm sheet 14 is placed in the adhesive device. and glue. A perspective view thereof is shown in FIG. 2B.
次に切断機を使用して第２図Ａでの横方向印刷
線１５ａの線***部であり第２図Ｂの線イ−
イ′の矢印方向に直角に切断し、つぎに第２図Ａ
での印刷線１５ａの平行線間の中央部で線ロ−
ロ′の矢印方向に直角に切断する。この時の切断
した厚さは0.5mmである。この要領で何枚かを切
断し、印刷線***部で切断した面を上面として
シート４隅に位置を決める孔１８を設け第２図Ｃ
の斜視図に示す。この製作したシートが積層した
時、最上段に位置するものとし、リード取出し部
１９及びIC素子２９を塔載する接続部２０の印
刷を必要に応じ行つてもよい。 Next, using a cutting machine, cut the center part on the horizontal printed line 15a in FIG. 2A and the line E in FIG. 2B.
Cut at right angles to the direction of the arrow A', and then
In the center between the parallel lines of the printed line 15a,
Cut at right angles in the direction of the arrow B. The thickness of the cut at this time is 0.5 mm. Cut several sheets in this manner, and make holes 18 to determine the position at the four corners of the sheet, with the cut surface at the center on the printing line as the top surface, as shown in Figure 2C.
This is shown in a perspective view. When the produced sheets are stacked, they will be positioned at the top, and the connection section 20 on which the lead extraction section 19 and the IC element 29 are mounted may be printed as necessary.
以上の工程と同様にして積層したときに第２層
目に位置するシートを製作し、これを第３図に示
す。 A sheet that will be the second layer when laminated is produced in the same manner as in the above process, and this is shown in FIG.
次に積層したとき下段に位置するシートの製作
は第２図Ａの導通位置となる縦線１５ｂの印刷は
行わない。またリード取出部の印刷も不用であ
り、其の他は上記方法と同様に行つて第４図に示
すシートを製作した。 Next, when manufacturing the lower sheet when stacked, the vertical lines 15b, which are the conductive positions shown in FIG. 2A, are not printed. Further, there was no need to print the lead extraction portions, and the sheet shown in FIG. 4 was manufactured in the same manner as described above.
次に積層するため第４図に示すシートの４隅の
位置合せ孔を接着治具に挿入して下段に位置させ
その上に第３図に示すシートを載せ、つぎに上段
に第２図Ｃに示すシートを載置して接着する。こ
れを第５図に示す。次に不用部分の両端面を切断
して第６図に示す所望の形状とし、温度200℃中
にて樹脂抜きを行つたあと、温度1550℃の水素雰
囲気中にて１時間保持して焼結し、目的の製品を
得た。IC素子２９を載置した斜視図を第７図に
示す。 Next, in order to stack the sheets, insert the positioning holes at the four corners of the sheets shown in Figure 4 into the adhesive jig, position them in the lower stage, place the sheets shown in Figure 3 on top of them, and then place the sheets shown in Figure 2 in the upper stage. Place and adhere the sheet shown in . This is shown in FIG. Next, both end faces of the unnecessary part were cut to give the desired shape as shown in Figure 6, and after removing the resin at a temperature of 200°C, it was held in a hydrogen atmosphere at a temperature of 1550°C for 1 hour and sintered. and obtained the desired product. A perspective view in which the IC element 29 is mounted is shown in FIG.
実施例１と同様にして電子部品のセラミツクチ
ツプキヤリヤの小型品を製作したものと、前記実
施例のIC基板とを、従来法のスルーホールを設
けて金族粉末ペーストを充填して製作した従来品
とを実際使用比較試験を行つたところ、差違なく
良好な結果が得られた。又、主表面の寸法は従来
法にて製作した製品より本発明品は1/3以下の小
型になつた。 A small ceramic chip carrier for electronic components was manufactured in the same manner as in Example 1, and the IC board of the above example was manufactured by providing through holes using the conventional method and filling them with metal group powder paste. When we conducted a practical comparison test with the conventional product, good results were obtained without any difference. In addition, the dimensions of the main surface of the product of the present invention are smaller than those of products manufactured by conventional methods, less than 1/3.
また上記実施例では、グリーンシート上に印刷
して積層、接着する方法について記述したが、最
上、下層のみグリーンシートを使用し、中間はグ
リーンシートと同質のペーストを塗布し、その上
面に印刷を施し、それを反復繰返して製造する方
法も可能である。 In addition, in the above example, a method of printing on green sheets, laminating, and adhering was described, but green sheets are used only for the top and bottom layers, a paste of the same quality as the green sheets is applied to the middle, and printing is performed on the top surface. It is also possible to manufacture the product by repeatedly applying the same process.
以上の実施例では３層の積層品について述べた
が、積層枚数は何層であつても限定されない。 In the above embodiments, a three-layer laminate was described, but the number of layers is not limited.
本発明の製造法は配線の密度が高くて層間に多
数の導通位置を有し、導通間の間隔寸法が極端に
接近した多層セラミツク基板の製造法に適し、小
型化して配線密度をあげる合理的な製法である。 The manufacturing method of the present invention is suitable for manufacturing multilayer ceramic substrates with high wiring density, many conductive positions between layers, and extremely close spacing between conductive lines, and is rational for miniaturization and increasing wiring density. It is a manufacturing method.
電子部品関係の小型品から大型品に利用出来
て、今後の期待は大きい。 It can be used for both small and large products related to electronic components, and there are high expectations for the future.
第１図はパンチングしたグリーンシートにスル
ーホールを設け、金属粉末ペーストを充填し、配
線を施した従来の製造法による斜視図、第２図Ａ
は本発明で導通線と配線回路を印刷して設け、
上、下面層を配置した斜視図。第２図Ｂは第２図
Ａを積層接着した斜視図。第２図Ｃは第２図Ｂの
線イ−イ′と線ロ−ロ′より切断し、線イ−イ′切
断面を上面とした（積層した時上段に位置する）
斜視図である。第３図は第２図Ａ，Ｂ，Ｃと同様
にして製作した（積層した時中段に位置する）斜
視図、第４図は第２図Ａ，Ｂ，Ｃと同様にして製
作した（積層した時下段に位置する）斜視図、第
５図は第２図Ｃと第３図、第４図を積層、接着し
た斜視図、第６図は両端面を切断した斜視図、第
７図は焼結後、後処理を行つてIC素子を塔載し
た斜視図である。
１，１１……パンチングしたグリーンシート、
２……スルーホールに金属粉末のペーストを充填
した導通口、３，１３，１８，２８，３８……位
置を決める孔、５……配線回路、１４……積層接
着した最上、下面に位置するシート、１５ａ，２
５ａ，３５ａ……配線回路となる印刷線、１５ｂ
……層間の導通となる印刷線、１６……印刷端の
露出した積層端面、１７，２７，３７……積層し
たものを切断したシート、１９……リード取出し
部、２０……素子との接続部、２９……IC素
子。
Figure 1 is a perspective view of a conventional manufacturing method in which through-holes are formed in a punched green sheet, filled with metal powder paste, and wired. Figure 2A
In the present invention, a conductive line and a wiring circuit are printed and provided,
A perspective view showing the arrangement of upper and lower layers. FIG. 2B is a perspective view of FIG. 2A laminated and bonded. Figure 2C is cut from line E-I' and line Ro-RO' in Figure 2B, with the cut surface of line E-I' as the top surface (located in the upper layer when stacked)
FIG. Figure 3 is a perspective view produced in the same manner as Figure 2 A, B, and C (positioned in the middle when stacked), and Figure 4 is a perspective view produced in the same manner as Figure 2 A, B, and C (layered). Fig. 5 is a perspective view of Fig. 2 C, Fig. 3, and Fig. 4 laminated and glued together, Fig. 6 is a perspective view with both end faces cut, Fig. 7 is a perspective view FIG. 3 is a perspective view of an IC element mounted on the tower after sintering and post-processing. 1,11...Punched green sheet,
2...Through holes filled with metal powder paste, 3, 13, 18, 28, 38... Holes to determine the position, 5... Wiring circuit, 14... Laminated and bonded topmost, located on the bottom surface Seat, 15a, 2
5a, 35a...Printed line that becomes a wiring circuit, 15b
...Printed line that serves as conduction between layers, 16...Laminated end face with exposed printed end, 17, 27, 37... Sheet cut from the laminated material, 19... Lead extraction portion, 20... Connection with element Section 29...IC element.
Claims (1)
ツク基板の製造法に於いて、未焼成セラミツク板
にメタライズペーストによる縦の平行線と該平行
線に直角に交る横の平行線を印刷して設け、それ
らの印刷線が同一方向になるように未焼成セラミ
ツク板を積層し、接着して、次に横の平行線上の
中央部と平行線間の中央部から縦の平行線に垂直
に切断して、印刷線上の切断面を回路配線とした
主表面とし、切断両面の印刷線切口部を導通口と
し、これらと同様にして積層する２層目、３層目
を製作し、これらを積層、接着して非酸化性雰囲
気中で焼成することを特徴とする高密度多層配線
セラミツク基板の製造法。1. In the method of manufacturing a multilayer wiring ceramic board that has electrical continuity with the wiring in each layer, vertical parallel lines made of metallized paste and horizontal parallel lines crossing the parallel lines at right angles are printed on an unfired ceramic board. Laminate the unfired ceramic plates so that their printed lines are in the same direction, glue them together, and then cut perpendicularly to the vertical parallel lines from the center on the horizontal parallel lines and the center between the parallel lines. Then, the cut surface on the printed line is used as the main surface for the circuit wiring, the cut portion of the printed line on both sides of the cut is used as the conductive hole, and the second and third layers are manufactured in the same manner as above, and these are laminated. A method for producing a high-density multilayer wiring ceramic substrate, which is characterized by bonding and firing in a non-oxidizing atmosphere.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2168479A JPS55115398A (en) | 1979-02-26 | 1979-02-26 | Method of manufacturing high density multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2168479A JPS55115398A (en) | 1979-02-26 | 1979-02-26 | Method of manufacturing high density multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55115398A JPS55115398A (en) | 1980-09-05 |
| JPS6259479B2 true JPS6259479B2 (en) | 1987-12-11 |
Family
ID=12061883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2168479A Granted JPS55115398A (en) | 1979-02-26 | 1979-02-26 | Method of manufacturing high density multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55115398A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2658726B2 (en) * | 1991-09-26 | 1997-09-30 | 三菱電機株式会社 | refrigerator |
-
1979
- 1979-02-26 JP JP2168479A patent/JPS55115398A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55115398A (en) | 1980-09-05 |
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