JPS6258671A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6258671A JPS6258671A JP60198076A JP19807685A JPS6258671A JP S6258671 A JPS6258671 A JP S6258671A JP 60198076 A JP60198076 A JP 60198076A JP 19807685 A JP19807685 A JP 19807685A JP S6258671 A JPS6258671 A JP S6258671A
- Authority
- JP
- Japan
- Prior art keywords
- grooves
- region
- film
- trench
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 21
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 229920005591 polysilicon Polymers 0.000 abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000007123 defense Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は超高密度ＬＳＩにおいて、ＭＯＳトランジスタ
及び下層にキャパシタをつくる半導体装置の製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for forming a MOS transistor and a capacitor thereunder in an ultra-high density LSI.
従来の技術
１９８４年１２月に米国インターナショナル エレクト
ロン デバイス ミーティングＣＩ ［Ｄ Ｍ ３にお
いて講演番号９．３． ９．４，９．５で提案された［
ダイナミックＲＡＭにおける木子間分離とセルメモリー
キャパシタを共有したＭｔｊ 造Ｊでは、その＠迫上プ
ロセスが非常に複雑になる欠点があった。その困難なプ
ロセスの数列を第３図と第４図に示づ。Prior Art In December 1984, at the US International Electron Device Meeting CI [DM 3, Lecture No. 9.3. Proposed in 9.4, 9.5 [
The Mtj structure J, which shared the chip separation and cell memory capacitor in dynamic RAM, had the disadvantage that the process was extremely complicated. The numerical sequence of this difficult process is shown in Figures 3 and 4.
第３図はＳｉ基板１に溝を形成した一部の凸部をとり出
して示したものである。この溝中の一部ではポリシリコ
ン１４を埋め込み、一部では数μｌの深さにまでこのポ
リ３ｉを駐り出して絶縁ｖ１５を埋め込むという工程が
要求される。しかも、上部にむいてポリＳｉの酸化等を
行なったり、ＬＳＩの通常プロセスとは非常に整合性の
悪い困難な工程を多く含んでしまう。また、第４図は８
１基板１に溝を形成した後にｎｌの拡散層１６と、一部
ではｐ＋の拡散層１７を数μｆの深さに形成された？１
４側面に選択的に形成する必要があったりザる。この工
程については、溝幅が０．５μｌ＋！ｉ！麿となるため
、深さ数μｔの満へ拡散／６：選択的に入れることは容
易ではない。FIG. 3 shows a part of the convex portion in which a groove is formed in the Si substrate 1. As shown in FIG. A process is required in which polysilicon 14 is buried in a part of this groove, and in a part of the groove, this polysilicon 3i is brought out to a depth of several microliters and an insulator v15 is buried. Furthermore, it involves many difficult steps that are very inconsistent with normal LSI processes, such as oxidizing the poly-Si toward the top. Also, Figure 4 shows 8
1 After forming a groove in the substrate 1, an Nl diffusion layer 16 and, in some cases, a P+ diffusion layer 17 were formed to a depth of several μf. 1
It may be necessary to selectively form the four sides. For this process, the groove width is 0.5μl+! i! Diffusion to a depth of several μt/6: It is not easy to selectively introduce the material.
５芒明が解決しようとする問題点
このような従来の製造方法ではシリコンのｒｌと動領域
を分離で囲まれた形で、下部にコンデンサ等を形成した
メモリセルとしてのセルキャパシタを形成づることが非
常に難しい。The problem that 5-point mei is trying to solve In this conventional manufacturing method, a cell capacitor is formed as a memory cell with a silicon RL and a dynamic region separated and surrounded by a capacitor at the bottom. is very difficult.
本弁明は上記のようなセルキャパシタを従来の１−８１
製造プロセス技術で実現できる半導体の製造方法を提供
することを目的とする。This defense is based on the conventional 1-81 cell capacitor as described above.
The purpose is to provide a semiconductor manufacturing method that can be realized using manufacturing process technology.
問題点を解決Ｊるための手段
木ｙｈ明の半導体装置の製造方法は、半導体基板に必要
な深きを有する溝を形成し、その上にカバレッジが侵れ
た膜を（１９記溝中にまでｉ（Ｃ積し、垂直方向に強い
異方性のあるエツチング法により前記１積膜をエツチン
グして前記溝側面にだけ前記堆積膜を残留させ、溝中の
半導体基板表面が露出した部分をさらに深くエツチング
して、この深く形成された溝を用いて容量素子あるいは
分離領域の一部として半導体装置を形成したことを特徴
とする。Means to Solve the Problems The semiconductor device manufacturing method of Kimihiro Kiyohime is to form a groove with the required depth on the semiconductor substrate, and then deposit a film with poor coverage on the groove (19). i(C), and etching the one layered film using an etching method with strong vertical anisotropy, leaving the deposited film only on the side surfaces of the trench, and further etching the exposed portion of the semiconductor substrate surface in the trench. The semiconductor device is characterized in that it is etched deeply and uses this deeply formed groove to form a semiconductor device as a part of a capacitive element or isolation region.
作用
この構成によると、ＭＯＳ トランジスタを形成するた
めの浅い分離溝を掘り、そのまわりを酸化膜で覆い、そ
の覆われたままの状態で深い溝掘りエツチングを追加し
、必要な不純物ドーピングを行なってキャパシタを形成
する壁を形成し、表面に絶縁膜を形成してポリシリコン
電極を埋め込み、浅い部分には、５ｉ０２等の堆積絶縁
物を埋め込み分離と容量の共用プロセスを完成するので
、表面に近いＭＯＳトランジスタ形成領域を酸化膜等で
取り囲んだ後に、深い部分に容量をつくるため、容ｆｆ
ｉ領域を形成するときに上部の素子領域への影響が小さ
く、はぼ分離してつくることが可能であり、ザベて埋め
込んだ後では、容量領域は上に全く露出していない。し
かもづべての］二二番よ、現在のＬＳＩの工程と整合性
が高く比較的容易に実現づることができる。Operation According to this configuration, a shallow isolation trench is dug to form a MOS transistor, its surroundings are covered with an oxide film, and deep trench etching is added while the trench is covered, and the necessary impurity doping is performed. A wall for forming a capacitor is formed, an insulating film is formed on the surface, and a polysilicon electrode is buried, and a deposited insulator such as 5i02 is buried in the shallow part to complete the isolation and capacitance sharing process. After surrounding the MOS transistor formation region with an oxide film, etc., the capacitance is
When forming the i-region, the effect on the upper element region is small, and it is possible to form the i-region separately, and after it is buried and buried, the capacitor region is not exposed above at all. Moreover, point 22 is highly compatible with current LSI processes and can be realized relatively easily.
実施例
以下、本弁明の製造方法を具体的な一実施例に基づいて
説明づる。EXAMPLE Hereinafter, the manufacturing method of the present invention will be explained based on a specific example.
第１図（ａ）〜（０）は本発明の工程図を示づ。先ず、
■Ｐｉ！（ａ）においてはＰ型Ｓ ＋ Ｍ板１にレジス
トマスク用酸化映としての５ｉＯ２１１Ｑ２を形成して
、エツチングにより５ｉｌＪ板１に約０．５μｍ深さの
満を形成した。この溝中にｊＢいては、溝の壁を含めて
一部ではｒ１型、ある部分ではｐ型のイオンを一イオン
ビーム３て注入して［１１領域４、ｎ１領域５のを作り
分けた。次に、工程（］」）にＪ３いて減圧ＣＶＤ法に
よって酸化膜としてカバレッジが優れている５ｉＯ２ｉ
（ｆ、積膜６を形成し、工程（Ｃ）ではその上からＯ３
Ｆ８ガスを用いたカソードカップリング平行平板型ドラ
イエツチング法（以下、Ｉ ＲＥ法と称″ｔｊ）により
エツチングし、溝側面にだけＳｉＯ２堆積膜６を残存さ
せた。７はこの残存したＳｉＯ２膜を表わしている。次
に工程（ｄ）において再びＲＩＥ法により３ｉ基板１を
約４μｍの深さにまでエツチングを行なった。そしてＯ
４の不純物を導入しｎ４領域８を形成し溝の底には、ｐ
“領域９の形成を行なった。ｎ１領域８およびｎ１領域
９は何れもイオン打込み法によった。この工程図の右側
に示ｔＡの部分は、酸化膜としてのＳｉＯ２膜７で覆わ
れているため、各種の不純物ドーピング時には全く影響
されない構造をもっている。この縦の壁に残留された５
ｉＯｚ膜７が本発明のポイントである。FIGS. 1(a) to 1(0) show process diagrams of the present invention. First of all,
■Pi! In (a), 5iO211Q2 was formed as an oxide film for a resist mask on a P-type S + M plate 1, and a hole with a depth of about 0.5 μm was formed on a 5ilJ plate 1 by etching. In this groove, including the walls of the groove, r1 type ions were implanted in some areas and p type ions were implanted in some areas using an ion beam 3 to form a region 4 and an n1 region 5 separately. Next, in the process (]''), 5iO2i, which has excellent coverage as an oxide film, is processed by low pressure CVD using J3.
(f, forming the laminated film 6, and in step (C) O3
Etching was carried out by a cathode coupled parallel plate dry etching method (hereinafter referred to as IRE method) using F8 gas, leaving the SiO2 deposited film 6 only on the side surfaces of the groove. Next, in step (d), the 3i substrate 1 was etched to a depth of about 4 μm by RIE again.
4 impurity is introduced to form an n4 region 8, and at the bottom of the trench, p
“A region 9 was formed. Both the n1 region 8 and the n1 region 9 were formed by ion implantation. The portion tA shown on the right side of this process diagram is covered with a SiO2 film 7 as an oxide film. Therefore, it has a structure that is completely unaffected by the doping of various impurities.
The iOz film 7 is the key point of the present invention.
そして次の工程（ｅ）において、はぼ最終の形を示す。In the next step (e), the final shape of the dowel is shown.
１５は溝の中に埋込み形成されたポリシリコンを示す。Reference numeral 15 indicates polysilicon buried in the trench.
Ａ′の部分にはゲート電極１２、ｎ４′領域のソース１
１、ｎ”領域のドレイン１０が形成され、配線電極１３
をもっているＭＯＳトランジスタを示しており、Ｂ′の
部分にはキャパシタ絶縁膜として１０ｎ１の厚さの薄い
酸化膜１４と埋込み電極としてのポリシリコン１５を有
するセルキャパシタを示すものである。なおＡ′部分の
溝中には絶縁膜として５ｉ０２が埋め込まれている。A' part has a gate electrode 12 and a source 1 in the n4' region.
1, the drain 10 in the n'' region is formed, and the wiring electrode 13
The part B' shows a cell capacitor having a thin oxide film 14 with a thickness of 10n1 as a capacitor insulating film and polysilicon 15 as a buried electrode. Note that 5i02 is embedded as an insulating film in the trench of the A' portion.
上部のＭＯＳトランジスタのソース電極とけルキッパシ
タの部分は■稈（ａ）で形成したｒｌ”領域４′により
電気的に接続されており、ドレイン領域１０とキャパシ
タの一方の電極部分である日＋領域８とは工程（ａ）で
形成したｐ＋領域５′によって分離されている。The source electrode of the upper MOS transistor and the capacitor part are electrically connected by the rl'' region 4' formed by the culm (a), and the drain region 10 and the capacitor region 8 which is one electrode part of the capacitor. and is separated by the p+ region 5' formed in step (a).
第２図においては、本プロセスを用いることによって作
成したダイナミツすス七リヒルの１−ランジスタ部分の
立体図を第１図（０）に対応して示している。なお、Ｍ
ＯＳトランジスタのゲート及びその上の電極、配線、保
護膜については、省略されている。In FIG. 2, a three-dimensional view of the 1-transistor part of the dynamic transistor manufactured by using this process is shown corresponding to FIG. 1 (0). In addition, M
The gate of the OS transistor, the electrode thereon, the wiring, and the protective film are omitted.
弁明の効宋
以上説明のように本発明の半導体装置の￥！迄方法は、
半導体基板の表面に近いＭＯＳトランジスタ形成領域を
酸化躾等で取り囲んだ後に、深い部分に容量をつくると
いう工程を用いているため、容量領域を形成するときに
上部の素子領域への影響が小さく、はぼ分離してつくる
ことが可能であり、すべて埋め込んだ後では、容量領域
は上に全く露出していない。しかもづべての工程は、現
在のＬＳＩの工程と整合性が高く比較的容易に実現する
ことができる。Effect of Defense Song As explained above, the semiconductor device of the present invention costs ¥! The method up to
The process uses a process in which the MOS transistor formation region near the surface of the semiconductor substrate is surrounded with oxide, etc., and then a capacitance is created in a deep part, so when forming the capacitance region, the effect on the upper element region is small. It is possible to make it separately, and after filling it all, no capacitive area is exposed above. Furthermore, all of the steps described above are highly consistent with current LSI processes and can be implemented relatively easily.
また、比較的容易な製造工程でありながら、高密度が可
能で容量の十分に大きなメモリーセルを形成することが
できる。Further, it is possible to form a memory cell with high density and sufficiently large capacity while using a relatively easy manufacturing process.
第１図は本発明の具体的な一実施例の製造工程断面図、
第２図は本発明の方法により作成されたダイナミックセ
ルの構造図、第３図と第４図は従来のＭ４造の説明図で
ある。
１−８ ｉ基板、６−＝Ｓ ｉ ０２ Ｎ１１ａ膜、８
−ｎ ”領域、１４・・・酸化躾〔キャパシタ絶縁膜］
、１５・・・ポリシリコン
代理人 森 本 義 弘
第１図
フ
デＰｔ＠域
第２図FIG. 1 is a cross-sectional view of the manufacturing process of a specific embodiment of the present invention;
FIG. 2 is a structural diagram of a dynamic cell produced by the method of the present invention, and FIGS. 3 and 4 are explanatory diagrams of a conventional M4 structure. 1-8 i substrate, 6-=S i 02 N11a film, 8
-n'' region, 14... oxidation [capacitor insulating film]
, 15...Polysilicon Agent Yoshihiro Morimoto Figure 1 Fude Pt @ Area Figure 2
Claims (1)
上にカバレッジが優れた膜を前記溝中にまで堆積し、垂
直方向に強い異方性のあるエッチング法により前記堆積
膜をエッチングして前記溝側面にだけ前記堆積膜を残留
させ、溝中の半導体基板表面が露出した部分をさらに深
くエッチングして、この深く形成された溝を用いて容量
素子あるいは分離領域の一部として半導体装置を形成し
た半導体装置の製造方法。 ２、カバレッジの優れた膜を絶縁膜としたことを特徴と
する特許請求の範囲第１項記載の半導体装置の製造方法
。 ３、第２番目のシリコンエッチングで形成された溝を薄
い絶縁膜を介して電極を形成し、コンデンサとしたこと
を特徴とする特許請求の範囲第１項記載の半導体装置の
製造方法。[Claims] 1. An etching method that forms a trench with a necessary depth in a semiconductor substrate, deposits a film with excellent coverage into the trench, and has strong anisotropy in the vertical direction. The deposited film is etched so that the deposited film remains only on the side surfaces of the trench, and the exposed part of the semiconductor substrate surface in the trench is further etched deeply, and this deeply formed trench is used to form a capacitive element or an isolation device. A method for manufacturing a semiconductor device in which the semiconductor device is formed as part of a region. 2. The method of manufacturing a semiconductor device according to claim 1, characterized in that a film with excellent coverage is used as an insulating film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein an electrode is formed in the groove formed by the second silicon etching through a thin insulating film to form a capacitor.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60198076A JPS6258671A (en) | 1985-09-06 | 1985-09-06 | Manufacture of semiconductor device |
| KR1019860005211A KR900001836B1 (en) | 1985-07-02 | 1986-06-28 | Method of manufacturing semiconductor device |
| US07/218,456 US4920390A (en) | 1985-07-02 | 1988-07-07 | Semiconductor memory device and method of fabricating the same |
| US07/404,447 US5026658A (en) | 1985-07-02 | 1989-09-08 | Method of making a trench capacitor dram cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60198076A JPS6258671A (en) | 1985-09-06 | 1985-09-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6258671A true JPS6258671A (en) | 1987-03-14 |
Family
ID=16385114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60198076A Pending JPS6258671A (en) | 1985-07-02 | 1985-09-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6258671A (en) |
-
1985
- 1985-09-06 JP JP60198076A patent/JPS6258671A/en active Pending
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