JPH0334378A - Mos type field effect transistor - Google Patents
Mos type field effect transistorInfo
- Publication number
- JPH0334378A JPH0334378A JP16945689A JP16945689A JPH0334378A JP H0334378 A JPH0334378 A JP H0334378A JP 16945689 A JP16945689 A JP 16945689A JP 16945689 A JP16945689 A JP 16945689A JP H0334378 A JPH0334378 A JP H0334378A
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- gate
- active region
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 230000010354 integration Effects 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＭＯＳ型電界効果トランジスタに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a MOS type field effect transistor.
ＭＯ３型トランジスタは、バイポーラ型トランジスタに
比して高集積化に適し、特に大容量メモリデバイスに広
く使用されている。しがしながら、メモリデバイスを更
に大容量高集積化するには通常の平面的な構造よりも平
面積利用効率の高い三次元的な構造のＭＯ３型トランジ
スタが望ましい。MO3 type transistors are more suitable for high integration than bipolar type transistors, and are particularly widely used in large capacity memory devices. However, in order to further increase the capacity and integration of memory devices, MO3 type transistors having a three-dimensional structure, which has a higher planar area utilization efficiency than a normal planar structure, are desirable.
従来、三次元構造のＭＯ８型トランジスタはいくつか提
案されているが、代表的なものに溝内にソース、ドレイ
ン、チャネルを形成した縦型ＭＯＳトランジスタがある
。縦型ＭＯＳ）ランジスタについては、例えばアイイー
デイエム（ＩＥＤＭ）１９８５年、予稿集、７１４〜７
１７頁に記載されている。Several MO8 type transistors with a three-dimensional structure have been proposed in the past, and a typical one is a vertical MOS transistor in which a source, drain, and channel are formed in a trench. Regarding vertical MOS) transistors, for example, IEDM (IEDM) 1985, Proceedings, 714-7.
It is described on page 17.
第３図は従来の縦型ＭＯＳトランジスタの一例の断面図
である。FIG. 3 is a cross-sectional view of an example of a conventional vertical MOS transistor.
Ｐ型シリコン基板１に後でソース領域、チャネル領域と
なるＮ型層、Ｐ型層を形成し、フィールド酸化膜８を形
成する。イオン注入法等により表面にＮ型層を形成した
後、素子間分離溝５を掘る。ゲート酸化膜６、ゲート電
極７を形成することにより、Ｎ型ソース領域２、Ｐ型チ
ャネル領域３、Ｎ型ドレイン領域４、ゲート電極７から
成る縦型ＭＯＳトランジスタが構成される。An N-type layer and a P-type layer, which will later become a source region and a channel region, are formed on a P-type silicon substrate 1, and a field oxide film 8 is formed. After forming an N-type layer on the surface by ion implantation or the like, an isolation groove 5 between elements is dug. By forming gate oxide film 6 and gate electrode 7, a vertical MOS transistor consisting of N type source region 2, P type channel region 3, N type drain region 4, and gate electrode 7 is configured.
上述した従来の縦型ＭＯＳトランジスタは、第３図から
分るように、平面的な活性領域内に縦型のチャネルを形
成するための溝５を設けていた。As can be seen from FIG. 3, the conventional vertical MOS transistor described above has a trench 5 for forming a vertical channel in a planar active region.
この溝の開孔面積は活性領域の面積（ドレインの平面積
）を減少させ、平面積利用効率を低下させるという欠点
がある。また、従来の縦型トランジスタでは素子間を電
気的に分離するのになんらかの素子量分Ｍｎ４造を必要
とする（第３図ではフィールド酸化膜８による分離〉。The opening area of this groove reduces the area of the active region (the planar area of the drain), which has the disadvantage of reducing the planar area utilization efficiency. Furthermore, in conventional vertical transistors, a certain amount of Mn4 is required to electrically isolate between elements (isolation by field oxide film 8 in FIG. 3).
この素子間分離用の非活性領域の面積もトランジスタを
高集積化する上での大きな障害となる。The area of this inactive region for isolation between elements also becomes a major obstacle in achieving high integration of transistors.
本発明のＭＯ３型電界効果トランジスタは、半導体基板
上にソース領域、チャネル領域及びドレイン領域が積層
されて成る活性領域と、前記活性領域のうちの少くとも
上から二層までの領域を分−離するように形成された溝
と、前記溝の側壁でありかつ前記活性領域の側壁である
部分に設けられたゲート絶縁膜と、前記ゲート絶縁膜上
に形成されたゲート電極とを含んで構成される。The MO3 type field effect transistor of the present invention has an active region formed by stacking a source region, a channel region, and a drain region on a semiconductor substrate, and at least the upper two layers of the active region are separated. A gate insulating film provided on a side wall of the trench and a side wall of the active region, and a gate electrode formed on the gate insulating film. Ru.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の一実施例の平面図及び
Ａ−Ａ’線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of an embodiment of the present invention.
Ｐ型シリコン基板１の上にＮ型ソース領域２、Ｐ型チャ
ネル領域３、Ｎ型ドレイン領域４を形成し、各々のトラ
ンジスタを素子間分離用溝５によって分離する。露出し
たシリコン表面を熱酸化してゲート酸化膜６を形成する
。次に、溝の側壁にＮ型多結晶シリコンでゲート電極を
形成する。後は通常の方法に従って眉間絶縁膜、ソース
、ドレイン、ゲートの各電極引き出し用のコンタクト及
び金属配線等を形成して完成させる。An N-type source region 2, a P-type channel region 3, and an N-type drain region 4 are formed on a P-type silicon substrate 1, and each transistor is separated by an element isolation trench 5. A gate oxide film 6 is formed by thermally oxidizing the exposed silicon surface. Next, a gate electrode is formed using N-type polycrystalline silicon on the side wall of the trench. After that, a glabellar insulating film, contacts for drawing out each of the source, drain, and gate electrodes, metal wiring, etc. are formed according to the usual method to complete the process.
本実施例のトランジスタは、表面反転層型ＭＯＳトラン
ジスタとして動作する。The transistor of this example operates as a surface inversion layer type MOS transistor.
次に、この実施例の製造方法を説明する。Next, the manufacturing method of this example will be explained.
第２図（ａ）〜（ｃ）は第１図に示す実施例の製造方法
を説明するための工１程順に示した断面図である。FIGS. 2(a) to 2(c) are sectional views shown in order of step 1 for explaining the manufacturing method of the embodiment shown in FIG. 1.
まず、第２図に示すように、面指数（１００）のＰ型シ
リコン基板１の上にＮ型不純物であるヒ素を５Ｘ１０１
５／−のドーズ量でイオン打込みしてＮ型ソース領域２
を形成する０通常のエピタキシャル成長性により比抵抗
１Ω・０で厚さ２μｍのＰ型シリコン層を成長させＰ型
チャネル領域３とする。ヒ素を５Ｘ１０１５／−のドー
ズ量でイオン打込みしてＮ型ドレイン領域４を順次形成
する。First, as shown in FIG.
N-type source region 2 is formed by ion implantation at a dose of 5/-.
A P-type silicon layer having a resistivity of 1 Ω·0 and a thickness of 2 μm is grown using normal epitaxial growth to form a P-type channel region 3. Arsenic is ion-implanted at a dose of 5.times.10.sup.15/- to sequentially form an N-type drain region 4.
次に、第２図（ｂ）に示すように、活性領域を分離する
ための素子間分離溝５を形成する。この講の形成はホト
レジストをマスクとして通常の反応性イオンエツチング
（ＲＩＥ）技術を用いて形成した。ここで渭５の深さは
Ｎ型ソース領域２に達するだけの深さ約２，５μｍに設
定される。Next, as shown in FIG. 2(b), element isolation trenches 5 for isolating the active regions are formed. This layer was formed using a conventional reactive ion etching (RIE) technique using a photoresist as a mask. Here, the depth of the edge 5 is set to be about 2.5 μm deep enough to reach the N-type source region 2.
次に、第２図（ｃ）に示すように、９００℃のスチーム
雰囲気中で熱酸化して厚さ２０ｎｍのゲート酸化膜６を
形成する。次いで全面に４００ｎｍの厚さに多結晶シリ
コン膜７ａを成長させ、リンを添加する。Next, as shown in FIG. 2(c), a gate oxide film 6 having a thickness of 20 nm is formed by thermal oxidation in a steam atmosphere at 900°C. Next, a polycrystalline silicon film 7a is grown to a thickness of 400 nm over the entire surface, and phosphorus is added.
次いで、異方性の強いドライエツチング技術により多結
晶シリコン膜７ａを全面エツチングして活性領域の側壁
にのみ多結晶シリコンのゲート電極７を残すと、第１図
の（ａ）、（ｂ）に示す構造を得る。Next, by etching the entire surface of the polycrystalline silicon film 7a using a highly anisotropic dry etching technique, leaving the polycrystalline silicon gate electrode 7 only on the sidewalls of the active region, the result is shown in FIGS. 1(a) and (b). Obtain the structure shown.
上記実施例はチャネル領域をＰ型としたが、Ｎ型にした
縦型ＭＯＳトランジスタに対しても本発明を適用するこ
とができる。このトランジスタは、いわゆる埋込チャネ
ル型のＭＯＳトランジスタと類似の動作をする。ゲート
電極の電位がＯＶ（或は低電位）の場合には、ワークフ
ァンクションの違いによりチャネル領域４中に側面のゲ
ート電極側からバルク中央に向って空乏層が広がる。Although the above embodiment has a P-type channel region, the present invention can also be applied to a vertical MOS transistor having an N-type channel region. This transistor operates similar to a so-called buried channel type MOS transistor. When the potential of the gate electrode is OV (or low potential), a depletion layer spreads in the channel region 4 from the side gate electrode side toward the center of the bulk due to the difference in work function.
チャネル中のＮ型不純物濃度と、チャネル領域のバルク
の寸法を適当に設定すれば、ゲート側がら広がった空乏
層が継がり、チャネルを完全にカットオフする。逆に、
フラットバンド電圧以上の高電圧を印加すれば、空乏層
が縮み、蓄積層型のチャネルが形成されて導通する。If the N-type impurity concentration in the channel and the bulk dimensions of the channel region are appropriately set, the depletion layer that spreads from the gate side will continue and completely cut off the channel. vice versa,
When a high voltage higher than the flat band voltage is applied, the depletion layer shrinks and an accumulation layer-type channel is formed, resulting in conduction.
以上説明したように、本発明は、活性領域分離用の溝と
縦型ＭＯＳトランジスタのチャネルを形成するための溝
を共用するから、素子間分離のための余分な非活性領域
を必要としない、このために、従来装置に比して平面的
な集積度を向上できるという効果を有する。As explained above, in the present invention, since the trench for active region isolation and the trench for forming the channel of the vertical MOS transistor are shared, there is no need for an extra inactive region for isolation between elements. For this reason, it has the effect that the degree of planar integration can be improved compared to conventional devices.
第１図（ａ）、（ｂ）は本発明の一実施例の平面図及び
Ａ−Ａ’線断面図、第２図（ａ）〜（Ｃ）は第１図（ａ
）、（ｂ）に示す実施例の製造方法を説明するための工
程順に示した断面図、第３図は従来の縦型ＭＯＳ）ラン
ジスタの一例の断面図である。
１・・・Ｐ型シリコン基板、２・・・Ｎ型ソース領域、
３・・・Ｐ型チャネル領域、４・・・Ｎ＋型トドレイン
領域５・・・素子間分離用溝、６・・・ゲート酸化膜、
７・・・ゲート電極、７ａ・・・多結晶シリコン膜。FIGS. 1(a) and (b) are a plan view and a sectional view taken along the line A-A' of an embodiment of the present invention, and FIGS. 2(a) to (C) are FIGS.
) and (b) are cross-sectional views shown in the order of steps for explaining the manufacturing method of the embodiment shown in FIG. 3, and FIG. 3 is a cross-sectional view of an example of a conventional vertical MOS transistor. 1... P-type silicon substrate, 2... N-type source region,
3... P type channel region, 4... N+ type drain region 5... element isolation groove, 6... gate oxide film,
7... Gate electrode, 7a... Polycrystalline silicon film.
Claims (1)
領域が積層されて成る活性領域と、前記活性領域のうち
の少くとも上から二層までの領域を分離するように形成
された溝と、前記溝の側壁でありかつ前記活性領域の側
壁である部分に設けられたゲート絶縁膜と、前記ゲート
絶縁膜上に形成されたゲート電極とを含むことを特徴と
するＭＯＳ型電界効果トランジスタ。an active region formed by stacking a source region, a channel region, and a drain region on a semiconductor substrate; a trench formed to separate at least two upper layers of the active region; A MOS field effect transistor comprising: a gate insulating film provided on a sidewall of the active region; and a gate electrode formed on the gate insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16945689A JPH0334378A (en) | 1989-06-29 | 1989-06-29 | Mos type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16945689A JPH0334378A (en) | 1989-06-29 | 1989-06-29 | Mos type field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0334378A true JPH0334378A (en) | 1991-02-14 |
Family
ID=15886926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16945689A Pending JPH0334378A (en) | 1989-06-29 | 1989-06-29 | Mos type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0334378A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315143A (en) * | 1992-04-28 | 1994-05-24 | Matsushita Electric Industrial Co., Ltd. | High density integrated semiconductor device |
| JP2009038201A (en) * | 2007-08-01 | 2009-02-19 | Elpida Memory Inc | Semiconductor device and manufacturing method of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263152A (en) * | 1985-05-15 | 1986-11-21 | Nippon Texas Instr Kk | Mask rom device |
| JPS6231167A (en) * | 1985-07-30 | 1987-02-10 | イ−トン コ−ポレ−シヨン | Bidirectional power fet having on state of bipolar |
-
1989
- 1989-06-29 JP JP16945689A patent/JPH0334378A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263152A (en) * | 1985-05-15 | 1986-11-21 | Nippon Texas Instr Kk | Mask rom device |
| JPS6231167A (en) * | 1985-07-30 | 1987-02-10 | イ−トン コ−ポレ−シヨン | Bidirectional power fet having on state of bipolar |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5315143A (en) * | 1992-04-28 | 1994-05-24 | Matsushita Electric Industrial Co., Ltd. | High density integrated semiconductor device |
| JP2009038201A (en) * | 2007-08-01 | 2009-02-19 | Elpida Memory Inc | Semiconductor device and manufacturing method of semiconductor device |
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