JPS6242549A - Package for electronic part and manufacture thereof - Google Patents
Package for electronic part and manufacture thereofInfo
- Publication number
- JPS6242549A JPS6242549A JP18212685A JP18212685A JPS6242549A JP S6242549 A JPS6242549 A JP S6242549A JP 18212685 A JP18212685 A JP 18212685A JP 18212685 A JP18212685 A JP 18212685A JP S6242549 A JPS6242549 A JP S6242549A
- Authority
- JP
- Japan
- Prior art keywords
- insulating plate
- electrodes
- insulating board
- external electrode
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、ＩＣ，ＬＳＩ等の電子部品を、小形。[Detailed description of the invention] Industrial applications The present invention enables miniaturization of electronic components such as ICs and LSIs.
薄形にパッケージして部品の実装密度を向上させること
を目的とした電子部品パッケージに関するものである。The present invention relates to an electronic component package whose purpose is to improve the packaging density of components by packaging it thinly.
従来の技術
第４図、第６図、第６図に、従来の小形パッケージの一
例を示す。BACKGROUND OF THE INVENTION An example of a conventional small package is shown in FIGS. 4, 6, and 6.
以下にこの従来例の構成について、第４図、第６図、第
６図とともに説明する。第４図は、上面図、第６図は、
工程別断面、第６図は、プリント基板へ半田付けした状
態を示したものであるＯ第５図ａは、電子部品搭載用の
基板であり厚みが、０．１ａａ〜０．３順程度の耐熱性
ガラスエボキシ等の薄い絶縁板１の片面に、ダイパッド
２．ワイヤボンドパッド３．配線４．後に外部電極と本
なる導体５′を有する。形成方法は、まず、絶縁板の後
に外部電極となる導体５′が位置する部分に、パンチン
グ等により穴をあけ、絶縁板１．１′を形成する。次に
厚みが、３５）１部程度の銅箔を絶縁板の片面に、接着
する。その後エツチングにより、不要な銅箔を除去し、
ダイパッド２．ワイヤボンドパッド３．配線４．後に外
部電極となる導体５′を形成する。最後に、ダイパッド
２．ワイヤボンドパッド３にＡｕメッキ、後に外部電極
となる導体５′に半田メッキを施す。The configuration of this conventional example will be explained below with reference to FIGS. 4, 6, and 6. Figure 4 is a top view, Figure 6 is
The process-specific cross-section, Figure 6, shows the soldered state to a printed circuit board. Figure 5a shows a board for mounting electronic components, and the thickness is in the order of 0.1aa to 0.3mm. A die pad 2 is placed on one side of a thin insulating plate 1 made of heat-resistant glass epoxy or the like. Wire bond pad 3. Wiring 4. Later on, it has an external electrode and a main conductor 5'. The method for forming the insulating plate 1.1' is as follows: First, a hole is made by punching or the like in a portion of the insulating plate where the conductor 5' which will become the external electrode is located, to form the insulating plate 1.1'. Next, a copper foil having a thickness of about 35) parts is adhered to one side of the insulating board. After that, unnecessary copper foil is removed by etching,
Die pad 2. Wire bond pad 3. Wiring 4. A conductor 5' which will later become an external electrode is formed. Finally, die pad 2. The wire bond pad 3 is plated with Au, and the conductor 5', which will later become an external electrode, is plated with solder.
次に、第６図すに示すように、ダイパッド２上に、Ａｑ
ペースト等のダイボンド樹脂９を用いて、ＬＳＩチップ
６を、ダイボンドする。次にＡｕ等のボンディングワイ
ヤ８を用いて、ワイヤボンディングを行ない、ＬＳＩチ
ップ６の電極７と、ワイヤボンドバンド３を電気的に接
続する。次に、ＬＳＩチップ６を覆う様に、エポキシ等
の封止樹脂１ｏをボッティングし封止する。Next, as shown in FIG. 6, Aq
The LSI chip 6 is die-bonded using a die-bonding resin 9 such as paste. Next, wire bonding is performed using a bonding wire 8 made of Au or the like to electrically connect the electrode 7 of the LSI chip 6 and the wire bond band 3. Next, a sealing resin 1o such as epoxy is potted and sealed so as to cover the LSI chip 6.
最後に、第５図りの切断線１４の位置で、後に外部電極
となる導体５′の１部を切離した後、フォーミングを行
い、第５図Ｃに示す様に、絶縁板１から突出した、外部
電極５を得る。Finally, after cutting off a part of the conductor 5' that will later become an external electrode at the position of the cutting line 14 in the fifth diagram, forming is performed, and as shown in FIG. An external electrode 5 is obtained.
第６図に示す様に、プリント基板１１への半田付けは、
外部電極６と、プリント基板１１の電極１３と位置合わ
せした後、半田１２により接続される。半田付けの方法
としては、半田クリームを印刷してリフローする方法、
熱圧着法等がある。As shown in FIG. 6, soldering to the printed circuit board 11 is as follows.
After aligning the external electrodes 6 with the electrodes 13 of the printed circuit board 11, they are connected by solder 12. Soldering methods include printing solder cream and reflowing,
There are methods such as thermocompression bonding.
発明が解決しようとする問題点
しかしながら、上記従来例においては、外部電極が、絶
縁板より突出した、構造となっている為次に示す欠点が
ある。Problems to be Solved by the Invention However, in the conventional example described above, since the external electrode is structured to protrude from the insulating plate, there are the following drawbacks.
（１）外部電極の切断、フォーミング時、及び、プリン
ト基板への搭載時に、外部電極が薄くし厚み＃３５μｍ
）強度が弱い為、外部電極に変形、不ぞろい、浮き、が
発生し、半田付けの歩留シを低下させる。(1) When cutting and forming the external electrode, and when mounting it on the printed circuit board, the external electrode is thinned to a thickness of #35 μm.
) Due to its weak strength, external electrodes may become deformed, uneven, or lifted, reducing the soldering yield.
（２） リードレステップキャリヤパッケージ等に比
べると、突出した外部電極が占有面積を増大させ、実装
密度が低い。(2) Compared to leadless step carrier packages, etc., the protruding external electrodes increase the occupied area and the packaging density is low.
本発明は、上記従来例の欠点を除去するものであり、外
部電極の変形、不ぞろい、浮き等をなくし、半田付けを
容易にするとともに、占有面積を小さくし、小形、高密
度の電子部品パッケージを得ることを目的とするもので
ある。The present invention eliminates the drawbacks of the conventional example described above, eliminates deformation, unevenness, floating, etc. of external electrodes, facilitates soldering, reduces the occupied area, and provides a compact, high-density electronic component package. The purpose is to obtain.
問題点を解決するための手段
本発明は、上記目的を達成するために、電子部品搭載用
基板のダイパッドを有する絶縁板から突出した、外部電
極にも絶縁板を設け、ＬＳＩチップ組み込み後、外部電
極を有した絶縁板を、ダイパッドを有する絶縁板の裏面
に折り曲げる構成としたものである。Means for Solving the Problems In order to achieve the above object, the present invention provides an insulating plate also for the external electrode protruding from the insulating plate having the die pad of the electronic component mounting board, and after incorporating the LSI chip, the external The structure is such that an insulating plate having electrodes is bent onto the back side of an insulating plate having a die pad.
作 用
このように外部電極は、絶縁板で保持されている為、変
形、不ぞろい、浮きは発生しない。また、ダイパッドを
有する絶縁板の裏面に折り曲げる為、占有面積が小さく
なり、高密度な電子部品パッケージが得られるものであ
る。Function Since the external electrode is held by an insulating plate in this way, deformation, irregularity, and floating do not occur. In addition, since it is bent to the back side of the insulating plate having the die pad, the occupied area is reduced and a high-density electronic component package can be obtained.
実施例
以下に、本発明の一実施例の構成について、第１図、第
２図、第３図とともに説明する。本実施例は、薄形、小
形のＩＣ、ＬＳ Ｉパッケージであり第１図は、工程別
断面図、第２図はプリント基板への搭載例、第３図は、
完成品の上面図である。Embodiment Below, the configuration of an embodiment of the present invention will be explained with reference to FIGS. 1, 2, and 3. This example is a thin and small IC/LSI package. Figure 1 is a sectional view of each process, Figure 2 is an example of mounting on a printed circuit board, and Figure 3 is a
It is a top view of a completed product.
まず、第１図ａに電子部品搭載用基板を示す。First, FIG. 1a shows a board for mounting electronic components.
基板は、第１の絶縁板２１上に、ダイパッド２２゜ワイ
ヤボンドパッド２３．配線２４を有し、第１の絶縁板２
１より穴３５により分離された第２の絶縁板２１′上に
は、後に外部電極となる導体２ダを有する。また、穴３
６の部分には、ワイヤボンドパッド２３と後に外部電極
となる導体２６′を接続する配線の一部２４′が位置す
る。形成方法は、まず厚みが、０．１〜０．３Ｂ程度の
耐熱性ガラスエポキシ等よりなる絶縁板にプレス加工に
より穴をあけ、第１の絶縁板２１と第２の絶縁板２１′
を形成する。この時、生産方式として、ロールに巻き取
るテープ処理を行う場合は、絶縁板の巾は、３０〜８０
ｗ程度とし、外側に、ガイド孔（スプロケットホール）
を形成しておく。次に、絶縁板の片面に、銅、ＡＩ！、
Ｎｉ等の金属箔をエポキシ系等の接着剤を用い、はりつ
ける。金属箔の厚みは、通常９〜７０．ｙｍ程度である
。次に、エツチングにより、不要部の金属箔を除去し、
ダイパッド２２゜ワイヤボンドパッド２３．配線２４．
２４’、後に外部電極となる導体２５′を形成する。金
属箔が銅の場合は、塩化第二鉄等の溶液によりエツチン
グする。ワイヤボンドバット”２３の巾は、０．２〜０
．６耐程度である。外部電極となる導体２６′のピッチ
は、０．４〜１朋程度であり、後に搭載するＬＳＩチッ
プの電極板と、パッケージの寸法、実装性等を考慮して
決定する。最後に、ＬＳＩチップ裏面との電気接続及び
ワイヤボンディング性を良好にする為に、ダイパッド２
２．ワイヤボンドパッド２３に、０．１〜１ ／Ｉｆ
ｍ程度のＡｕメッキ。The substrate has die pads 22.degree. wire bond pads 23.on a first insulating plate 21. The first insulating plate 2 has wiring 24.
On the second insulating plate 21' separated from the first insulating plate 21 by the hole 35, there is provided a conductor 2da which will later become an external electrode. Also, hole 3
A portion 24' of the wiring connecting the wire bond pad 23 and the conductor 26', which will later become an external electrode, is located at a portion 6. The forming method is as follows: First, holes are made by press working in an insulating plate made of heat-resistant glass epoxy or the like having a thickness of about 0.1 to 0.3 B, and the first insulating plate 21 and the second insulating plate 21' are formed.
form. At this time, if the production method is to process the tape by winding it into a roll, the width of the insulating plate should be 30 to 80 mm.
A guide hole (sprocket hole) on the outside.
Form it. Next, on one side of the insulating board, copper, AI! ,
Attach a metal foil such as Ni using an adhesive such as epoxy. The thickness of the metal foil is usually 9 to 70 mm. It is about ym. Next, remove unnecessary metal foil by etching,
Die pad 22° wire bond pad 23. Wiring 24.
24', and a conductor 25' which will later become an external electrode is formed. If the metal foil is copper, it is etched using a solution such as ferric chloride. Width of wire bond bat "23 is 0.2 to 0.
．． It is about 6 resistant. The pitch of the conductors 26', which serve as external electrodes, is approximately 0.4 to 1 mm, and is determined by taking into consideration the electrode plate of the LSI chip to be mounted later, the dimensions of the package, and the ease of mounting. Finally, in order to improve the electrical connection and wire bonding properties with the back surface of the LSI chip, the die pad 2
2. 0.1 to 1/If to the wire bond pad 23
Au plating of about m.
後に外部電極となる導体２６′には、後の半田付けを容
易にする為に、１〜１０．ａｍ程度の半田メッキを施す
。The conductor 26', which will later become an external electrode, is coated with 1 to 10 to facilitate soldering later. Apply solder plating to am grade.
次に、第１図すに示す様に、ダイパッド２２上に、ダイ
ボンド樹脂２９を用い、ＬＳＩチップ２６を固着する。Next, as shown in FIG. 1, an LSI chip 26 is fixed onto the die pad 22 using die bond resin 29.
ダイボンド樹脂２９には、通常、Ａｑエポキシ等のペー
スト状の樹脂を用い、加熱硬化する。次に、ボンディン
グワイヤ２８を用い、ワイヤボンディングを行い、ＬＳ
Ｉチップ２６の電極２７とワイヤボンドパッド２３を電
気的に接続する。ボンディングワイヤ２８には、径が２
０〜６０．ｘｍ程度のＡｕ、Ａ１等を用いる。Ａｕワイ
ヤを用いた場合のボンディング方式としては、低温（１
２０〜２００℃）でのボンディングが可能な超音波熱圧
着方式が適している。その後、ＬＳＩテップ２６を覆う
様に、封止樹脂３０を形成し、封止する。封止は、エポ
キシあるいはシリコーン等の液状樹脂を用いボッティン
グ等により形成し、加熱硬化して行う。液状樹脂以外で
は、Ｂステージのエボキシベレノトを用いて行う方法も
ある。The die-bonding resin 29 is usually a paste-like resin such as Aq epoxy, and is cured by heating. Next, wire bonding is performed using the bonding wire 28, and the LS
The electrode 27 of the I-chip 26 and the wire bond pad 23 are electrically connected. The bonding wire 28 has a diameter of 2
0-60. Au, A1, etc. of about xm are used. As a bonding method when using Au wire, low temperature (1
An ultrasonic thermocompression bonding method that allows bonding at a temperature of 20 to 200°C is suitable. Thereafter, a sealing resin 30 is formed to cover the LSI tip 26 and is sealed. The sealing is performed by botting or the like using a liquid resin such as epoxy or silicone, and then heating and curing. In addition to liquid resins, there is also a method using B-stage epoxyberenote.
本実施例では、第１の絶縁板の全領域に封止樹脂３ｏを
形成したが、ボンディングワイヤ２８を含む、ＬＳＩテ
ップ２６の周囲のみでもかまわない。In this embodiment, the sealing resin 3o is formed over the entire area of the first insulating plate, but the sealing resin 3o may be formed only around the LSI tip 26 including the bonding wire 28.
最後に、第２図すの切断線３４の位置で、基板を切断し
、その後、第２図Ｃに示すように、第２の絶縁板２１′
が、第１の絶縁板２１の裏面に位置する様に、第１の絶
縁板２１から突出した配線２４′を折り曲げ、第１の絶
縁板２１の裏面に、外部電極２５を形成する。配線２４
′の折り曲げは、金型等を用いて、４辺の７オーミンク
を行う。この時、配線２４′は、３５μｍ程度の薄いも
のである為、容易に折り曲げることができる。また、外
部電極２５が、第２の絶縁板２１′で保持されている為
、従来のような外部電極の変形、不ぞろい。Finally, the substrate is cut at the cutting line 34 in FIG. 2C, and then the second insulating plate 21'
The wiring 24' protruding from the first insulating plate 21 is bent so that it is located on the back side of the first insulating plate 21, and the external electrode 25 is formed on the back side of the first insulating plate 21. Wiring 24
For the bending, use a mold or the like to form a 7-ohm mink on the four sides. At this time, since the wiring 24' is thin, about 35 μm, it can be easily bent. Further, since the external electrode 25 is held by the second insulating plate 21', the external electrode is not deformed or uneven as in the conventional case.
浮き等は発生しない。また、本実施例では、第１の絶縁
板２１と第２の絶縁板２１′を接着しなかったが、接着
剤を用いて接着してもよい。No floating occurs. Further, in this embodiment, the first insulating plate 21 and the second insulating plate 21' were not bonded together, but they may be bonded together using an adhesive.
プリント基板への実装例を、第６図に示す。半田付けの
方法は、プリント基板３１の半田付はパッド３３上に、
半田ペーストを印刷した後、パッケージを搭載し、リフ
ローする。この時外部電極の変形、不ぞろい、浮きがな
い為、半田付けが大変容易であり、歩留りがよく、信頼
性の高い接続を得ることができる。また、半田３２は、
外部電極２６及び配線２４′にも、付着する為、半田付
は後の、目視検査が容易である。また、パッケージとプ
リント基板３３０間に、０．３〜０．５ｗ程度の間隙が
ある為、フラックス、半田ボールの、洗浄での除去が容
易であり、耐熱応力性も高い。An example of mounting on a printed circuit board is shown in FIG. The soldering method is to solder the printed circuit board 31 onto the pad 33,
After printing the solder paste, mount the package and reflow. At this time, since there is no deformation, irregularity, or floating of the external electrode, soldering is very easy, and a connection with high yield and reliability can be obtained. Moreover, the solder 32 is
Since it also adheres to the external electrode 26 and wiring 24', visual inspection after soldering is easy. Further, since there is a gap of about 0.3 to 0.5 W between the package and the printed circuit board 330, flux and solder balls can be easily removed by cleaning, and the heat stress resistance is also high.
薄形でかつ、樹脂製のパッケージは一般的には耐湿性が
劣る。本実施例においては実施しなかったが、耐湿性を
向上させる策としては、絶縁板２１の裏面にも、金属箔
をはりつけておく、封止樹脂の上面に、金属箔、金属板
を接着することによりパッケージ内への水分の浸入を防
ぐ方法等がある。Packages that are thin and made of resin generally have poor moisture resistance. Although not implemented in this example, measures to improve moisture resistance include pasting metal foil on the back side of the insulating plate 21 as well, and bonding metal foil and a metal plate to the top surface of the sealing resin. There are methods to prevent moisture from entering the package.
また、本実施例では、ＬＳＩチップの組み込みを、ワイ
ヤボンド方式を用いて行ったが、金属バンプを介してリ
ードと接続する、テープキャリヤ方式等でもかまわない
。Further, in this embodiment, the LSI chip was assembled using a wire bonding method, but a tape carrier method or the like in which the LSI chip is connected to the leads via metal bumps may also be used.
搭載する電子部品は、ＩＣ、ＬＳ Ｉに限らずチップ抵
抗、コンデンサ等も使用できる。The electronic components to be mounted are not limited to ICs and LSIs, but can also include chip resistors, capacitors, etc.
電子部品搭載基板を切断し、配線を折り曲げる工程を、
電子部品の組み込み後に実施したが、電子部品の組み込
み前に実施してもよい。The process of cutting the electronic component mounting board and bending the wiring,
Although this was carried out after the electronic parts were installed, it may be carried out before the electronic parts are installed.
発明の効果
本発明は、上記のような構成であり、以下に示す効果が
得られるものである。Effects of the Invention The present invention has the above-described configuration, and provides the following effects.
（１）外部電極が、絶縁板で保持されている為、外部電
極の、変形、不ぞろい、浮きが発生せず、プリント基板
への半田付は時において、短絡、接続不良等が発生しな
い。したがって、半田付けの歩留りが向上し、信頼性の
高い接続を得ることができる。(1) Since the external electrode is held by an insulating plate, the external electrode will not be deformed, uneven, or lifted, and short circuits, poor connections, etc. will not occur when soldering to a printed circuit board. Therefore, the soldering yield is improved and a highly reliable connection can be obtained.
に））外部電極をパッケージの裏面に形成する方法とし
て、スルーホールを形成せず、片面に形成した、導体を
折り曲げる方法としている為、コストが安い。B)) The method of forming the external electrode on the back side of the package is by bending the conductor formed on one side without forming a through hole, so the cost is low.
（３）外部電極をパッケージの裏面に形成している為、
占有面積が小さく、高密度なパッケージを得ることがで
きる。(3) Since the external electrode is formed on the back of the package,
A high-density package with a small footprint can be obtained.
（４）折り曲げられた、配線がパッケージの側面に位置
し、半田付は時にこの部分にも半田が付着する。したが
って、半田付は後の目視検査が容易である。(4) The bent wiring is located on the side of the package, and sometimes solder adheres to this part as well. Therefore, soldering is easy to visually inspect later.
（５）外部電極をパッケージの裏面に、絶縁板ともに折
り曲げた為、プリント基板への実装後は、゛パッケージ
の裏面と、プリント基板の表面に、外部電極を保持した
、絶縁板の厚み以上（０，３〜０．５Ｍ）の間隙ができ
、半田付は後の洗浄において、フランクス、半田ボール
等の除去が容易となる。(5) Since the external electrodes were bent onto the back side of the package and the insulating plate together, after mounting on the printed circuit board, the thickness of the insulating plate holding the external electrodes on the back side of the package and the front surface of the printed circuit board ( A gap of 0.3 to 0.5 M) is created, and franks, solder balls, etc. can be easily removed during cleaning after soldering.
さらに、熱応力による半田付は部の破損もない。Furthermore, soldering due to thermal stress does not cause damage to the parts.
第１図〜第３図は、本発明の実施例であり、第１図は工
程別断面図、第２図はプリント基板への実装例の断面図
、第３図はその上面図、第４図〜第６図は、従来のＩＣ
，ＬＳＩの小形パッケージであり、第４図は上面図、第
５図は工程別断面図、第６図はフコリント基板への実装
例の断面図である。
１．１’、２１．２１’・・・・・・絶縁板、２，２２
・・・・・・グイパッド、３ 、２３’・・・・・・ワ
イヤボンドパッド、４．２４．２４’・・・・・・配線
、５，２６・・・・・・外部電極、５’、２５’・・・
・・・後に外部電極となる導体、６，２６・・・・・・
ＬＳＩチップ、７，２７・・・・・・ＬＳＩチップの電
極、８，２８・・・・・・ボンディングワイヤ、９，２
９・・・・・・ダイボンド樹脂、１ｏ、３０・・・・・
・封止樹脂、１１．３１・・・・・・プリント基板、１
２ 、３２・・団・半田、１３ 、３３・・・・・プリ
ント基板の半田付はパッド、１４．３４・・・・・・切
断線、３５・・印・穴。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名２ｆ
−−一才！のｊ！象シＪ
２５−−−デＬ１苧１喝：４シ１
２ｅ−ＬＳ Ｉ ｆｙア
第５図
第６図1 to 3 show examples of the present invention, in which FIG. 1 is a cross-sectional view by process, FIG. 2 is a cross-sectional view of an example of mounting on a printed circuit board, FIG. 3 is a top view thereof, and FIG. Figures 6 to 6 show conventional ICs.
, a small LSI package, FIG. 4 is a top view, FIG. 5 is a cross-sectional view by process, and FIG. 6 is a cross-sectional view of an example of mounting on a Fucorint board. 1.1', 21.21'... Insulating plate, 2, 22
...Gui pad, 3, 23'... Wire bond pad, 4.24.24'... Wiring, 5, 26... External electrode, 5' , 25'...
...Conductor that will later become the external electrode, 6, 26...
LSI chip, 7, 27... LSI chip electrode, 8, 28... Bonding wire, 9, 2
9...Die bond resin, 1o, 30...
・Sealing resin, 11.31...Printed circuit board, 1
2, 32... group/solder, 13, 33... pad for soldering on printed circuit board, 14. 34... cutting line, 35... mark/hole. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd floor
--One year old! Noj! Elephant Shi J 25 --- De L1 苧 1 Sake: 4 Shi 1 2e-LS I fyA Fig. 5 Fig. 6
Claims (2)
び内部電極と、内部電極から突出し、第１の絶縁板の外
周部に設けた第２の絶縁板上に形成した外部電極に接続
された配線と、電子部品搭載部に設けたＩＣ、ＬＳＩ等
の電子部品とを備え、電子部品の電極と内部電極とを電
気的に接続するとともに、第１の絶縁板から突出した前
記配線を折り曲げて、外部電極を有した第２の絶縁板を
、第１の絶縁板の内部電極を有さない面に位置させた電
子部品パッケージ。(1) An electronic component mounting part and an internal electrode provided on one main surface of the first insulating plate, and an external part protruding from the internal electrode and formed on the second insulating plate provided on the outer periphery of the first insulating plate. It includes wiring connected to the electrodes and electronic components such as ICs and LSIs provided in the electronic component mounting section, electrically connects the electrodes of the electronic components and internal electrodes, and protrudes from the first insulating plate. An electronic component package in which the wiring is bent and a second insulating plate having external electrodes is positioned on a surface of the first insulating plate that does not have internal electrodes.
電極を有し、内部電極から伸びた配線が、第１の絶縁板
から突出し、第１の絶縁板の外周部に設けた第２の絶縁
板上に形成した外部電極に接続され電子部品搭載部にＩ
Ｃ、ＬＳＩ等の電子部品を搭載する工程、電子部品の電
極と内部電極を電気的に接続する工程、外部電極を有し
た第２の絶縁板が、第１の絶縁板の内部電極を有さない
面に位置する様に第１の絶縁板から突出した配線を折り
曲げる工程よりなる電子部品パッケージの製造方法。(2) The first insulating plate has an electronic component mounting part and an internal electrode on one main surface, and the wiring extending from the internal electrode protrudes from the first insulating plate and is attached to the outer periphery of the first insulating plate. It is connected to the external electrode formed on the provided second insulating plate and is connected to the electronic component mounting part.
C, a step of mounting an electronic component such as an LSI, a step of electrically connecting an electrode of the electronic component and an internal electrode, a second insulating plate having an external electrode having an internal electrode of the first insulating plate; A method for manufacturing an electronic component package comprising the step of bending the wiring protruding from a first insulating plate so that it is located on a non-contact surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18212685A JPS6242549A (en) | 1985-08-20 | 1985-08-20 | Package for electronic part and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18212685A JPS6242549A (en) | 1985-08-20 | 1985-08-20 | Package for electronic part and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6242549A true JPS6242549A (en) | 1987-02-24 |
Family
ID=16112781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18212685A Pending JPS6242549A (en) | 1985-08-20 | 1985-08-20 | Package for electronic part and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6242549A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05211204A (en) * | 1991-11-29 | 1993-08-20 | Akira Kitahara | Surface mount electronic part |
| JPH08116017A (en) * | 1994-10-14 | 1996-05-07 | Nec Corp | Lead frame for semiconductor integrated circuit device and its manufacturing method |
| KR20010058572A (en) * | 1999-12-30 | 2001-07-06 | 마이클 디. 오브라이언 | semiconductor package and its mounting method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58161354A (en) * | 1982-03-19 | 1983-09-24 | Hitachi Ltd | Semiconductor device |
| JPS6025159B2 (en) * | 1983-04-11 | 1985-06-17 | 松下電器産業株式会社 | iron storage device |
-
1985
- 1985-08-20 JP JP18212685A patent/JPS6242549A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58161354A (en) * | 1982-03-19 | 1983-09-24 | Hitachi Ltd | Semiconductor device |
| JPS6025159B2 (en) * | 1983-04-11 | 1985-06-17 | 松下電器産業株式会社 | iron storage device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05211204A (en) * | 1991-11-29 | 1993-08-20 | Akira Kitahara | Surface mount electronic part |
| JPH08116017A (en) * | 1994-10-14 | 1996-05-07 | Nec Corp | Lead frame for semiconductor integrated circuit device and its manufacturing method |
| KR20010058572A (en) * | 1999-12-30 | 2001-07-06 | 마이클 디. 오브라이언 | semiconductor package and its mounting method |
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